Shawn Lin
365ee62df1
Native APCI support for PCIe need firmware to initialize HW and provide ECAM vectors via Mcfg and _CRS tables via root port descriptors. We implement UEFI as firmware to cover HW part, so this driver must be used under UEFI environment. DW IP isn't ECAM compatible so we provide RKCP0001 as HID to workaround ECAM scan, so that we can get DBI(_CRS) and Cfg space(_CBA) from ACPI. Cfg space should be different from Mcfg table for mapping. rk_pcie_ecam_ops is registered as quriks for accessing different cfg space in ACPI pcie lib. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Change-Id: I6a34768add6fd7030a187269955bcd6ed764c9e8
70 lines
2.3 KiB
C
70 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright 2016 Broadcom
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*/
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#ifndef DRIVERS_PCI_ECAM_H
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#define DRIVERS_PCI_ECAM_H
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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/*
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* struct to hold pci ops and bus shift of the config window
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* for a PCI controller.
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*/
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struct pci_config_window;
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struct pci_ecam_ops {
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unsigned int bus_shift;
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struct pci_ops pci_ops;
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int (*init)(struct pci_config_window *);
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};
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/*
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* struct to hold the mappings of a config space window. This
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* is expected to be used as sysdata for PCI controllers that
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* use ECAM.
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*/
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struct pci_config_window {
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struct resource res;
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struct resource busr;
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void *priv;
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const struct pci_ecam_ops *ops;
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union {
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void __iomem *win; /* 64-bit single mapping */
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void __iomem **winp; /* 32-bit per-bus mapping */
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};
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struct device *parent;/* ECAM res was from this dev */
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};
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/* create and free pci_config_window */
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struct pci_config_window *pci_ecam_create(struct device *dev,
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struct resource *cfgres, struct resource *busr,
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const struct pci_ecam_ops *ops);
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void pci_ecam_free(struct pci_config_window *cfg);
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/* map_bus when ->sysdata is an instance of pci_config_window */
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void __iomem *pci_ecam_map_bus(struct pci_bus *bus, unsigned int devfn,
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int where);
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/* default ECAM ops */
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extern const struct pci_ecam_ops pci_generic_ecam_ops;
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#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
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extern const struct pci_ecam_ops pci_32b_ops; /* 32-bit accesses only */
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extern const struct pci_ecam_ops pci_32b_read_ops; /* 32-bit read only */
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extern const struct pci_ecam_ops hisi_pcie_ops; /* HiSilicon */
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extern const struct pci_ecam_ops rk_pcie_ecam_ops; /* Rockchip */
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extern const struct pci_ecam_ops thunder_pem_ecam_ops; /* Cavium ThunderX 1.x & 2.x */
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extern const struct pci_ecam_ops pci_thunder_ecam_ops; /* Cavium ThunderX 1.x */
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extern const struct pci_ecam_ops xgene_v1_pcie_ecam_ops; /* APM X-Gene PCIe v1 */
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extern const struct pci_ecam_ops xgene_v2_pcie_ecam_ops; /* APM X-Gene PCIe v2.x */
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extern const struct pci_ecam_ops al_pcie_ops; /* Amazon Annapurna Labs PCIe */
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#endif
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#if IS_ENABLED(CONFIG_PCI_HOST_COMMON)
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/* for DT-based PCI controllers that support ECAM */
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int pci_host_common_probe(struct platform_device *pdev);
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int pci_host_common_remove(struct platform_device *pdev);
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#endif
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#endif
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