9403086898
If the DRAM frequency conversion jitters during the transmission process, it will cause the DMA to be unable to transport SPI FIFO data in a timely manner, resulting in FIFO overflow/underflow. Clear performance status for short cmd packet and Set the performance status for data packet. Change-Id: I65532ba309677a8d98c8277875a3bd358ca44e44 Signed-off-by: Jon Lin <jon.lin@rock-chips.com>