save changes

Signed-off-by: Heinrich Toews <ht@twx-software.de>

Documentation/devicetree/bindings/extcon/extcon-ptn5150.yaml

@@ -37,6 +37,12 @@ properties:
       GPIO pin (output) used to control VBUS. If skipped, no such control
       takes place.
 
+  vbus-supply:
+    maxItems: 1
+    description:
+      VBUS regulator used to control VBUS. If skipped, no such control
+      takes place.
+
 required:
   - compatible
   - interrupts

Documentation/devicetree/bindings/remoteproc/ti,k3-m4f-rproc.yaml

@@ -0,0 +1,125 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/remoteproc/ti,k3-m4f-rproc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI K3 M4F processor subsystems
+
+maintainers:
+  - Hari Nagalla <hnagalla@ti.com>
+  - Mathieu Poirier <mathieu.poirier@linaro.org>
+
+description: |
+  Some K3 family SoCs have Arm Cortex M4F cores. AM64x is a SoC in K3
+  family with a M4F core. Typically safety oriented applications may use
+  the M4F core in isolation without an IPC. Where as some industrial and
+  home automation applications, may use the M4F core as a remote processor
+  with IPC communications.
+
+$ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
+
+properties:
+  compatible:
+    enum:
+      - ti,am64-m4fss
+
+  power-domains:
+    maxItems: 1
+
+  "#address-cells":
+    const: 2
+
+  "#size-cells":
+    const: 2
+
+  reg:
+    items:
+      - description: IRAM internal memory region
+      - description: DRAM internal memory region
+
+  reg-names:
+    items:
+      - const: iram
+      - const: dram
+
+  resets:
+    maxItems: 1
+
+  firmware-name:
+    maxItems: 1
+    description: Name of firmware to load for the M4F core
+
+  mboxes:
+    description:
+      OMAP Mailbox specifier denoting the sub-mailbox, to be used for
+      communication with the remote processor. This property should match
+      with the sub-mailbox node used in the firmware image.
+    maxItems: 1
+
+  memory-region:
+    description:
+      phandle to the reserved memory nodes to be associated with the
+      remoteproc device. Optional memory regions available for firmware
+      specific purposes.
+      (see reserved-memory/reserved-memory.yaml in dtschema project)
+    maxItems: 8
+    items:
+      - description: regions used for DMA allocations like vrings, vring buffers
+                     and memory dedicated to firmware's specific purposes.
+    additionalItems: true
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - ti,sci
+  - ti,sci-dev-id
+  - ti,sci-proc-ids
+  - resets
+  - firmware-name
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    reserved-memory {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        mcu_m4fss_dma_memory_region: m4f-dma-memory@9cb00000 {
+            compatible = "shared-dma-pool";
+            reg = <0x00 0x9cb00000 0x00 0x100000>;
+            no-map;
+        };
+
+        mcu_m4fss_memory_region: m4f-memory@9cc00000 {
+            compatible = "shared-dma-pool";
+            reg = <0x00 0x9cc00000 0x00 0xe00000>;
+            no-map;
+        };
+    };
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        mailbox0_cluster0: mailbox-0 {
+            #mbox-cells = <1>;
+        };
+
+        remoteproc@5000000 {
+            compatible = "ti,am64-m4fss";
+            reg = <0x00 0x5000000 0x00 0x30000>,
+                  <0x00 0x5040000 0x00 0x10000>;
+            reg-names = "iram", "dram";
+            resets = <&k3_reset 9 1>;
+            firmware-name = "am62-mcu-m4f0_0-fw";
+            mboxes = <&mailbox0_cluster0>, <&mbox_m4_0>;
+            memory-region = <&mcu_m4fss_dma_memory_region>,
+                            <&mcu_m4fss_memory_region>;
+            ti,sci = <&dmsc>;
+            ti,sci-dev-id = <9>;
+            ti,sci-proc-ids = <0x18 0xff>;
+         };
+    };

arch/arm/boot/dts/st/stm32mp153-cc100-v2.dts

@@ -31,6 +31,21 @@ SLB9670: SLB9670@0 {
 	};
 };
 
+&i2c4 {
+	cc_logic_usb_c_1: cclogic@1d {
+		compatible = "nxp,ptn5150";
+		reg = <0x1d>;
+		int-gpio = <&gpioh 3 GPIO_ACTIVE_LOW>;
+		vbus-supply = <&vbus_otg>;
+
+		port {
+			con_usbotg_hs_ep_1: endpoint {
+				remote-endpoint = <&usbotg_hs_ep>;
+			};
+		};
+	};
+};
+
 &usbotg_hs {
         status = "okay";
 };

arch/arm/boot/dts/wago-devconf.dtsi

@@ -53,14 +53,18 @@
  * |            100a |   PFC 750-8110/8111 |
  * |            100b |        PFC 750-8112 |
  * |            100c |    AOPT 6" 762-3406 |
+ * |            100c |        PFC 750-8302 |
+ * |            100d |        PFC 750-8400 |
+ * |            100e |  WP410-RRS 762-3407 |
  * |            1010 |         EC 752-8303 |
  * |            1011 |      CC100 751-9301 |
  * |            1012 |   CC100 V2 751-9402 |
  * |            1013 |  CC100 CAN 751-9401 |
  * |            1014 |  CC100 TPM 751-9301 |
  * |            1015 |  WP400  7" 762-3403 |
-* |            1016 |  WP400 10" 762-3404 |
-* |            1017 |  WP400 15" 762-3405 |
+ * |            1016 |  WP400 10" 762-3404 |
+ * |            1017 |  WP400 15" 762-3405 |
+ * |            1018 | CC100 DALI 751-9403 |
  * |-----------------|---------------------|
  *
  * ============== LEGACY FORMAT ================================================

arch/arm64/boot/dts/ti/Makefile

@@ -24,7 +24,8 @@ dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk.dtb
 dtb-$(CONFIG_ARCH_K3) += k3-am625-sk-hdmi-audio.dtb
 dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk-hdmi-audio.dtb
 dtb-$(CONFIG_ARCH_K3) += k3-am623-pfc-750-8302.dtb
-dtb-$(CONFIG_ARCH_K3) += k3-am623-pfc-ems.dtb
+dtb-$(CONFIG_ARCH_K3) += k3-am623-pfc-750-830x-ems.dtb
+dtb-$(CONFIG_ARCH_K3) += k3-am623-pfc-750-8400.dtb
 
 # Boards with AM62Ax SoC
 dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk.dtb

arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi

@@ -171,4 +171,17 @@ mcu_mcan1: can@4e18000 {
 		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 		status = "disabled";
 	};
+
+	mcu_m4fss: m4fss@5000000 {
+		compatible = "ti,am64-m4fss";
+		reg = <0x00 0x5000000 0x00 0x30000>,
+		      <0x00 0x5040000 0x00 0x10000>;
+		reg-names = "iram", "dram";
+		resets = <&k3_reset 9 1>;
+		firmware-name = "am62-mcu-m4f0_0-fw";
+		ti,sci = <&dmsc>;
+		ti,sci-dev-id = <9>;
+		ti,sci-proc-ids = <0x18 0xff>;
+		status = "disabled";
+	};
 };

arch/arm64/boot/dts/ti/k3-am623-pfc-750-8302.dts

@@ -6,12 +6,22 @@
  * Copyright (C) 2024 WAGO GmbH & Co. KG - https://www.wago.com/
  */
 
-#include "k3-am62x-pfc.dtsi"
+#include "k3-am623-pfc-750-8xxx-common.dtsi"
+#include "k3-am623-pfc-750-830x-common.dtsi"
+#include "k3-am623-pfc-kbus.dtsi"
+#include "k3-am623-pfc-rs485.dtsi"
+#include "k3-am623-pfc-tpm.dtsi"
+#include "k3-am623-pfc-rtc.dtsi"
 
 / {
 	model = "WAGO PFC300 750-8302";
 	compatible = "ti,am623-pfc", "ti,am625";
 
+	aliases {
+		ethernet0 = &cpsw_port1;
+		ethernet1 = &cpsw_port2;
+	};
+
         cpus {
                 cpu-map {
                         cluster0 {
@@ -31,10 +41,197 @@ cpu@1 {
                 /delete-node/ cpu@2;
                 /delete-node/ cpu@3;
         };
+
+	memory@80000000 {
+		device_type = "memory";
+		/* 2G RAM */
+		reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
+
+	};
+
+	/* this name of the gpio-keys device is a
+	 * historical heritage from 3.6.11 kernel.
+	 * the device-name is checked in omsd. So we
+	 * need to adapt this configuration
+	 */
+	oms: PAC-Operating-Mode-Switch {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&oms_pins_default>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		autorepeat;
+
+		oms_run: run {
+			label = "RUN";
+			gpios = <&main_gpio0 65 GPIO_ACTIVE_LOW>;
+			linux,code = <1>;
+			linux,input-type = <5>;
+			debounce-interval = <1>;
+		};
+
+		oms_stop: stop {
+			label = "STOP";
+			gpios = <&main_gpio1 10 GPIO_ACTIVE_LOW>;
+			linux,code = <2>;
+			linux,input-type = <5>;
+			debounce-interval = <1>;
+		};
+
+		oms_reset: reset {
+			label = "RESET";
+			gpios = <&main_gpio1 12 GPIO_ACTIVE_LOW>;
+			linux,code = <3>;
+			linux,input-type = <1>;
+			debounce-interval = <1>;
+		};
+
+		oms_reset_all: reset_all {
+			label = "RESET_ALL";
+			gpios = <&main_gpio1 11 GPIO_ACTIVE_HIGH>;
+			linux,code = <4>;
+			linux,input-type = <1>;
+			debounce-interval = <1>;
+		};
+	};
+
+	uio_nvram: nvram@51000000 {
+		compatible = "uio_pdrv_genirq";
+		linux,uio-name = "UIO_NVRAM";
+		reg = <0 0x51000000 0 0x00020000>; /* 128k 16bit NVRAM */
+	};
+
+	vdd_mmc1: regulator-3 {
+		compatible = "regulator-fixed";
+	 	pinctrl-names = "default";
+	 	pinctrl-0 = <&vdd_sd_dv_pins_default>;
+		regulator-name = "vdd_mmc1";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		vin-supply = <&vcc_3v3_sys>;
+		gpio = <&main_gpio0 31 GPIO_ACTIVE_LOW>;
+		enable-active-high;
+		startup-delay-us = <5000>;
+	};
+};
+
+&mcu_pmx0 {
+	gpmc_data_pins_default: gpmc-data-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x00bc, PIN_OUTPUT, 1) /* (V24) VOUT0_DATA1.GPMC0_A1    */
+			AM62X_IOPAD(0x00c0, PIN_OUTPUT, 1) /* (W25) VOUT0_DATA2.GPMC0_A2    */
+			AM62X_IOPAD(0x00c4, PIN_OUTPUT, 1) /* (W24) VOUT0_DATA3.GPMC0_A3    */
+			AM62X_IOPAD(0x00c8, PIN_OUTPUT, 1) /* (Y25) VOUT0_DATA4.GPMC0_A4    */
+			AM62X_IOPAD(0x00cc, PIN_OUTPUT, 1) /* (Y24) VOUT0_DATA5.GPMC0_A5    */
+			AM62X_IOPAD(0x00d0, PIN_OUTPUT, 1) /* (Y23) VOUT0_DATA6.GPMC0_A6    */
+			AM62X_IOPAD(0x00d4, PIN_OUTPUT, 1) /* (AA25) VOUT0_DATA7.GPMC0_A7   */
+			AM62X_IOPAD(0x00d8, PIN_OUTPUT, 1) /* (V21) VOUT0_DATA8.GPMC0_A8    */
+			AM62X_IOPAD(0x00dc, PIN_OUTPUT, 1) /* (W21) VOUT0_DATA9.GPMC0_A9    */
+			AM62X_IOPAD(0x00e0, PIN_OUTPUT, 1) /* (V20) VOUT0_DATA10.GPMC0_A10  */
+			AM62X_IOPAD(0x00e4, PIN_OUTPUT, 1) /* (AA23) VOUT0_DATA11.GPMC0_A11 */
+			AM62X_IOPAD(0x00e8, PIN_OUTPUT, 1) /* (AB25) VOUT0_DATA12.GPMC0_A12 */
+			AM62X_IOPAD(0x00ec, PIN_OUTPUT, 1) /* (AA24) VOUT0_DATA13.GPMC0_A13 */
+			AM62X_IOPAD(0x00f0, PIN_OUTPUT, 1) /* (Y22) VOUT0_DATA14.GPMC0_A14  */
+			AM62X_IOPAD(0x00f4, PIN_OUTPUT, 1) /* (AA21) VOUT0_DATA15.GPMC0_A15 */
+			AM62X_IOPAD(0x00f8, PIN_OUTPUT, 1) /* (AB24) VOUT0_HSYNC.GPMC0_A16  */
+		>;
+	};
+
+	gpmc_addr_pins_default: gpmc-addr-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x003c, PIN_INPUT, 0) /* (M25) GPMC0_AD0  */
+			AM62X_IOPAD(0x0040, PIN_INPUT, 0) /* (N23) GPMC0_AD1  */
+			AM62X_IOPAD(0x0044, PIN_INPUT, 0) /* (N24) GPMC0_AD2  */
+			AM62X_IOPAD(0x0048, PIN_INPUT, 0) /* (N25) GPMC0_AD3  */
+			AM62X_IOPAD(0x004c, PIN_INPUT, 0) /* (P24) GPMC0_AD4  */
+			AM62X_IOPAD(0x0050, PIN_INPUT, 0) /* (P22) GPMC0_AD5  */
+			AM62X_IOPAD(0x0054, PIN_INPUT, 0) /* (P21) GPMC0_AD6  */
+			AM62X_IOPAD(0x0058, PIN_INPUT, 0) /* (R23) GPMC0_AD7  */
+			AM62X_IOPAD(0x005c, PIN_INPUT, 0) /* (R24) GPMC0_AD8  */
+			AM62X_IOPAD(0x0060, PIN_INPUT, 0) /* (R25) GPMC0_AD9  */
+			AM62X_IOPAD(0x0064, PIN_INPUT, 0) /* (T25) GPMC0_AD10 */
+			AM62X_IOPAD(0x0068, PIN_INPUT, 0) /* (R21) GPMC0_AD11 */
+			AM62X_IOPAD(0x006c, PIN_INPUT, 0) /* (T22) GPMC0_AD12 */
+			AM62X_IOPAD(0x0070, PIN_INPUT, 0) /* (T24) GPMC0_AD13 */
+			AM62X_IOPAD(0x0074, PIN_INPUT, 0) /* (U25) GPMC0_AD14 */
+			AM62X_IOPAD(0x0078, PIN_INPUT, 0) /* (U24) GPMC0_AD15 */
+		>;
+	};
+
+	gpmc_ctrl_pins_default: gpmc-ctrl-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x0094, PIN_OUTPUT, 0) /* (N20) GPMC0_BE1n     */
+			AM62X_IOPAD(0x00a8, PIN_OUTPUT, 0) /* (M21) GPMC0_CSn0     */
+			AM62X_IOPAD(0x0088, PIN_OUTPUT, 0) /* (L24) GPMC0_OEn_REn  */
+			AM62X_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L25) GPMC0_WEn      */
+			AM62X_IOPAD(0x0090, PIN_OUTPUT, 0) /* (M24) GPMC0_BE0n_CLE */
+		>;
+	};
+
+	main_mdio1_pins_default: main-mdio1-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x160,  PIN_OUTPUT,       0) /* (AD24) MDIO0_MDC */
+			AM62X_IOPAD(0x15c,  PIN_INPUT_PULLUP, 0) /* (AB22) MDIO0_MDIO */
+			AM62X_IOPAD(0x019c, PIN_OUTPUT,       7) /* (B18) MCASP0_AXR1.GPIO1_9 */
+		>;
+	};
+
+	main_rgmii1_pins_default: main-rgmii1-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x14c, PIN_INPUT,  0) /* (AB17) RGMII1_RD0 */
+			AM62X_IOPAD(0x150, PIN_INPUT,  0) /* (AC17) RGMII1_RD1 */
+			AM62X_IOPAD(0x154, PIN_INPUT,  0) /* (AB16) RGMII1_RD2 */
+			AM62X_IOPAD(0x158, PIN_INPUT,  0) /* (AA15) RGMII1_RD3 */
+			AM62X_IOPAD(0x148, PIN_INPUT,  0) /* (AD17) RGMII1_RXC */
+			AM62X_IOPAD(0x144, PIN_INPUT,  0) /* (AE17) RGMII1_RX_CTL */
+			AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */
+			AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */
+			AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */
+			AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */
+			AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */
+			AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */
+			AM62X_IOPAD(0x0030, PIN_INPUT, 7) /* (G21) OSPI0_CSn1.GPIO0_12 nINT-RGMII1 */
+		>;
+	};
+
+	main_rgmii2_pins_default: main-rgmii2-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x184, PIN_INPUT,  0) /* (AE23) RGMII2_RD0 */
+			AM62X_IOPAD(0x188, PIN_INPUT,  0) /* (AB20) RGMII2_RD1 */
+			AM62X_IOPAD(0x18c, PIN_INPUT,  0) /* (AC21) RGMII2_RD2 */
+			AM62X_IOPAD(0x190, PIN_INPUT,  0) /* (AE22) RGMII2_RD3 */
+			AM62X_IOPAD(0x180, PIN_INPUT,  0) /* (AD23) RGMII2_RXC */
+			AM62X_IOPAD(0x17c, PIN_INPUT,  0) /* (AD22) RGMII2_RX_CTL */
+			AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */
+			AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */
+			AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */
+			AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */
+			AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */
+			AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */
+			AM62X_IOPAD(0x0034, PIN_INPUT, 7) /* (H21) OSPI0_CSn2.GPIO0_13 */
+		>;
+	};
+
+	vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */
+		>;
+	};
+
+	oms_pins_default: oms-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x0108, PIN_INPUT, 7) /* (D24) MMC2_DAT3.GPIO0_65 */
+			AM62X_IOPAD(0x01a0, PIN_INPUT, 7) /* (E18) MCASP0_AXR0.GPIO1_10 */
+			AM62X_IOPAD(0x01a8, PIN_INPUT, 7) /* (D20) MCASP0_AFSX.GPIO1_12 */
+			AM62X_IOPAD(0x01a4, PIN_INPUT, 7) /* (B20) MCASP0_ACLKX.GPIO1_11 */
+		>;
+	};
 };
 
 &wsysinit {
 	status = "okay";
+        board,variant = "pfc300";
 };
 
 &oms {
@@ -51,6 +248,42 @@ &watchdog_ext {
 
 &gpmc0 {
 	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&gpmc_data_pins_default>, <&gpmc_addr_pins_default>, <&gpmc_ctrl_pins_default>;
+
+	num-cs = <4>;
+	num-waitpins = <4>;
+	ranges = <
+		0 0 0x00 0x51000000 0x01000000	/* CS0: NVRAM, 16M */
+	>;
+
+	nvram: nor@0,0 { /* NVRAM Device 128k */
+		reg = <0 0 0x01000000>;
+		bank-width = <2>; /* 1: 8bit, 2: 16bit */
+		gpmc,sync-clk-ps = <0>;
+		gpmc,cs-on-ns = <0>;
+		gpmc,cs-rd-off-ns = <50>;
+		gpmc,cs-wr-off-ns = <30>;
+		gpmc,adv-on-ns = <0>;
+		gpmc,adv-rd-off-ns = <0>;
+		gpmc,adv-wr-off-ns = <0>;
+		gpmc,oe-on-ns = <0>;
+		gpmc,oe-off-ns = <50>;
+		gpmc,we-on-ns = <0>;
+		gpmc,we-off-ns = <30>;
+		gpmc,rd-cycle-ns = <50>;
+		gpmc,wr-cycle-ns = <30>;
+		gpmc,access-ns = <40>;
+		gpmc,wr-access-ns = <10>;
+		gpmc,wr-data-mux-bus-ns = <0>;
+		gpmc,cycle2cycle-delay-ns = <10>;
+		gpmc,cycle2cycle-samecsen;
+		gpmc,cycle2cycle-diffcsen;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+	};
 };
 
 &main_uart0 {
@@ -87,22 +320,56 @@ &sdhci0 { /* eMMC */
 
 &sdhci1 { /* SD */
 	status = "okay";
+
+	vmmc-supply = <&vdd_mmc1>;
+
+	cap-sd-highspeed;
+	no-1-8-v;
 };
 
 &cpsw3g {
 	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_mdio1_pins_default
+		     &main_rgmii1_pins_default
+		     &main_rgmii2_pins_default>;
 };
 
 &cpsw_port1 {
 	status = "okay";
+	phy-mode = "rgmii-rxid";
+	phy-handle = <&cpsw3g_phy0>;
 };
 
 &cpsw_port2 {
 	status = "okay";
+	phy-mode = "rgmii-rxid";
+	phy-handle = <&cpsw3g_phy1>;
 };
 
 &cpsw3g_mdio {
 	status = "okay";
+
+        reset-gpios = <&main_gpio1 9 GPIO_ACTIVE_LOW>;
+        reset-delay-us = <10>;
+        reset-post-delay-us = <10000>;
+
+	cpsw3g_phy0: ethernet-phy@0 {
+		// ADIN1300
+		compatible = "ethernet-phy-id0283.bc30";
+
+		reg = <0>;
+		adi,rx-internal-delay-ps = <2000>;
+	};
+
+	cpsw3g_phy1: ethernet-phy@1 {
+		// ADIN1300
+		compatible = "ethernet-phy-id0283.bc30";
+
+		reg = <1>;
+		adi,rx-internal-delay-ps = <2000>;
+	};
 };
 
 &usbss0 {

arch/arm64/boot/dts/ti/k3-am623-pfc-750-830x-common.dtsi

@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0
+
+&main_i2c0 {
+
+        #include "k3-am623-pfc-750-830x-leds.dtsi"
+
+	tps65219_30: pmic@30 {
+		compatible = "ti,tps65219";
+		reg = <0x30>;
+		system-power-controller;
+
+		buck1-supply = <&vcc_5v0>;
+		buck2-supply = <&vcc_5v0>;
+		buck3-supply = <&vcc_5v0>;
+		ldo1-supply = <&vcc_3v3_sys>;
+		ldo2-supply = <&vcc_3v3_sys>;
+		ldo3-supply = <&vcc_5v0>;
+		ldo4-supply = <&vcc_5v0>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_irq_pins_default>;
+
+		interrupt-parent = <&main_gpio0>;
+		interrupts = <68 IRQ_TYPE_EDGE_FALLING>;
+
+		regulators {
+			buck1_30_reg: buck1 {
+				regulator-name = "VDD_CORE";
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <850000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck2_30_reg: buck2 {
+				regulator-name = "VCC1V8_SYS";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck3_30_reg: buck3 {
+				regulator-name = "VCC3V3_SYS";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo1_30_reg: ldo1 {
+				regulator-name = "VCC3V3_SDC";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			ldo2_30_reg: ldo2 {
+				regulator-name = "VDDA_1V8";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+

arch/arm64/boot/dts/ti/k3-am623-pfc-750-830x-ems.dts

@@ -6,7 +6,8 @@
  * Copyright (C) 2024 WAGO GmbH & Co. KG - https://www.wago.com/
  */
 
-#include "k3-am62x-pfc.dtsi"
+#include "k3-am623-pfc-750-8xxx-common.dtsi"
+#include "k3-am623-pfc-750-830x-common.dtsi"
 
 / {
 	model = "WAGO AM623 PFC EMS";
@@ -460,14 +461,6 @@ &wsysinit {
 	status = "okay";
 };
 
-&oms {
-	status = "disabled";
-};
-
-&nvram {
-	status = "okay";
-};
-
 &watchdog_ext {
 	status = "okay";
 };
@@ -509,9 +502,6 @@ &sdhci1 { /* SD */
 	status = "disabled";
 };
 
-/delete-node/ &vdd_mmc1;
-/delete-node/ &vdd_sd_dv_pins_default;
-
 &cpsw3g {
 	status = "disabled";
 };

arch/arm64/boot/dts/ti/k3-am623-pfc-750-830x-leds.dtsi

@@ -0,0 +1,143 @@
+// SPDX-License-Identifier: GPL-2.0
+
+led_bar60: pca9552@60 {
+        compatible = "nxp,pca9552";
+        #address-cells = <1>;
+        #size-cells = <0>;
+        reg = <0x60>;
+
+        lb60_0: sys-red@0 {
+                label = "sys-red";
+                reg = <0>;
+                linux,default-trigger = "timer";
+        };
+
+        lb60_1: sys-green@1 {
+                label = "sys-green";
+                reg = <1>;
+                linux,default-trigger = "timer";
+        };
+
+        lb60_2: run-red@2 {
+                label = "run-red";
+                reg = <2>;
+        };
+
+        lb60_3: run-green@3 {
+                label = "run-green";
+                reg = <3>;
+        };
+
+        lb60_4: io-red@4 {
+                label = "io-red";
+                reg = <4>;
+        };
+
+        lb60_5: io-green@5 {
+                label = "io-green";
+                reg = <5>;
+        };
+
+        lb60_6: ms-red@6 {
+                label = "ms-red";
+                reg = <6>;
+        };
+
+        lb60_7: ms-green@7 {
+                label = "ms-green";
+                reg = <7>;
+        };
+
+        lb60_8: ns-red@8 {
+                label = "ns-red";
+                reg = <8>;
+        };
+
+        lb60_9: ns-green@9 {
+                label = "ns-green";
+                reg = <9>;
+        };
+
+        lb60_10: usr_r@10 {
+                label = "trm-red";
+                reg = <10>;
+        };
+
+        lb60_11: usr_g@11 {
+                label = "trm-green";
+                reg = <11>;
+        };
+
+        lb60_15: sys-over-red@15 {
+                label = "sys-over-red";
+                reg = <15>;
+                linux,default-trigger = "default-on";
+        };
+};
+
+led_bar61: pca9552@61 {
+        compatible = "nxp,pca9552";
+        #address-cells = <1>;
+        #size-cells = <0>;
+        reg = <0x61>;
+
+        lb61_0: u6-red@0 {
+                label = "u6-red";
+                reg = <0>;
+        };
+
+        lb61_1: u6-green@1 {
+                label = "u6-green";
+                reg = <1>;
+        };
+
+        lb61_2: u5-red@2 {
+                label = "u5-red";
+                reg = <2>;
+        };
+
+        lb61_3: u5-green@3 {
+                label = "u5-green";
+                reg = <3>;
+        };
+
+        lb61_4: u4-red@4 {
+                label = "u4-red";
+                reg = <4>;
+        };
+
+        lb61_5: u4-green@5 {
+                label = "u4-green";
+                reg = <5>;
+        };
+
+        lb61_6: u3-red@6 {
+                label = "u3-red";
+                reg = <6>;
+        };
+
+        lb61_7: u3-green@7 {
+                label = "u3-green";
+                reg = <7>;
+        };
+
+        lb61_8: u2-red@8 {
+                label = "u2-red";
+                reg = <8>;
+        };
+
+        lb61_9: u2-green@9 {
+                label = "u2-green";
+                reg = <9>;
+        };
+
+        lb61_10: u1-red@10 {
+                label = "u1-red";
+                reg = <10>;
+        };
+
+        lb61_11: u1-green@11 {
+                label = "u1-green";
+                reg = <11>;
+        };
+};

arch/arm64/boot/dts/ti/k3-am623-pfc-750-8400.dts

@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PFC400 - AM62x based WAGO device
+ *
+ * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2025 WAGO GmbH & Co. KG - https://www.wago.com/
+ */
+
+#include "k3-am623-pfc-750-84xx-wosm.dtsi"
+#include "k3-am623-pfc-750-84xx-baseboard.dtsi"
+#include "k3-am623-pfc-750-84xx-kbus.dtsi"
+#include "k3-am623-pfc-750-84xx-interaction.dtsi"
+
+&wsysinit {
+	status = "okay";
+        board,variant = "pfc400";
+};

arch/arm64/boot/dts/ti/k3-am623-pfc-750-84xx-baseboard.dtsi

@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+* PFC400 baseboard dtsi for AM62x based WAGO devices
+*
+* Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
+* Copyright (C) 2025 WAGO GmbH & Co. KG - https://www.wago.com/
+*/
+
+&main_pmx0 {
+        main_ksz9477_pins: main-ksz9477-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x01a0, PIN_OUTPUT, 7) /* (E18) MCASP0_AXR0.GPIO1_10  nRST-RGMII2 / nRST-ETHSW (BB) */
+			AM62X_IOPAD(0x0034, PIN_INPUT, 7)  /* (H21) OSPI0_CSn2.GPIO0_13 nINT-RGMII2 / nINT-ETHSW(BB) */
+		>;
+        };
+};
+
+&mcu_spi0 {
+	ksz9477@0 {
+		compatible = "microchip,ksz9477";
+                pinctrl-names = "default";
+                pinctrl-0 = <&main_ksz9477_pins>;
+		reg = <0>;
+		spi-max-frequency = <1000000>;
+
+                reset-gpios = <&main_gpio1 10 GPIO_ACTIVE_LOW>;
+
+		dsa,member = <0 0>;
+
+		interrupt-parent = <&main_gpio0>;
+		interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				label = "ethX3";
+				phy-mode = "internal";
+			};
+
+			port@1 {
+				reg = <1>;
+				label = "ethX2";
+				phy-mode = "internal";
+			};
+
+			port@2 {
+				reg = <2>;
+				label = "ethX1";
+				phy-mode = "internal";
+			};
+
+			port@3 {
+				reg = <3>;
+				label = "ethEM";
+				phy-mode = "internal";
+			};
+
+			port@4 {
+				reg = <4>;
+				label = "ethX4";
+				phy-mode = "internal";
+			};
+
+			port@5 {
+                                reg = <5>;
+                                label = "cpu";
+                                ethernet = <&cpsw3g>; /* &eth0 */
+                                phy-mode = "rgmii-txid";
+				tx-internal-delay-ps = <2000>;
+
+                                fixed-link {
+                                    speed = <1000>;
+                                    full-duplex;
+                                };
+                        };
+                };
+        };
+};
+
+&main_i2c1 {
+	eeprom_hw_id_bb: at24c02@54 {
+		status = "disabled";
+		compatible = "atmel,24c02";
+		reg = <0x51>;
+		pagesize = <16>;
+	};
+};

arch/arm64/boot/dts/ti/k3-am623-pfc-750-84xx-interaction.dtsi

@@ -0,0 +1,140 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PFC400 interaction board dtsi for AM62x based WAGO devices
+ *
+ * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2025 WAGO GmbH & Co. KG - https://www.wago.com/
+ */
+
+#include "k3-am623-pfc-rs485.dtsi"
+#include "k3-am623-pfc-rtc.dtsi"
+
+&mcu_pmx0 {
+	led_reset_pins_default: led-reset-pins-default {
+		pinctrl-single,pins = <
+			AM62X_MCU_IOPAD(0x050, PIN_OUTPUT | INPUT_EN, 7)   /* (A9)  WKUP_I2C0_SDA.GPIO0_20 nRST-LED-DISP */
+		>;
+	};
+};
+
+&main_i2c1 {
+	status = "okay";
+
+	eeprom_hw_id_ib: at24c02@54 {
+		status = "disabled";
+		compatible = "atmel,24c02";
+		reg = <0x54>;
+		pagesize = <16>;
+	};
+
+        /*
+         * NXP PCA9552BS
+         * 16-Bit I²C-Bus LED Driver
+         */
+        led_bar60: pca9552@60 {
+                compatible = "nxp,pca9552";
+		pinctrl-names = "default";
+		pinctrl-0 = <&led_reset_pins_default>;
+
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg = <0x60>;
+
+                lb60_0: sys-red@0 {
+                        label = "sys-red";
+                        reg = <0>;
+                        linux,default-trigger = "timer";
+                };
+
+                lb60_1: sys-green@1 {
+                        label = "sys-green";
+                        reg = <1>;
+                        linux,default-trigger = "timer";
+                };
+
+                lb60_2: sys-blue@2 {
+                        label = "sys-blue";
+                        reg = <2>;
+                };
+
+                lb60_3: run-red@3 {
+                        label = "run-red";
+                        reg = <3>;
+                };
+
+                lb60_4: run-green@4 {
+                        label = "run-green";
+                        reg = <4>;
+                };
+
+                lb60_5: run-blue@5 {
+                        label = "run-blue";
+                        reg = <5>;
+                };
+
+                lb60_6: io-red@6 {
+                        label = "io-red";
+                        reg = <6>;
+                };
+
+                lb60_7: io-green@7 {
+                        label = "io-green";
+                        reg = <7>;
+                };
+
+                lb60_8: io-blue@8 {
+                        label = "io-blue";
+                        reg = <8>;
+                };
+
+                lb60_9: ms-red@9 {
+                        label = "ms-red";
+                        reg = <9>;
+                };
+
+                lb60_10: ms-green@10 {
+                        label = "ms-green";
+                        reg = <10>;
+                };
+
+                lb60_11: ms-blue@11 {
+                        label = "ms-blue";
+                        reg = <11>;
+                };
+
+                lb60_12: usr_r@12 {
+                        label = "trm-red";
+                        reg = <12>;
+                };
+
+                lb60_13: usr_g@13 {
+                        label = "trm-green";
+                        reg = <13>;
+                };
+
+                lb60_14: usr_b@14 {
+                        label = "trm-blue";
+                        reg = <14>;
+                };
+
+                lb60_15: sys-over-red@15 {
+                        label = "sys-over-red";
+                        reg = <15>;
+                        linux,default-trigger = "default-on";
+                };
+        };
+
+        /*
+         * Dynamic NFC/RFID tag IC with 4-Kbit EEPROM
+         *
+         * This driver is not yet upstream but there is a kernel driver available at:
+         * 
+         *      https://github.com/2pecshy/eeprom-ST25DV-linux-driver/tree/master
+         *
+         */
+        st25dv04k: st25dv04k@53 {
+                status = "okay";
+                compatible = "st25dv,st25dv04k";
+                reg = <0x53>;
+        };
+};

arch/arm64/boot/dts/ti/k3-am623-pfc-750-84xx-kbus.dtsi

@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Common dtsi for AM62x WAGO based devices
+ *
+ * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2025 WAGO GmbH & Co. KG - https://www.wago.com/
+ */
+
+#include "k3-am623-pfc-kbus.dtsi"
+
+/ {
+	/* this name of the gpio-keys device is a
+	 * historical heritage from 3.6.11 kernel.
+	 * the device-name is checked in omsd. So we
+	 * need to adapt this configuration
+	 */
+	oms: PAC-Operating-Mode-Switch {
+		status = "okay";
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&oms_pins_default>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		autorepeat;
+
+		oms_stop_run: stop_run {
+			label = "RUN";
+			gpios = <&main_gpio0 65 GPIO_ACTIVE_LOW>;
+			linux,code = <1>;
+			linux,input-type = <5>;
+			debounce-interval = <1>;
+		};
+
+		oms_reset_all: reset_all {
+			label = "RESET_ALL";
+			gpios = <&main_gpio1 11 GPIO_ACTIVE_HIGH>;
+			linux,code = <4>;
+			linux,input-type = <1>;
+			debounce-interval = <1>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = <&sd_activity_led_pin>;
+		pinctrl-names = "default";
+
+		led-0 {
+			function = LED_FUNCTION_SD;
+			color = <LED_COLOR_ID_ORANGE>;
+			gpios = <&main_gpio0 31 GPIO_ACTIVE_LOW>;
+			linux,default-trigger = "mmc0";
+			default-state = "on";
+		};
+	};
+};
+
+&main_pmx0 {
+	oms_pins_default: oms-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x0108, PIN_INPUT, 7) /* (D24) MMC2_DAT3.GPIO0_65     nSTOP-RUN */
+			AM62X_IOPAD(0x01a4, PIN_INPUT, 7) /* (B20) MCASP0_ACLKX.GPIO1_11  IO-RAB    */
+		>;
+	};
+
+	sd_activity_led_pin: sd-activity-led-pin {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 (MMC1.PWR / SDC.LED) */
+		>;
+	};
+};
+
+&main_i2c1 {
+	eeprom_hw_id_kbus: at24c02@50 {
+		status = "disabled";
+		compatible = "atmel,24c02";
+		reg = <0x50>;
+		pagesize = <16>;
+	};
+};

arch/arm64/boot/dts/ti/k3-am623-pfc-750-84xx-wosm.dtsi

@@ -0,0 +1,355 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PFC400 WOSM dtsi for AM62x based WAGO devices
+ *
+ * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2025 WAGO GmbH & Co. KG - https://www.wago.com/
+ */
+
+#include "k3-am623-pfc-750-8xxx-common.dtsi"
+#include "k3-am623-pfc-tpm.dtsi"
+
+/ {
+	model = "WAGO PFC400 750-8400";
+	compatible = "ti,am623-pfc", "ti,am625";
+
+	aliases {
+		usb1 = &usb1;
+		ethernet0 = &cpsw_port2;
+	};
+
+        cpus {
+                cpu@0 {
+                        cpu-supply = <&buck1_30_reg>;
+                };
+
+                cpu@1 {
+                        cpu-supply = <&buck1_30_reg>;
+                };
+
+                cpu@2 {
+                        cpu-supply = <&buck1_30_reg>;
+                };
+
+                cpu@3 {
+                        cpu-supply = <&buck1_30_reg>;
+                };
+        };
+
+	memory@80000000 {
+		device_type = "memory";
+
+		/* 4 GiB RAM */
+		reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
+		      <0x00000008 0x80000000 0x00000000 0x80000000>;
+	};
+
+	vcc_1v8_sys: regulator-4 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_1v8_sys";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vmain_pd>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	leds_gpio: leds {
+		compatible = "gpio-leds";
+	};
+};
+
+&fss {
+	uio_mram: uio@500000000 {
+		compatible = "uio_pdrv_genirq";
+		linux,uio-name = "UIO_OSPI_MRAM";
+
+		/*
+		 * FSS Memory Region: External Memory Space (Region 3)
+		 * OSPI EVERSPIN MRAM
+		 *
+		 */
+		reg = <0x05 0x00000000 0x01 0x00000000>;
+	};
+};
+
+&mcu_pmx0 {
+	mcu_spi0_pins: mcu-spi0-pins {
+		pinctrl-single,pins = <
+			AM64X_MCU_IOPAD(0x008, PIN_OUTPUT, 0)   /* (A7) MCU_SPI0_CLK SCLK */
+			AM64X_MCU_IOPAD(0x000, PIN_OUTPUT, 0)   /* (E8) MCU_SPI0_CS0 nCS0 */
+			AM64X_MCU_IOPAD(0x00c, PIN_INPUT, 0)    /* (D9) MCU_SPI0_D0  MISO */
+			AM64X_MCU_IOPAD(0x010, PIN_OUTPUT, 0)   /* (C9) MCU_SPI0_D1  MOSI */
+		>;
+	};
+};
+
+&main_pmx0 {
+	main_mdio1_pins_default: main-mdio1-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x160,  PIN_OUTPUT,       0) /* (AD24) MDIO0_MDC  not used, just for testing */
+			AM62X_IOPAD(0x15c,  PIN_INPUT_PULLUP, 0) /* (AB22) MDIO0_MDIO not used, just for testing */
+		>;
+	};
+
+	main_rgmii2_pins_default: main-rgmii2-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x184, PIN_INPUT,  0) /* (AE23) RGMII2_RD0 */
+			AM62X_IOPAD(0x188, PIN_INPUT,  0) /* (AB20) RGMII2_RD1 */
+			AM62X_IOPAD(0x18c, PIN_INPUT,  0) /* (AC21) RGMII2_RD2 */
+			AM62X_IOPAD(0x190, PIN_INPUT,  0) /* (AE22) RGMII2_RD3 */
+			AM62X_IOPAD(0x180, PIN_INPUT,  0) /* (AD23) RGMII2_RXC */
+			AM62X_IOPAD(0x17c, PIN_INPUT,  0) /* (AD22) RGMII2_RX_CTL */
+			AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */
+			AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */
+			AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */
+			AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */
+			AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */
+			AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */
+		>;
+	};
+
+	usb1_pins_default: usb1-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x0258, PIN_INPUT, 0) /* (F18) USB1_DRVVBUS */
+		>;
+	};
+
+	mram_irq_pins_default: mram-irq-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x0038, PIN_INPUT, 7) /* (E24) OSPI0_CSn3.GPIO0_14 (nINT-nVMEM) */
+		>;
+	};
+
+	ospi0_pins_default: ospi0-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */
+			AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */
+			AM62X_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */
+			AM62X_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */
+			AM62X_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */
+			AM62X_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */
+			AM62X_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */
+			AM62X_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */
+			AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */
+			AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */
+			AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */
+		>;
+	};
+};
+
+&watchdog_ext {
+	status = "okay";
+};
+
+&gpmc0 {
+	status = "disabled";
+};
+
+&mcu_spi0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcu_spi0_pins>;
+};
+
+&main_spi0 {
+	status = "okay";
+};
+
+&main_spi2 {
+	status = "okay";
+};
+
+&ospi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&ospi0_pins_default>;
+	status = "okay";
+
+        /* Everspin Tech. EM008LXO
+         * Order-No EM008LXOAB320IS1R
+         */
+	mram: mram@0 {
+                pinctrl-names = "default";
+		pinctrl-0 = <&mram_irq_pins_default>;
+
+		interrupt-parent = <&main_gpio0>;
+		interrupts = <14 IRQ_TYPE_EDGE_FALLING>;
+
+		compatible = "jedec,spi-nor";
+		reg = <0x0>;
+		spi-tx-bus-width = <8>;
+		spi-rx-bus-width = <8>;
+		spi-max-frequency = <25000000>;
+		cdns,tshsl-ns = <60>;
+		cdns,tsd2d-ns = <60>;
+		cdns,tchsh-ns = <60>;
+		cdns,tslch-ns = <60>;
+		cdns,read-delay = <4>;
+		cdns,phy-mode;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "ospi.mram.mem";
+				reg = <0x0 0x800000>;
+			};
+		};
+	};
+};
+
+&main_i2c0 {
+	status = "okay";
+
+	eeprom_hw_id_wosm: at24c02@50 {
+		status = "disabled";
+		compatible = "atmel,24c02";
+		reg = <0x50>;
+		pagesize = <16>;
+	};
+
+	tps65219: pmic@30 {
+		compatible = "ti,tps65219";
+		reg = <0x30>;
+		system-power-controller;
+
+		buck1-supply = <&vcc_5v0>;
+		buck2-supply = <&vcc_5v0>;
+		buck3-supply = <&vcc_5v0>;
+		ldo1-supply = <&vcc_3v3_sys>;
+		ldo2-supply = <&vcc_1v8_sys>;
+		ldo3-supply = <&vcc_3v3_sys>;
+		ldo4-supply = <&vcc_3v3_sys>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_irq_pins_default>;
+
+		interrupt-parent = <&main_gpio0>;
+		interrupts = <68 IRQ_TYPE_EDGE_FALLING>;
+
+                /* NOTICE:
+                 *
+                 * We could use "tps65219-gpio" here with GPO1 (EN-DCDC-1V8)
+                 * and GPO2 (CARRIER_PWR_EN for SD-Card and I2C1 devices) enabled,
+                 * but will skip it for now and trust the bootloader or TPS-NVM for the
+                 * correct settings correctly.
+                 *
+                 * For now we declare vcc_1v8_sys as being fixed.
+                 *
+                 */
+		regulators {
+			buck1_30_reg: buck1 {
+				regulator-name = "VDD_CORE";
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck2_30_reg: buck2 {
+				regulator-name = "VCC3V3";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck3_30_reg: buck3 {
+				regulator-name = "VDD_LPDDR4";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo1_30_sd_1v8_reg: ldo1 {
+				regulator-name = "VDDSHV_SD_1V8_IO_PMIC";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+			};
+
+			ldo2_30_reg: ldo2 {
+				regulator-name = "VDDAR_CORE";
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo3_30_reg: ldo3 {
+				regulator-name = "VDDA_1V8";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo4_30_reg: ldo4 {
+				regulator-name = "VDDA_2V5";
+				regulator-min-microvolt = <2500000>;
+				regulator-max-microvolt = <2500000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&main_i2c1 {
+	status = "okay";
+};
+
+&sdhci0 { /* eMMC */
+	status = "okay";
+};
+
+&sdhci1 { /* SD */
+	status = "okay";
+
+	vmmc-supply = <&vcc_3v3_sys>;
+	vqmmc-supply = <&ldo1_30_sd_1v8_reg>;
+};
+
+&cpsw3g {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_mdio1_pins_default
+		     &main_rgmii2_pins_default>;
+};
+
+&cpsw_port1 {
+	status = "disabled";
+};
+
+/*
+ * Use a fixed phy for emac2.
+ * that's rgmii2
+ */
+&cpsw_port2 {
+	status = "okay";
+	phy-mode = "rgmii-rxid";
+
+	fixed-link {
+		speed = <1000>;
+		full-duplex;
+	};
+};
+
+&cpsw3g_mdio {
+	status = "disabled";
+};
+
+&usbss1 {
+	status = "okay";
+	ti,vbus-divider;
+};
+
+&usb1 {
+	status = "okay";
+	dr_mode = "host";
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb1_pins_default>;
+};

arch/arm64/boot/dts/ti/k3-am623-pfc-750-8xxx-common.dtsi

@@ -0,0 +1,378 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Common dtsi for AM62x based WAGO devices
+ *
+ * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * Copyright (C) 2025 WAGO GmbH & Co. KG <http://global.wago.com>
+ */
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/net/ti-dp83867.h>
+#include "k3-am625.dtsi"
+
+/ {
+	aliases {
+		serial2 = &main_uart0;
+		serial1 = &main_uart2;
+		serial4 = &main_uart4;
+		mmc0 = &sdhci1;
+		mmc1 = &sdhci0;
+		ethernet0 = &cpsw_port1;
+		ethernet1 = &cpsw_port2;
+		usb0 = &usb0;
+		watchdog0 = &main_rti0;
+		watchdog1 = &watchdog_ext;
+		watchdog2 = &main_rti1;
+		eeprom_typelabel = &eeprom_type_label;
+	};
+
+	opp-table {
+		opp-200000000 {
+			opp-microvolt = <750000>;
+		};
+
+		opp-400000000 {
+			opp-microvolt = <750000>;
+		};
+
+		opp-600000000 {
+			opp-microvolt = <750000>;
+		};
+
+		opp-800000000 {
+			opp-microvolt = <750000>;
+		};
+
+		opp-1000000000 {
+			opp-microvolt = <750000>;
+		};
+
+		opp-1250000000 {
+			opp-microvolt = <750000>;
+		};
+
+		opp-1400000000 {
+			opp-hz = /bits/ 64 <1400000000>;
+			opp-microvolt = <850000>;
+			opp-supported-hw = <0x01 0x0004>;
+			clock-latency-ns = <6000000>;
+		};
+	};
+
+	chosen {
+		stdout-path = "serial2:115200n8";
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		ramoops@9ca00000 {
+			compatible = "ramoops";
+			reg = <0x00 0x9ca00000 0x00 0x00100000>;
+			record-size = <0x8000>;
+			console-size = <0x8000>;
+			ftrace-size = <0x00>;
+			pmsg-size = <0x8000>;
+		};
+
+		secure_tfa_ddr: tfa@9e780000 {
+			reg = <0x00 0x9e780000 0x00 0x80000>;
+			alignment = <0x1000>;
+			no-map;
+		};
+
+		secure_ddr: optee@9e800000 {
+			reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
+			alignment = <0x1000>;
+			no-map;
+		};
+
+		wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0x9db00000 0x00 0xc00000>;
+			no-map;
+		};
+
+		mcu_m4fss_dma_memory_region: m4f-dma-memory@9cb00000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0x9cb00000 0x00 0x100000>;
+			no-map;
+		};
+
+		mcu_m4fss_memory_region: m4f-memory@9cc00000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0x9cc00000 0x00 0xe00000>;
+			no-map;
+		};
+	};
+
+	vmain_pd: regulator-0 {
+		/* TPS6522005 Dual PMIC */
+		compatible = "regulator-fixed";
+		regulator-name = "vmain_pd";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vcc_5v0: regulator-1 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_5v0";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vmain_pd>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vcc_3v3_sys: regulator-2 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_3v3_sys";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vmain_pd>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	watchdog_ext: watchdog {
+		compatible = "linux,wdt-gpio";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wdg_ext_pins_default>;
+		hw_algo = "toggle";
+		hw_margin_ms = <1120>; /* STWD100xY: min. 1120, typ. 1600 */
+		en-gpios = <&main_gpio0 42 GPIO_ACTIVE_LOW>;
+		gpios = <&main_gpio1 30 GPIO_ACTIVE_LOW>;
+	};
+
+	wsysinit: wsysinit_init {
+		compatible = "wago,sysinit";
+
+		tty,rs232-485 = "ttyS0";
+	};
+};
+
+&main_pmx0 {
+	main_uart0_pins_default: main-uart0-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
+			AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
+		>;
+	};
+
+	main_uart2_pins_default: main-uart2-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x01d0, PIN_INPUT,  3) /* (A15) UART0_CTSn.UART2_RXD */
+			AM62X_IOPAD(0x01d4, PIN_OUTPUT, 3) /* (B15) UART0_RTSn.UART2_TXD */
+		>;
+	};
+
+	main_uart4_pins_default: main-uart4-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x0b0, PIN_INPUT, 3) /* (K22) UART4_RXD */
+			AM62X_IOPAD(0x0b4, PIN_OUTPUT, 3) /* (K24) UART4_TXD */
+			AM62X_IOPAD(0x09c, PIN_OUTPUT_PULLDOWN, 7) /* (V25) GPIO0_38 (RS-DE) */
+		>;
+	};
+
+	main_i2c0_pins_default: main-i2c0-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */
+			AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */
+		>;
+	};
+
+	main_i2c1_pins_default: main-i2c1-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */
+			AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */
+		>;
+	};
+
+	main_mmc0_pins_default: main-mmc0-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x220, PIN_INPUT,  0) /* (Y3) MMC0_CMD */
+			AM62X_IOPAD(0x218, PIN_OUTPUT, 0) /* (AB1) MMC0_CLK */
+			AM62X_IOPAD(0x214, PIN_INPUT,  0) /* (AA2) MMC0_DAT0 */
+			AM62X_IOPAD(0x210, PIN_INPUT,  0) /* (AA1) MMC0_DAT1 */
+			AM62X_IOPAD(0x20c, PIN_INPUT,  0) /* (AA3) MMC0_DAT2 */
+			AM62X_IOPAD(0x208, PIN_INPUT,  0) /* (Y4) MMC0_DAT3 */
+			AM62X_IOPAD(0x204, PIN_INPUT,  0) /* (AB2) MMC0_DAT4 */
+			AM62X_IOPAD(0x200, PIN_INPUT,  0) /* (AC1) MMC0_DAT5 */
+			AM62X_IOPAD(0x1fc, PIN_INPUT,  0) /* (AD2) MMC0_DAT6 */
+			AM62X_IOPAD(0x1f8, PIN_INPUT,  0) /* (AC2) MMC0_DAT7 */
+		>;
+	};
+
+	main_mmc1_pins_default: main-mmc1-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x23c, PIN_INPUT,        0) /* (A21) MMC1_CMD */
+			AM62X_IOPAD(0x234, PIN_OUTPUT,       0) /* (B22) MMC1_CLK */
+			AM62X_IOPAD(0x230, PIN_INPUT,        0) /* (A22) MMC1_DAT0 */
+			AM62X_IOPAD(0x22c, PIN_INPUT,        0) /* (B21) MMC1_DAT1 */
+			AM62X_IOPAD(0x228, PIN_INPUT,        0) /* (C21) MMC1_DAT2 */
+			AM62X_IOPAD(0x224, PIN_INPUT,        0) /* (D22) MMC1_DAT3 */
+			AM62X_IOPAD(0x240, PIN_INPUT_PULLUP, 0) /* (D17) MMC1_SDCD */
+			AM62X_IOPAD(0x244, PIN_INPUT_PULLUP, 0) /* (C17) MMC1_SDWP */
+		>;
+	};
+
+	main_spi0_pins_default: main-spi0-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (A14) SPI0_CLK */
+			AM62X_IOPAD(0x01c0, PIN_INPUT,  0) /* (B13) SPI0_D0  */
+			AM62X_IOPAD(0x01c4, PIN_OUTPUT, 0) /* (B14) SPI0_D1  */
+			AM62X_IOPAD(0x01b4, PIN_OUTPUT, 0) /* (A13) SPI0_CS0 */
+		>;
+
+	};
+
+	main_spi2_pins_default: main-spi2-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x01b0, PIN_OUTPUT, 1) /* (A20) MCASP0_ACLKR.SPI2_CLK */
+			AM62X_IOPAD(0x0194, PIN_INPUT,  1) /* (B19) MCASP0_AXR3.SPI2_D0 */
+			AM62X_IOPAD(0x0198, PIN_OUTPUT, 1) /* (A19) MCASP0_AXR2.SPI2_D1 */
+			AM62X_IOPAD(0x01ac, PIN_OUTPUT, 1) /* (E19) MCASP0_AFSR.SPI2_CS0 */
+		>;
+	};
+
+	wdg_ext_pins_default: wdg-ext-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x00ac, PIN_OUTPUT_PULLUP | INPUT_EN, 7) /* (L21) GPMC0_CSn1.GPIO0_42 */
+			AM62X_IOPAD(0x01f0, PIN_OUTPUT, 7) /* (A18) EXT_REFCLK1.GPIO1_30 */
+		>;
+	};
+
+	pmic_irq_pins_default: pmic-irq-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x0114, PIN_INPUT, 7) /* (B24) MMC2_DAT0.GPIO0_68 */
+		>;
+	};
+};
+
+&main_uart0 { /* DGB UART */
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_uart0_pins_default>;
+};
+
+&main_uart2 { /* KBUS Firmware download */
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_uart2_pins_default>;
+};
+
+&main_uart4 { /* RS485 */
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_uart4_pins_default>;
+};
+
+&main_i2c0 { /* type label */
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_i2c0_pins_default>;
+	clock-frequency = <400000>;
+
+	eeprom_type_label: at24c512@54 {
+		compatible = "atmel,24c512";
+		reg = <0x54>;
+		pagesize = <128>;
+	};
+};
+
+&main_spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_spi0_pins_default>;
+
+	dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>;
+	dma-names = "tx0", "rx0";
+
+	/*
+	 * When this option is set, the McSPI EOW Interrupt will be used
+	 * to signal when a DMA Transfer is done. This is needed for this
+	 * platform to prevent unpredictable delays resulting from TX/RX
+	 * completions within the UDMA driver.
+	 */
+	use-eow-interrupt;
+};
+
+&main_spi2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_spi2_pins_default>;
+};
+
+&main_i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_i2c1_pins_default>;
+	clock-frequency = <400000>;
+
+	rtc@52 {
+		compatible = "microcrystal,rv3028";
+		reg = <0x52>;
+		// The backup goldcap is supplied with a higher voltage (+5V)
+		// then the RTC (+3,3) itself. It requires a special setup
+		// to avoid hardware failure.
+		use-goldcap-with-higher-voltage;
+	};
+};
+
+&sdhci0 {
+	/* eMMC */
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_mmc0_pins_default>;
+	ti,driver-strength-ohm = <33>;
+	disable-wp;
+};
+
+&sdhci1 {
+        /* SD */
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_mmc1_pins_default>;
+	ti,driver-strength-ohm = <33>;
+	disable-wp;
+};
+
+&mailbox0_cluster0 {
+	mbox_m4_0: mbox-m4-0 {
+		ti,mbox-rx = <0 0 0>;
+		ti,mbox-tx = <1 0 0>;
+	};
+};
+
+/*
+ * AM6232 does not have main_rti2, main_rti3, and main_rti15
+ * https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1218039/am623-stuck-in-sd-card-after-boot-up
+ */
+&main_rti2 {    // watchdog@e020000
+    status = "disabled";
+};
+
+&main_rti3 {    // watchdog@e030000
+    status = "disabled";
+};
+
+&main_rti15 {   // watchdog@e0f0000
+    status = "disabled";
+};
+
+&usbss0 {
+	status = "okay";
+	ti,vbus-divider;
+};
+
+&usb0 {
+	status = "okay";
+	dr_mode = "peripheral";
+};
+
+&mcu_m4fss {
+	mboxes = <&mailbox0_cluster0 &mbox_m4_0>;
+	memory-region = <&mcu_m4fss_dma_memory_region>,
+			<&mcu_m4fss_memory_region>;
+	status = "okay";
+};

arch/arm64/boot/dts/ti/k3-am623-pfc-kbus.dtsi

@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+* Common dtsi for AM62x WAGO based devices
+*
+* Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
+* Copyright (C) 2025 WAGO GmbH & Co. KG - https://www.wago.com/
+*/
+
+&main_pmx0 {
+	kbus_pins_default: kbus-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x0100, PIN_INPUT_PULLUP,    7) /* (AC25) VOUT0_VSYNC.GPIO0_63 (kbus,nsync) */
+			AM62X_IOPAD(0x0128, PIN_OUTPUT_PULLDOWN, 7) /* (B23) MMC2_SDWP.GPIO0_72 (kbus,nrst) */
+			AM62X_IOPAD(0x0118, PIN_OUTPUT_PULLUP,   7) /* (D25) MMC2_CLK.GPIO0_69 (kbus,cmdsel) */
+			AM62X_IOPAD(0x0104, PIN_OUTPUT_PULLUP,   7) /* (AC24) VOUT0_PCLK.GPIO0_64 (kbus,nirq) */
+			AM62X_IOPAD(0x0120, PIN_INPUT_PULLUP,    7) /* (C24) MMC2_CMD.GPIO0_70 (kbus,nerr) */
+			AM62X_IOPAD(0x0124, PIN_INPUT_PULLUP,    7) /* (A23) MMC2_SDCD.GPIO0_71 (kbus,nrdy) */
+		>;
+	};
+};
+
+&main_spi0 {
+	spi-rt;
+	spi-rt-prio = <81>;
+
+	kbus@0 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&kbus_pins_default>;
+		compatible = "wago,spi-kbus";
+		reg = <0>;
+		spi-max-frequency = <25000000>;
+
+		kbus,reset-on-boot;
+		kbus,renesas;
+
+		/*
+		 * kbus,cmdsel-gpio is used to signal the need for an update
+		 * while the KBUS slave cpu is being reset. Its low level
+		 * forces an update.
+		 */
+		kbus,force-update-detection;
+
+		/*
+		 * announce used tty-device in /sys/class/wago/system.
+		 * is needed to link this device to /dev/ttyKbus
+		 */
+		/* TODO: check serial device name in user-space */
+		kbus,tty-device = "ttyS1"; /* corresponds to &uart2*/
+
+		/* some should be active low, keep all to high for compatibility reasons */
+		kbus,nrst-gpio   = <&main_gpio0 72 GPIO_ACTIVE_LOW>;
+		kbus,nsync-gpio  = <&main_gpio0 63 GPIO_ACTIVE_HIGH>;
+		kbus,cmdsel-gpio = <&main_gpio0 69 GPIO_ACTIVE_HIGH>;
+		kbus,nirq-gpio   = <&main_gpio0 64 GPIO_ACTIVE_HIGH>;
+		kbus,nerr-gpio   = <&main_gpio0 70 GPIO_ACTIVE_HIGH>;
+		kbus,nrdy-gpio   = <&main_gpio0 71 GPIO_ACTIVE_HIGH>;
+	};
+};

arch/arm64/boot/dts/ti/k3-am623-pfc-rs485.dtsi

@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Common dtsi for AM62x WAGO based devices
+ *
+ * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2025 WAGO GmbH & Co. KG - https://www.wago.com/
+ */
+
+&main_i2c1 {
+        /*
+         * PCA9538, 8-Bit I/O Expander
+         */
+	io_exp_8bit: io-exp-8bit@71 {
+		compatible = "nxp,pca9538";
+		reg = <0x71>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		gpio-line-names = "RS.TERM-EN", "RS.SLR",
+				  "+5V0-FB-ENA", "IO3",
+				  "BIAS.EN", "BIAS.HIR",
+				  "IO6", "IO7";
+
+                rs485-5v { /* +5V0-FB-ENA */
+                    gpio-hog;
+                    gpios = <2 GPIO_ACTIVE_HIGH>;
+                    output-high;
+                };
+        };
+};
+
+&main_uart4 { /* RS485 Interface */
+	rts-gpios = <&main_gpio0 38 GPIO_ACTIVE_HIGH>;
+	rs485-term-gpios = <&io_exp_8bit 0 GPIO_ACTIVE_HIGH>;
+	rs485-rts-active-high;
+	linux,rs485-enabled-at-boot-time;
+};

arch/arm64/boot/dts/ti/k3-am623-pfc-rtc.dtsi

@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Common Real-Time-Clock dtsi for AM62x WAGO based devices
+ *
+ * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2025 WAGO GmbH & Co. KG - https://www.wago.com/
+ */
+
+&main_i2c1 {
+	rtc@52 {
+		compatible = "microcrystal,rv3028";
+		reg = <0x52>;
+
+		/* 
+                 * The backup goldcap is supplied with a higher voltage (+5V)
+		 * then the RTC (+3,3) itself. It requires a special setup
+		 * to avoid hardware failure.
+                 */
+		use-goldcap-with-higher-voltage;
+	};
+};

arch/arm64/boot/dts/ti/k3-am623-pfc-tpm.dtsi

@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Common Trusted Platform Module dtsi for AM62x based WAGO devices
+ *
+ * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2025 WAGO GmbH & Co. KG - https://www.wago.com/
+ */
+
+&main_pmx0 {
+	tpm_pins_default: tpm-pins-default-pins {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x010c, PIN_INPUT, 7) /* (E23) MMC2_DAT2.GPIO0_66 */
+		>;
+	};
+};
+
+&main_spi2 {
+	SLB9670: SLB9670@0 {
+		compatible = "infineon,slb9670", "tis,tpm2-spi", "tcg,tpm_tis-spi";
+		reg = <0>;
+		#gpio-cells = <2>;
+		#interrupt-cells = <2>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&tpm_pins_default>;
+		
+		interrupt-parent = <&main_gpio0>;
+		interrupts = <66 IRQ_TYPE_EDGE_FALLING>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		spi-max-frequency = <43000000>;
+	};
+};

arch/arm64/boot/dts/ti/k3-am62x-pfc.dtsi

@@ -1,910 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Common dtsi for AM62x WAGO based devices
- *
- * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
- *
- * Copyright (C) 2024 WAGO GmbH & Co. KG <http://global.wago.com>
- *     Oleg Karfich <oleg.karfich@wago.com>
- *     Andrej Unrau <andrej.unrau@wago.com>
- */
-
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/net/ti-dp83867.h>
-#include "k3-am625.dtsi"
-
-/ {
-	aliases {
-		serial2 = &main_uart0;
-		serial1 = &main_uart2;
-		serial4 = &main_uart4;
-		mmc0 = &sdhci1;
-		mmc1 = &sdhci0;
-		ethernet0 = &cpsw_port1;
-		ethernet1 = &cpsw_port2;
-		usb0 = &usb0;
-		watchdog0 = &main_rti0;
-		watchdog1 = &watchdog_ext;
-		watchdog2 = &main_rti1;
-	};
-
-	opp-table {
-		opp-200000000 {
-			opp-microvolt = <750000>;
-		};
-
-		opp-400000000 {
-			opp-microvolt = <750000>;
-		};
-
-		opp-600000000 {
-			opp-microvolt = <750000>;
-		};
-
-		opp-800000000 {
-			opp-microvolt = <750000>;
-		};
-
-		opp-1000000000 {
-			opp-microvolt = <750000>;
-		};
-
-		opp-1250000000 {
-			opp-microvolt = <750000>;
-		};
-
-		opp-1400000000 {
-			opp-hz = /bits/ 64 <1400000000>;
-			opp-microvolt = <850000>;
-			opp-supported-hw = <0x01 0x0004>;
-			clock-latency-ns = <6000000>;
-		};
-	};
-
-	chosen {
-		stdout-path = "serial2:115200n8";
-	};
-
-	memory@80000000 {
-		device_type = "memory";
-		/* 2G RAM */
-		reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
-
-	};
-
-	reserved-memory {
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
-
-		ramoops@9ca00000 {
-			compatible = "ramoops";
-			reg = <0x00 0x9ca00000 0x00 0x00100000>;
-			record-size = <0x8000>;
-			console-size = <0x8000>;
-			ftrace-size = <0x00>;
-			pmsg-size = <0x8000>;
-		};
-
-		secure_tfa_ddr: tfa@9e780000 {
-			reg = <0x00 0x9e780000 0x00 0x80000>;
-			alignment = <0x1000>;
-			no-map;
-		};
-
-		secure_ddr: optee@9e800000 {
-			reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
-			alignment = <0x1000>;
-			no-map;
-		};
-
-		wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 {
-			compatible = "shared-dma-pool";
-			reg = <0x00 0x9db00000 0x00 0xc00000>;
-			no-map;
-		};
-	};
-
-	wsysinit: wsysinit_init {
-		compatible = "wago,sysinit";
-
-		tty,rs232-485 = "ttyS0";
-		board,variant = "pfc300";
-	};
-
-	/* this name of the gpio-keys device is a
-	 * historical heritage from 3.6.11 kernel.
-	 * the device-name is checked in omsd. So we
-	 * need to adapt this configuration
-	 */
-	oms: PAC-Operating-Mode-Switch {
-		compatible = "gpio-keys";
-		pinctrl-names = "default";
-		pinctrl-0 = <&oms_pins_default>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		autorepeat;
-
-		oms_run: run {
-			label = "RUN";
-			gpios = <&main_gpio0 65 GPIO_ACTIVE_LOW>;
-			linux,code = <1>;
-			linux,input-type = <5>;
-			debounce-interval = <1>;
-		};
-
-		oms_stop: stop {
-			label = "STOP";
-			gpios = <&main_gpio1 10 GPIO_ACTIVE_LOW>;
-			linux,code = <2>;
-			linux,input-type = <5>;
-			debounce-interval = <1>;
-		};
-
-		oms_reset: reset {
-			label = "RESET";
-			gpios = <&main_gpio1 12 GPIO_ACTIVE_LOW>;
-			linux,code = <3>;
-			linux,input-type = <1>;
-			debounce-interval = <1>;
-		};
-
-		oms_reset_all: reset_all {
-			label = "RESET_ALL";
-			gpios = <&main_gpio1 11 GPIO_ACTIVE_HIGH>;
-			linux,code = <4>;
-			linux,input-type = <1>;
-			debounce-interval = <1>;
-		};
-	};
-
-	uio_nvram: nvram@51000000 {
-		compatible = "uio_pdrv_genirq";
-		linux,uio-name = "UIO_NVRAM";
-		reg = <0 0x51000000 0 0x00020000>; /* 128k 16bit NVRAM */
-	};
-
-	vmain_pd: regulator-0 {
-		/* TPS6522005 Dual PMIC */
-		compatible = "regulator-fixed";
-		regulator-name = "vmain_pd";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		regulator-always-on;
-		regulator-boot-on;
-	};
-
-	vcc_5v0: regulator-1 {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc_5v0";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		vin-supply = <&vmain_pd>;
-		regulator-always-on;
-		regulator-boot-on;
-	};
-
-	vcc_3v3_sys: regulator-2 {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc_3v3_sys";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		vin-supply = <&vmain_pd>;
-		regulator-always-on;
-		regulator-boot-on;
-	};
-
-	vdd_mmc1: regulator-3 {
-		compatible = "regulator-fixed";
-	 	pinctrl-names = "default";
-	 	pinctrl-0 = <&vdd_sd_dv_pins_default>;
-		regulator-name = "vdd_mmc1";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		vin-supply = <&vcc_3v3_sys>;
-		gpio = <&main_gpio0 31 GPIO_ACTIVE_LOW>;
-		enable-active-high;
-		startup-delay-us = <5000>;
-	};
-
-	watchdog_ext: watchdog {
-		compatible = "linux,wdt-gpio";
-		pinctrl-names = "default";
-		pinctrl-0 = <&wdg_ext_pins_default>;
-		hw_algo = "toggle";
-		hw_margin_ms = <1120>; /* STWD100xY: min. 1120, typ. 1600 */
-		en-gpios = <&main_gpio0 42 GPIO_ACTIVE_LOW>;
-		gpios = <&main_gpio1 30 GPIO_ACTIVE_LOW>;
-	};
-};
-
-&main_pmx0 {
-	main_uart0_pins_default: main-uart0-default-pins {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
-			AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
-		>;
-	};
-
-	main_uart2_pins_default: main-uart2-default-pins {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x01d0, PIN_INPUT,  3) /* (A15) UART0_CTSn.UART2_RXD */
-			AM62X_IOPAD(0x01d4, PIN_OUTPUT, 3) /* (B15) UART0_RTSn.UART2_TXD */
-		>;
-	};
-
-	main_uart4_pins_default: main-uart4-default-pins {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x0b0, PIN_INPUT, 3) /* (K22) UART4_RXD */
-			AM62X_IOPAD(0x0b4, PIN_OUTPUT, 3) /* (K24) UART4_TXD */
-			AM62X_IOPAD(0x09c, PIN_OUTPUT_PULLDOWN, 7) /* (V25) GPIO0_38 (RS-DE) */
-		>;
-	};
-
-	main_i2c0_pins_default: main-i2c0-default-pins {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */
-			AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */
-		>;
-	};
-
-	main_i2c1_pins_default: main-i2c1-default-pins {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */
-			AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */
-		>;
-	};
-
-	main_mmc0_pins_default: main-mmc0-default-pins {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x220, PIN_INPUT,  0) /* (Y3) MMC0_CMD */
-			AM62X_IOPAD(0x218, PIN_OUTPUT, 0) /* (AB1) MMC0_CLK */
-			AM62X_IOPAD(0x214, PIN_INPUT,  0) /* (AA2) MMC0_DAT0 */
-			AM62X_IOPAD(0x210, PIN_INPUT,  0) /* (AA1) MMC0_DAT1 */
-			AM62X_IOPAD(0x20c, PIN_INPUT,  0) /* (AA3) MMC0_DAT2 */
-			AM62X_IOPAD(0x208, PIN_INPUT,  0) /* (Y4) MMC0_DAT3 */
-			AM62X_IOPAD(0x204, PIN_INPUT,  0) /* (AB2) MMC0_DAT4 */
-			AM62X_IOPAD(0x200, PIN_INPUT,  0) /* (AC1) MMC0_DAT5 */
-			AM62X_IOPAD(0x1fc, PIN_INPUT,  0) /* (AD2) MMC0_DAT6 */
-			AM62X_IOPAD(0x1f8, PIN_INPUT,  0) /* (AC2) MMC0_DAT7 */
-		>;
-	};
-
-	main_mmc1_pins_default: main-mmc1-default-pins {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x23c, PIN_INPUT,        0) /* (A21) MMC1_CMD */
-			AM62X_IOPAD(0x234, PIN_OUTPUT,       0) /* (B22) MMC1_CLK */
-			AM62X_IOPAD(0x230, PIN_INPUT,        0) /* (A22) MMC1_DAT0 */
-			AM62X_IOPAD(0x22c, PIN_INPUT,        0) /* (B21) MMC1_DAT1 */
-			AM62X_IOPAD(0x228, PIN_INPUT,        0) /* (C21) MMC1_DAT2 */
-			AM62X_IOPAD(0x224, PIN_INPUT,        0) /* (D22) MMC1_DAT3 */
-			AM62X_IOPAD(0x240, PIN_INPUT_PULLUP, 0) /* (D17) MMC1_SDCD */
-			AM62X_IOPAD(0x244, PIN_INPUT_PULLUP, 0) /* (C17) MMC1_SDWP */
-		>;
-	};
-
-	main_mdio1_pins_default: main-mdio1-default-pins {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x160,  PIN_OUTPUT,       0) /* (AD24) MDIO0_MDC */
-			AM62X_IOPAD(0x15c,  PIN_INPUT_PULLUP, 0) /* (AB22) MDIO0_MDIO */
-			AM62X_IOPAD(0x019c, PIN_OUTPUT,       7) /* (B18) MCASP0_AXR1.GPIO1_9 */
-		>;
-	};
-
-	main_rgmii1_pins_default: main-rgmii1-default-pins {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x14c, PIN_INPUT,  0) /* (AB17) RGMII1_RD0 */
-			AM62X_IOPAD(0x150, PIN_INPUT,  0) /* (AC17) RGMII1_RD1 */
-			AM62X_IOPAD(0x154, PIN_INPUT,  0) /* (AB16) RGMII1_RD2 */
-			AM62X_IOPAD(0x158, PIN_INPUT,  0) /* (AA15) RGMII1_RD3 */
-			AM62X_IOPAD(0x148, PIN_INPUT,  0) /* (AD17) RGMII1_RXC */
-			AM62X_IOPAD(0x144, PIN_INPUT,  0) /* (AE17) RGMII1_RX_CTL */
-			AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */
-			AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */
-			AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */
-			AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */
-			AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */
-			AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */
-			AM62X_IOPAD(0x0030, PIN_INPUT, 7) /* (G21) OSPI0_CSn1.GPIO0_12 */
-		>;
-	};
-
-	main_rgmii2_pins_default: main-rgmii2-default-pins {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x184, PIN_INPUT,  0) /* (AE23) RGMII2_RD0 */
-			AM62X_IOPAD(0x188, PIN_INPUT,  0) /* (AB20) RGMII2_RD1 */
-			AM62X_IOPAD(0x18c, PIN_INPUT,  0) /* (AC21) RGMII2_RD2 */
-			AM62X_IOPAD(0x190, PIN_INPUT,  0) /* (AE22) RGMII2_RD3 */
-			AM62X_IOPAD(0x180, PIN_INPUT,  0) /* (AD23) RGMII2_RXC */
-			AM62X_IOPAD(0x17c, PIN_INPUT,  0) /* (AD22) RGMII2_RX_CTL */
-			AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */
-			AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */
-			AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */
-			AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */
-			AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */
-			AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */
-			AM62X_IOPAD(0x0034, PIN_INPUT, 7) /* (H21) OSPI0_CSn2.GPIO0_13 */
-		>;
-	};
-
-	vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */
-		>;
-	};
-
-	gpmc_data_pins_default: gpmc-data-default-pins {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x00bc, PIN_OUTPUT, 1) /* (V24) VOUT0_DATA1.GPMC0_A1    */
-			AM62X_IOPAD(0x00c0, PIN_OUTPUT, 1) /* (W25) VOUT0_DATA2.GPMC0_A2    */
-			AM62X_IOPAD(0x00c4, PIN_OUTPUT, 1) /* (W24) VOUT0_DATA3.GPMC0_A3    */
-			AM62X_IOPAD(0x00c8, PIN_OUTPUT, 1) /* (Y25) VOUT0_DATA4.GPMC0_A4    */
-			AM62X_IOPAD(0x00cc, PIN_OUTPUT, 1) /* (Y24) VOUT0_DATA5.GPMC0_A5    */
-			AM62X_IOPAD(0x00d0, PIN_OUTPUT, 1) /* (Y23) VOUT0_DATA6.GPMC0_A6    */
-			AM62X_IOPAD(0x00d4, PIN_OUTPUT, 1) /* (AA25) VOUT0_DATA7.GPMC0_A7   */
-			AM62X_IOPAD(0x00d8, PIN_OUTPUT, 1) /* (V21) VOUT0_DATA8.GPMC0_A8    */
-			AM62X_IOPAD(0x00dc, PIN_OUTPUT, 1) /* (W21) VOUT0_DATA9.GPMC0_A9    */
-			AM62X_IOPAD(0x00e0, PIN_OUTPUT, 1) /* (V20) VOUT0_DATA10.GPMC0_A10  */
-			AM62X_IOPAD(0x00e4, PIN_OUTPUT, 1) /* (AA23) VOUT0_DATA11.GPMC0_A11 */
-			AM62X_IOPAD(0x00e8, PIN_OUTPUT, 1) /* (AB25) VOUT0_DATA12.GPMC0_A12 */
-			AM62X_IOPAD(0x00ec, PIN_OUTPUT, 1) /* (AA24) VOUT0_DATA13.GPMC0_A13 */
-			AM62X_IOPAD(0x00f0, PIN_OUTPUT, 1) /* (Y22) VOUT0_DATA14.GPMC0_A14  */
-			AM62X_IOPAD(0x00f4, PIN_OUTPUT, 1) /* (AA21) VOUT0_DATA15.GPMC0_A15 */
-			AM62X_IOPAD(0x00f8, PIN_OUTPUT, 1) /* (AB24) VOUT0_HSYNC.GPMC0_A16  */
-		>;
-	};
-
-	gpmc_addr_pins_default: gpmc-addr-default-pins {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x003c, PIN_INPUT, 0) /* (M25) GPMC0_AD0  */
-			AM62X_IOPAD(0x0040, PIN_INPUT, 0) /* (N23) GPMC0_AD1  */
-			AM62X_IOPAD(0x0044, PIN_INPUT, 0) /* (N24) GPMC0_AD2  */
-			AM62X_IOPAD(0x0048, PIN_INPUT, 0) /* (N25) GPMC0_AD3  */
-			AM62X_IOPAD(0x004c, PIN_INPUT, 0) /* (P24) GPMC0_AD4  */
-			AM62X_IOPAD(0x0050, PIN_INPUT, 0) /* (P22) GPMC0_AD5  */
-			AM62X_IOPAD(0x0054, PIN_INPUT, 0) /* (P21) GPMC0_AD6  */
-			AM62X_IOPAD(0x0058, PIN_INPUT, 0) /* (R23) GPMC0_AD7  */
-			AM62X_IOPAD(0x005c, PIN_INPUT, 0) /* (R24) GPMC0_AD8  */
-			AM62X_IOPAD(0x0060, PIN_INPUT, 0) /* (R25) GPMC0_AD9  */
-			AM62X_IOPAD(0x0064, PIN_INPUT, 0) /* (T25) GPMC0_AD10 */
-			AM62X_IOPAD(0x0068, PIN_INPUT, 0) /* (R21) GPMC0_AD11 */
-			AM62X_IOPAD(0x006c, PIN_INPUT, 0) /* (T22) GPMC0_AD12 */
-			AM62X_IOPAD(0x0070, PIN_INPUT, 0) /* (T24) GPMC0_AD13 */
-			AM62X_IOPAD(0x0074, PIN_INPUT, 0) /* (U25) GPMC0_AD14 */
-			AM62X_IOPAD(0x0078, PIN_INPUT, 0) /* (U24) GPMC0_AD15 */
-		>;
-	};
-
-	gpmc_ctrl_pins_default: gpmc-ctrl-default-pins {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x0094, PIN_OUTPUT, 0) /* (N20) GPMC0_BE1n     */
-			AM62X_IOPAD(0x00a8, PIN_OUTPUT, 0) /* (M21) GPMC0_CSn0     */
-			AM62X_IOPAD(0x0088, PIN_OUTPUT, 0) /* (L24) GPMC0_OEn_REn  */
-			AM62X_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L25) GPMC0_WEn      */
-			AM62X_IOPAD(0x0090, PIN_OUTPUT, 0) /* (M24) GPMC0_BE0n_CLE */
-		>;
-	};
-
-	oms_pins_default: oms-default-pins {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x0108, PIN_INPUT, 7) /* (D24) MMC2_DAT3.GPIO0_65 */
-			AM62X_IOPAD(0x01a0, PIN_INPUT, 7) /* (E18) MCASP0_AXR0.GPIO1_10 */
-			AM62X_IOPAD(0x01a8, PIN_INPUT, 7) /* (D20) MCASP0_AFSX.GPIO1_12 */
-			AM62X_IOPAD(0x01a4, PIN_INPUT, 7) /* (B20) MCASP0_ACLKX.GPIO1_11 */
-		>;
-	};
-
-	main_spi0_pins_default: main-spi0-default-pins {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (A14) SPI0_CLK */
-			AM62X_IOPAD(0x01c0, PIN_INPUT,  0) /* (B13) SPI0_D0  */
-			AM62X_IOPAD(0x01c4, PIN_OUTPUT, 0) /* (B14) SPI0_D1  */
-			AM62X_IOPAD(0x01b4, PIN_OUTPUT, 0) /* (A13) SPI0_CS0 */
-		>;
-
-	};
-
-	main_spi2_pins_default: main-spi2-default-pins {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x01b0, PIN_OUTPUT, 1) /* (A20) MCASP0_ACLKR.SPI2_CLK */
-			AM62X_IOPAD(0x0194, PIN_INPUT,  1) /* (B19) MCASP0_AXR3.SPI2_D0 */
-			AM62X_IOPAD(0x0198, PIN_INPUT,  1) /* (A19) MCASP0_AXR2.SPI2_D1 */
-			AM62X_IOPAD(0x01ac, PIN_OUTPUT, 1) /* (E19) MCASP0_AFSR.SPI2_CS0 */
-		>;
-	};
-
-	tpm_pins_default: tpm-pins-default-pins {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x010c, PIN_INPUT, 7) /* (E23) MMC2_DAT2.GPIO0_66 */
-		>;
-	};
-
-	kbus_pins_default: kbus-default-pins {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x0100, PIN_INPUT_PULLUP,    7) /* (AC25) VOUT0_VSYNC.GPIO0_63 (kbus,nsync) */
-			AM62X_IOPAD(0x0128, PIN_OUTPUT_PULLDOWN, 7) /* (B23) MMC2_SDWP.GPIO0_72 (kbus,nrst) */
-			AM62X_IOPAD(0x0118, PIN_OUTPUT_PULLUP,   7) /* (D25) MMC2_CLK.GPIO0_69 (kbus,cmdsel) */
-			AM62X_IOPAD(0x0104, PIN_OUTPUT_PULLUP,   7) /* (AC24) VOUT0_PCLK.GPIO0_64 (kbus,nirq) */
-			AM62X_IOPAD(0x0120, PIN_INPUT_PULLUP,    7) /* (C24) MMC2_CMD.GPIO0_70 (kbus,nerr) */
-			AM62X_IOPAD(0x0124, PIN_INPUT_PULLUP,    7) /* (A23) MMC2_SDCD.GPIO0_71 (kbus,nrdy) */
-		>;
-	};
-
-	wdg_ext_pins_default: wdg-ext-default-pins {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x00ac, PIN_OUTPUT_PULLUP | INPUT_EN, 7) /* (L21) GPMC0_CSn1.GPIO0_42 */
-			AM62X_IOPAD(0x01f0, PIN_OUTPUT, 7) /* (A18) EXT_REFCLK1.GPIO1_30 */
-		>;
-	};
-
-	pmic_irq_pins_default: pmic-irq-default-pins {
-		pinctrl-single,pins = <
-			AM62X_IOPAD(0x0114, PIN_INPUT, 7) /* (B24) MMC2_DAT0.GPIO0_68 */
-		>;
-	};
-};
-
-&gpmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&gpmc_data_pins_default>, <&gpmc_addr_pins_default>, <&gpmc_ctrl_pins_default>;
-
-	num-cs = <4>;
-	num-waitpins = <4>;
-	ranges = <
-		0 0 0x00 0x51000000 0x01000000	/* CS0: NVRAM, 16M */
-	>;
-
-	nvram: nor@0,0 { /* NVRAM Device 128k */
-		reg = <0 0 0x01000000>;
-		bank-width = <2>; /* 1: 8bit, 2: 16bit */
-		gpmc,sync-clk-ps = <0>;
-		gpmc,cs-on-ns = <0>;
-		gpmc,cs-rd-off-ns = <50>;
-		gpmc,cs-wr-off-ns = <30>;
-		gpmc,adv-on-ns = <0>;
-		gpmc,adv-rd-off-ns = <0>;
-		gpmc,adv-wr-off-ns = <0>;
-		gpmc,oe-on-ns = <0>;
-		gpmc,oe-off-ns = <50>;
-		gpmc,we-on-ns = <0>;
-		gpmc,we-off-ns = <30>;
-		gpmc,rd-cycle-ns = <50>;
-		gpmc,wr-cycle-ns = <30>;
-		gpmc,access-ns = <40>;
-		gpmc,wr-access-ns = <10>;
-		gpmc,wr-data-mux-bus-ns = <0>;
-		gpmc,cycle2cycle-delay-ns = <10>;
-		gpmc,cycle2cycle-samecsen;
-		gpmc,cycle2cycle-diffcsen;
-
-		#address-cells = <1>;
-		#size-cells = <1>;
-	};
-};
-
-&main_uart0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_uart0_pins_default>;
-};
-
-&main_uart2 { /* KBUS Firmware download */
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_uart2_pins_default>;
-};
-
-&main_uart4 { /* RS485 Interface */
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_uart4_pins_default>;
-
-	rts-gpios = <&main_gpio0 38 GPIO_ACTIVE_HIGH>;
-	rs485-term-gpios = <&rs485 0 GPIO_ACTIVE_HIGH>;
-	rs485-rts-active-high;
-	linux,rs485-enabled-at-boot-time;
-};
-
-&main_i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_i2c0_pins_default>;
-	clock-frequency = <400000>;
-
-	eeprom: at24c512@54 {
-		compatible = "atmel,24c512";
-		reg = <0x54>;
-		pagesize = <128>;
-	};
-
-	led_bar60: pca9552@60 {
-		compatible = "nxp,pca9552";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0x60>;
-
-		lb60_0: sys-red@0 {
-			label = "sys-red";
-			reg = <0>;
-			linux,default-trigger = "timer";
-		};
-
-		lb60_1: sys-green@1 {
-			label = "sys-green";
-			reg = <1>;
-			linux,default-trigger = "timer";
-		};
-
-		lb60_2: run-red@2 {
-			label = "run-red";
-			reg = <2>;
-		};
-
-		lb60_3: run-green@3 {
-			label = "run-green";
-			reg = <3>;
-		};
-
-		lb60_4: io-red@4 {
-			label = "io-red";
-			reg = <4>;
-		};
-
-		lb60_5: io-green@5 {
-			label = "io-green";
-			reg = <5>;
-		};
-
-		lb60_6: ms-red@6 {
-			label = "ms-red";
-			reg = <6>;
-		};
-
-		lb60_7: ms-green@7 {
-			label = "ms-green";
-			reg = <7>;
-		};
-
-		lb60_8: ns-red@8 {
-			label = "ns-red";
-			reg = <8>;
-		};
-
-		lb60_9: ns-green@9 {
-			label = "ns-green";
-			reg = <9>;
-		};
-
-		lb60_10: usr_r@10 {
-			label = "trm-red";
-			reg = <10>;
-		};
-
-		lb60_11: usr_g@11 {
-			label = "trm-green";
-			reg = <11>;
-		};
-
-		lb60_15: sys-over-red@15 {
-			label = "sys-over-red";
-			reg = <15>;
-			linux,default-trigger = "default-on";
-		};
-	};
-
-	led_bar61: pca9552@61 {
-		compatible = "nxp,pca9552";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0x61>;
-
-		lb61_0: u6-red@0 {
-			label = "u6-red";
-			reg = <0>;
-		};
-
-		lb61_1: u6-green@1 {
-			label = "u6-green";
-			reg = <1>;
-		};
-
-		lb61_2: u5-red@2 {
-			label = "u5-red";
-			reg = <2>;
-		};
-
-		lb61_3: u5-green@3 {
-			label = "u5-green";
-			reg = <3>;
-		};
-
-		lb61_4: u4-red@4 {
-			label = "u4-red";
-			reg = <4>;
-		};
-
-		lb61_5: u4-green@5 {
-			label = "u4-green";
-			reg = <5>;
-		};
-
-		lb61_6: u3-red@6 {
-			label = "u3-red";
-			reg = <6>;
-		};
-
-		lb61_7: u3-green@7 {
-			label = "u3-green";
-			reg = <7>;
-		};
-
-		lb61_8: u2-red@8 {
-			label = "u2-red";
-			reg = <8>;
-		};
-
-		lb61_9: u2-green@9 {
-			label = "u2-green";
-			reg = <9>;
-		};
-
-		lb61_10: u1-red@10 {
-			label = "u1-red";
-			reg = <10>;
-		};
-
-		lb61_11: u1-green@11 {
-			label = "u1-green";
-			reg = <11>;
-		};
-	};
-
-	tps65219_30: pmic@30 {
-		compatible = "ti,tps65219";
-		reg = <0x30>;
-		system-power-controller;
-
-		buck1-supply = <&vcc_5v0>;
-		buck2-supply = <&vcc_5v0>;
-		buck3-supply = <&vcc_5v0>;
-		ldo1-supply = <&vcc_3v3_sys>;
-		ldo2-supply = <&vcc_3v3_sys>;
-		ldo3-supply = <&vcc_5v0>;
-		ldo4-supply = <&vcc_5v0>;
-
-		pinctrl-names = "default";
-		pinctrl-0 = <&pmic_irq_pins_default>;
-
-		interrupt-parent = <&main_gpio0>;
-		interrupts = <68 IRQ_TYPE_EDGE_FALLING>;
-
-		regulators {
-			buck1_30_reg: buck1 {
-				regulator-name = "VDD_CORE";
-				regulator-min-microvolt = <750000>;
-				regulator-max-microvolt = <850000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			buck2_30_reg: buck2 {
-				regulator-name = "VCC1V8_SYS";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			buck3_30_reg: buck3 {
-				regulator-name = "VCC3V3_SYS";
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			ldo1_30_reg: ldo1 {
-				regulator-name = "VCC3V3_SDC";
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-			};
-
-			ldo2_30_reg: ldo2 {
-				regulator-name = "VDDA_1V8";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-		};
-	};
-};
-
-&main_spi0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_spi0_pins_default>;
-
-	spi-rt;
-	spi-rt-prio = <81>;
-	dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>;
-	dma-names = "tx0", "rx0";
-
-	/*
-	 * When this option is set, the McSPI EOW Interrupt will be used
-	 * to signal when a DMA Transfer is done. This is needed for this
-	 * platform to prevent unpredictable delays resulting from TX/RX
-	 * completions within the UDMA driver.
-	 */
-	use-eow-interrupt;
-
-	kbus@0 {
-		pinctrl-names = "default";
-		pinctrl-0 = <&kbus_pins_default>;
-		compatible = "wago,spi-kbus";
-		reg = <0>;
-		spi-max-frequency = <10000000>;
-
-		kbus,reset-on-boot;
-
-		/*
-		 * kbus,cmdsel-gpio is used to signal the need for an update
-		 * while the KBUS slave cpu is being reset. Its low level
-		 * forces an update.
-		 */
-		kbus,force-update-detection;
-
-		/*
-		 * announce used tty-device in /sys/class/wago/system.
-		 * is needed to link this device to /dev/ttyKbus
-		 */
-		/* TODO: check serial device name in user-space */
-		kbus,tty-device = "ttyS1"; /* corresponds to &uart2*/
-
-		/* some should be active low, keep all to high for compatibility reasons */
-		kbus,nrst-gpio   = <&main_gpio0 72 GPIO_ACTIVE_LOW>;
-		kbus,nsync-gpio  = <&main_gpio0 63 GPIO_ACTIVE_HIGH>;
-		kbus,cmdsel-gpio = <&main_gpio0 69 GPIO_ACTIVE_HIGH>;
-		kbus,nirq-gpio   = <&main_gpio0 64 GPIO_ACTIVE_HIGH>;
-		kbus,nerr-gpio   = <&main_gpio0 70 GPIO_ACTIVE_HIGH>;
-		kbus,nrdy-gpio   = <&main_gpio0 71 GPIO_ACTIVE_HIGH>;
-	};
-
-};
-
-&main_spi2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_spi2_pins_default>;
-	
-	SLB9670: SLB9670@0 {
-		compatible = "infineon,slb9670", "tis,tpm2-spi", "tcg,tpm_tis-spi";
-		reg = <0>;
-		#gpio-cells = <2>;
-		#interrupt-cells = <2>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&tpm_pins_default>;
-		
-		interrupt-parent = <&main_gpio0>;
-		interrupts = <66 IRQ_TYPE_EDGE_FALLING>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		spi-max-frequency = <43000000>;
-	};
-};
-
-&main_i2c1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_i2c1_pins_default>;
-	clock-frequency = <400000>;
-
-	rtc@52 {
-		compatible = "microcrystal,rv3028";
-		reg = <0x52>;
-		// The backup goldcap is supplied with a higher voltage (+5V)
-		// then the RTC (+3,3) itself. It requires a special setup
-		// to avoid hardware failure.
-		use-goldcap-with-higher-voltage;
-	};
-
-	rs485: rs485@71 {
-		compatible = "nxp,pca9538";
-		reg = <0x71>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		gpio-line-names = "RS.TERM-EN", "RS.SLR",
-				  "+5V0-FB-ENA", "MP200",
-				  "BIAS.EN", "BIAS.HIR",
-				  "MP201", "MP202";
-
-		rs485-5v {
-			gpio-hog;
-			gpios = <2 GPIO_ACTIVE_HIGH>;
-			output-high;
-		};
-	};
-};
-
-&sdhci0 {
-	/* eMMC */
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_mmc0_pins_default>;
-	ti,driver-strength-ohm = <33>;
-	disable-wp;
-};
-
-&sdhci1 {
-	/* SD */
-	vmmc-supply = <&vdd_mmc1>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_mmc1_pins_default>;
-	ti,driver-strength-ohm = <33>;
-	cap-sd-highspeed;
-	no-1-8-v;
-};
-
-&cpsw3g {
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_mdio1_pins_default
-		     &main_rgmii1_pins_default
-		     &main_rgmii2_pins_default>;
-};
-
-&cpsw_port1 {
-	phy-mode = "rgmii-rxid";
-	phy-handle = <&cpsw3g_phy0>;
-};
-
-&cpsw_port2 {
-	phy-mode = "rgmii-rxid";
-	phy-handle = <&cpsw3g_phy1>;
-};
-
-&cpsw3g_mdio {
-        reset-gpios = <&main_gpio1 9 GPIO_ACTIVE_LOW>;
-        reset-delay-us = <10>;
-        reset-post-delay-us = <10000>;
-
-	cpsw3g_phy0: ethernet-phy@0 {
-		// ADIN1300
-		compatible = "ethernet-phy-id0283.bc30";
-
-		reg = <0>;
-		adi,rx-internal-delay-ps = <2000>;
-	};
-
-	cpsw3g_phy1: ethernet-phy@1 {
-		// ADIN1300
-		compatible = "ethernet-phy-id0283.bc30";
-
-		reg = <1>;
-		adi,rx-internal-delay-ps = <2000>;
-	};
-};
-
-&mailbox0_cluster0 {
-	mbox_m4_0: mbox-m4-0 {
-		ti,mbox-rx = <0 0 0>;
-		ti,mbox-tx = <1 0 0>;
-	};
-};
-
-/*
- * AM6232 does not have main_rti2, main_rti3, and main_rti15
- * https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1218039/am623-stuck-in-sd-card-after-boot-up
- */
-&main_rti2 {    // watchdog@e020000
-    status = "disabled";
-};
-
-&main_rti3 {    // watchdog@e030000
-    status = "disabled";
-};
-
-&main_rti15 {   // watchdog@e0f0000
-    status = "disabled";
-};
-
-&usbss0 {
-	ti,vbus-divider;
-};
-
-&usb0 {
-	dr_mode = "peripheral";
-};

arch/arm64/configs/am6xxx_defconfig

@@ -131,6 +131,7 @@ CONFIG_BRIDGE_EBT_T_FILTER=m
 CONFIG_BRIDGE_EBT_T_NAT=m
 CONFIG_BRIDGE=y
 CONFIG_BRIDGE_VLAN_FILTERING=y
+CONFIG_NET_DSA=y
 CONFIG_VLAN_8021Q=m
 CONFIG_VLAN_8021Q_GVRP=y
 CONFIG_NET_SCHED=y
@@ -149,9 +150,10 @@ CONFIG_NET_ACT_POLICE=m
 CONFIG_NET_ACT_GACT=m
 CONFIG_NET_ACT_MIRRED=m
 CONFIG_NET_ACT_GATE=m
-CONFIG_NET_SWITCHDEV=y
 CONFIG_CGROUP_NET_PRIO=y
 # CONFIG_WIRELESS is not set
+CONFIG_NFC=y
+CONFIG_NFC_TAG_ST25DV=y
 CONFIG_PAGE_POOL_STATS=y
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
@@ -161,10 +163,12 @@ CONFIG_VEXPRESS_CONFIG=y
 CONFIG_MHI_BUS=m
 CONFIG_ARM_SCMI_PROTOCOL=y
 CONFIG_ARM_SCPI_PROTOCOL=y
-CONFIG_MTD=m
+CONFIG_MTD=y
+CONFIG_MTD_OF_PARTS=m
 CONFIG_MTD_PHYSMAP=m
 CONFIG_MTD_PHYSMAP_OF=y
 CONFIG_MTD_PLATRAM=m
+CONFIG_MTD_SPI_NOR=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_NBD=m
 CONFIG_SRAM=y
@@ -172,6 +176,7 @@ CONFIG_SRAM=y
 CONFIG_EEPROM_AT24=y
 CONFIG_SCSI=y
 # CONFIG_SCSI_PROC_FS is not set
+CONFIG_BLK_DEV_SD=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_SCSI_SAS_LIBSAS=y
 # CONFIG_SCSI_LOWLEVEL is not set
@@ -182,6 +187,8 @@ CONFIG_IPVLAN=m
 CONFIG_VXLAN=m
 CONFIG_TUN=y
 CONFIG_VETH=m
+CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=y
+CONFIG_NET_DSA_MICROCHIP_KSZ_SPI=y
 # CONFIG_NET_VENDOR_ALACRITECH is not set
 # CONFIG_NET_VENDOR_AMAZON is not set
 # CONFIG_NET_VENDOR_AMD is not set
@@ -252,6 +259,7 @@ CONFIG_SERIAL_8250_DW=y
 CONFIG_SERIAL_8250_OMAP=y
 CONFIG_SERIAL_OF_PLATFORM=y
 # CONFIG_SERIAL_OMAP_MODBUS is not set
+CONFIG_RPMSG_TTY=y
 CONFIG_HW_RANDOM=y
 CONFIG_TCG_TPM=y
 CONFIG_TCG_TIS=y
@@ -263,7 +271,6 @@ CONFIG_I2C_MUX_PCA954x=y
 CONFIG_I2C_DESIGNWARE_PLATFORM=y
 CONFIG_I2C_OMAP=y
 CONFIG_SPI=y
-# CONFIG_SPI_MEM is not set
 CONFIG_SPI_CADENCE_QUADSPI=y
 CONFIG_SPI_DESIGNWARE=y
 CONFIG_SPI_OMAP24XX=y
@@ -297,14 +304,20 @@ CONFIG_REGULATOR_TPS65219=y
 CONFIG_USB=y
 CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
 # CONFIG_USB_DEFAULT_PERSIST is not set
+CONFIG_USB_OTG=y
+CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_MUSB_HDRC=y
 CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GADGET=y
 # CONFIG_USB_DWC3_KEYSTONE is not set
 CONFIG_NOP_USB_XCEIV=y
 CONFIG_USB_ULPI=y
 CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=32
 CONFIG_USB_CONFIGFS=m
 CONFIG_USB_CONFIGFS_SERIAL=y
 CONFIG_USB_CONFIGFS_ACM=y
@@ -317,6 +330,7 @@ CONFIG_USB_CONFIGFS_EEM=y
 CONFIG_USB_CONFIGFS_MASS_STORAGE=y
 CONFIG_USB_CONFIGFS_F_FS=y
 CONFIG_USB_FUNCTIONFS=m
+CONFIG_USB_MASS_STORAGE=y
 CONFIG_MMC=y
 CONFIG_MMC_BLOCK_MINORS=32
 CONFIG_MMC_ARMMMCI=y
@@ -326,6 +340,7 @@ CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_SDHCI_AM654=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
 CONFIG_LEDS_PCA955X=y
 CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_TIMER=y
@@ -356,6 +371,14 @@ CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y
 CONFIG_IOMMU_IO_PGTABLE_DART=y
 CONFIG_ARM_SMMU=y
 CONFIG_ARM_SMMU_V3=y
+CONFIG_REMOTEPROC=y
+CONFIG_REMOTEPROC_CDEV=y
+CONFIG_TI_K3_DSP_REMOTEPROC=y
+CONFIG_TI_K3_M4_REMOTEPROC=y
+CONFIG_TI_K3_R5_REMOTEPROC=y
+CONFIG_RPMSG_CHAR=y
+CONFIG_RPMSG_CTRL=y
+CONFIG_RPMSG_VIRTIO=y
 CONFIG_SOC_BRCMSTB=y
 CONFIG_TI_SCI_PM_DOMAINS=y
 CONFIG_PM_DEVFREQ=y
@@ -387,7 +410,6 @@ CONFIG_NTFS3_FS=m
 CONFIG_TMPFS=y
 CONFIG_TMPFS_POSIX_ACL=y
 CONFIG_HUGETLBFS=y
-CONFIG_CONFIGFS_FS=y
 CONFIG_SQUASHFS=y
 CONFIG_PSTORE=y
 CONFIG_PSTORE_CONSOLE=y
@@ -436,8 +458,6 @@ CONFIG_SYSTEM_TRUSTED_KEYRING=y
 CONFIG_PACKING=y
 CONFIG_INDIRECT_PIO=y
 CONFIG_CRC_CCITT=m
-CONFIG_CRC_T10DIF=y
-CONFIG_CRC64_ROCKSOFT=y
 CONFIG_CRC_ITU_T=y
 CONFIG_CRC7=y
 CONFIG_CRC8=y

drivers/extcon/extcon-ptn5150.c

@@ -18,6 +18,7 @@
 #include <linux/extcon-provider.h>
 #include <linux/gpio/consumer.h>
 #include <linux/usb/role.h>
+#include <linux/regulator/consumer.h>
 
 /* PTN5150 registers */
 #define PTN5150_REG_DEVICE_ID			0x01
@@ -54,6 +55,7 @@ struct ptn5150_info {
 	struct work_struct irq_work;
 	struct mutex mutex;
 	struct usb_role_switch *role_sw;
+	struct regulator *vbus_reg;
 };
 
 /* List of detectable cables */
@@ -69,10 +71,43 @@ static const struct regmap_config ptn5150_regmap_config = {
 	.max_register	= PTN5150_REG_END,
 };
 
+static void ptn5150_vbus_off(struct ptn5150_info *info)
+{
+	int ret = 0;
+
+	gpiod_set_value_cansleep(info->vbus_gpiod, 0);
+	if (info->vbus_reg) {
+		dev_info(info->dev, "Disable VBUS regulator\n");
+
+		if (regulator_is_enabled(info->vbus_reg))
+			ret = regulator_disable(info->vbus_reg);
+
+		if (ret)
+			dev_err(info->dev, "VBUS regulator disable failed\n");
+	}
+}
+
+static void ptn5150_vbus_on(struct ptn5150_info *info)
+{
+	int ret = 0;
+
+	gpiod_set_value_cansleep(info->vbus_gpiod, 1);
+	if (info->vbus_reg) {
+		dev_info(info->dev, "Enable VBUS regulator\n");
+
+		if (!regulator_is_enabled(info->vbus_reg))
+			ret = regulator_enable(info->vbus_reg);
+
+		if (ret)
+			dev_err(info->dev, "VBUS regulator enable failed\n");
+	}
+}
+
 static void ptn5150_check_state(struct ptn5150_info *info)
 {
 	unsigned int port_status, reg_data, vbus;
 	enum usb_role usb_role = USB_ROLE_NONE;
+	bool vbus_reg_enable = false;
 	int ret;
 
 	ret = regmap_read(info->regmap, PTN5150_REG_CC_STATUS, &reg_data);
@@ -86,17 +121,14 @@ static void ptn5150_check_state(struct ptn5150_info *info)
 	switch (port_status) {
 	case PTN5150_DFP_ATTACHED:
 		extcon_set_state_sync(info->edev, EXTCON_USB_HOST, false);
-		gpiod_set_value_cansleep(info->vbus_gpiod, 0);
 		extcon_set_state_sync(info->edev, EXTCON_USB, true);
 		usb_role = USB_ROLE_DEVICE;
 		break;
 	case PTN5150_UFP_ATTACHED:
 		extcon_set_state_sync(info->edev, EXTCON_USB, false);
 		vbus = FIELD_GET(PTN5150_REG_CC_VBUS_DETECTION, reg_data);
-		if (vbus)
-			gpiod_set_value_cansleep(info->vbus_gpiod, 0);
-		else
-			gpiod_set_value_cansleep(info->vbus_gpiod, 1);
+		if (!vbus)
+			vbus_reg_enable = true;
 
 		extcon_set_state_sync(info->edev, EXTCON_USB_HOST, true);
 		usb_role = USB_ROLE_HOST;
@@ -105,6 +137,11 @@ static void ptn5150_check_state(struct ptn5150_info *info)
 		break;
 	}
 
+	if (vbus_reg_enable)
+		ptn5150_vbus_on(info);
+	else
+		ptn5150_vbus_off(info);
+
 	if (usb_role) {
 		ret = usb_role_switch_set_role(info->role_sw, usb_role);
 		if (ret)
@@ -144,7 +181,7 @@ static void ptn5150_irq_work(struct work_struct *work)
 					EXTCON_USB_HOST, false);
 			extcon_set_state_sync(info->edev,
 					EXTCON_USB, false);
-			gpiod_set_value_cansleep(info->vbus_gpiod, 0);
+			ptn5150_vbus_off(info);
 
 			ret = usb_role_switch_set_role(info->role_sw,
 						       USB_ROLE_NONE);
@@ -249,6 +286,19 @@ static int ptn5150_i2c_probe(struct i2c_client *i2c)
 		}
 	}
 
+	info->vbus_reg = NULL;
+	if (of_find_property(np, "vbus-supply", NULL)) {
+		struct regulator *vbus_reg;
+
+		vbus_reg = devm_regulator_get_exclusive(dev, "vbus");
+		if (IS_ERR_OR_NULL(vbus_reg)) {
+			return dev_err_probe(dev, PTR_ERR(vbus_reg),
+				"Couldn't get the VBUS power regulator.\n");
+		}
+
+		info->vbus_reg = vbus_reg;
+	}
+
 	mutex_init(&info->mutex);
 
 	INIT_WORK(&info->irq_work, ptn5150_irq_work);

drivers/mtd/spi-nor/core.c

@@ -2003,6 +2003,7 @@ static const struct spi_nor_manufacturer *manufacturers[] = {
 	&spi_nor_eon,
 	&spi_nor_esmt,
 	&spi_nor_everspin,
+	&spi_mram_everspin,
 	&spi_nor_fujitsu,
 	&spi_nor_gigadevice,
 	&spi_nor_intel,

drivers/mtd/spi-nor/core.h

@@ -635,6 +635,7 @@ extern const struct spi_nor_manufacturer spi_nor_catalyst;
 extern const struct spi_nor_manufacturer spi_nor_eon;
 extern const struct spi_nor_manufacturer spi_nor_esmt;
 extern const struct spi_nor_manufacturer spi_nor_everspin;
+extern const struct spi_nor_manufacturer spi_mram_everspin;
 extern const struct spi_nor_manufacturer spi_nor_fujitsu;
 extern const struct spi_nor_manufacturer spi_nor_gigadevice;
 extern const struct spi_nor_manufacturer spi_nor_intel;

drivers/mtd/spi-nor/everspin.c

@@ -8,6 +8,248 @@
 
 #include "core.h"
 
+/* flash_info mfr_flag. Used to read proprietary FSR register. */
+#define USE_FSR		BIT(0)
+
+#define SPINOR_OP_RDFSR		0x70	/* Read flag status register */
+#define SPINOR_OP_CLFSR		0x50	/* Clear flag status register */
+#define SPINOR_OP_MT_DTR_RD	0xfd	/* Fast Read opcode in DTR mode */
+#define SPINOR_OP_MT_RD_ANY_REG	0x85	/* Read volatile register */
+#define SPINOR_OP_MT_WR_ANY_REG	0x81	/* Write volatile register */
+#define SPINOR_REG_MT_CFR0V	0x00	/* For setting octal DTR mode */
+#define SPINOR_REG_MT_CFR1V	0x01	/* For setting dummy cycles */
+#define SPINOR_REG_MT_CFR1V_DEF	0x1f	/* Default dummy cycles */
+#define SPINOR_MT_OCT_DTR	0xe7	/* Enable Octal DTR. */
+#define SPINOR_MT_EXSPI		0xff	/* Enable Extended SPI (default) */
+
+/* Flag Status Register bits */
+#define FSR_READY		BIT(7)	/* Device status, 0 = Busy, 1 = Ready */
+#define FSR_E_ERR		BIT(5)	/* Erase operation status */
+#define FSR_P_ERR		BIT(4)	/* Program operation status */
+#define FSR_CRC_ERR		BIT(3)	/* CRC Error status */
+#define FSR_PT_ERR		BIT(1)	/* Protection error bit */
+#define FSR_4B_ADDR		BIT(0)	/* 3 or 4 Byte Addressing Mode */
+
+
+/* Everspin SPI NOR flash operations. */
+#define EVERSPIN_NOR_WR_ANY_REG_OP(naddr, addr, ndata, buf)		\
+	SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 0),		\
+		   SPI_MEM_OP_ADDR(naddr, addr, 0),			\
+		   SPI_MEM_OP_NO_DUMMY,					\
+		   SPI_MEM_OP_DATA_OUT(ndata, buf, 0))
+
+#define EVERSPIN_RDFSR_OP(buf)						\
+	SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDFSR, 0),			\
+		   SPI_MEM_OP_NO_ADDR,					\
+		   SPI_MEM_OP_NO_DUMMY,					\
+		   SPI_MEM_OP_DATA_IN(1, buf, 0))
+
+#define EVERSPIN_CLFSR_OP						\
+	SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLFSR, 0),			\
+		   SPI_MEM_OP_NO_ADDR,					\
+		   SPI_MEM_OP_NO_DUMMY,					\
+		   SPI_MEM_OP_NO_DATA)
+
+
+static int everspin_nor_octal_dtr_en(struct spi_nor *nor)
+{
+	struct spi_mem_op op;
+	u8 *buf = nor->bouncebuf;
+	int ret;
+
+	/* Use 8 dummy cycles for memory array reads. */
+	*buf = 8;
+	op = (struct spi_mem_op)
+		EVERSPIN_NOR_WR_ANY_REG_OP(4, SPINOR_REG_MT_CFR1V, 1, buf);
+	ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);
+	if (ret)
+		return ret;
+
+	buf[0] = SPINOR_MT_OCT_DTR;
+	op = (struct spi_mem_op)
+		EVERSPIN_NOR_WR_ANY_REG_OP(4, SPINOR_REG_MT_CFR0V, 1, buf);
+	ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);
+	if (ret)
+		return ret;
+
+	/* Read flash ID to make sure the switch was successful. */
+	ret = spi_nor_read_id(nor, 0, 8, buf, SNOR_PROTO_8_8_8_DTR);
+	if (ret) {
+		dev_dbg(nor->dev, "error %d reading JEDEC ID after enabling 8D-8D-8D mode\n", ret);
+		return ret;
+	}
+
+	if (memcmp(buf, nor->info->id, nor->info->id_len))
+		return -EINVAL;
+
+	return 0;
+}
+
+static int everspin_nor_octal_dtr_dis(struct spi_nor *nor)
+{
+	struct spi_mem_op op;
+	u8 *buf = nor->bouncebuf;
+	int ret;
+
+	/*
+	 * The register is 1-byte wide, but 1-byte transactions are not allowed
+	 * in 8D-8D-8D mode. The next register is the dummy cycle configuration
+	 * register. Since the transaction needs to be at least 2 bytes wide,
+	 * set the next register to its default value. This also makes sense
+	 * because the value was changed when enabling 8D-8D-8D mode, it should
+	 * be reset when disabling.
+	 */
+	buf[0] = SPINOR_MT_EXSPI;
+	buf[1] = SPINOR_REG_MT_CFR1V_DEF;
+	op = (struct spi_mem_op)
+		EVERSPIN_NOR_WR_ANY_REG_OP(4, SPINOR_REG_MT_CFR0V, 2, buf);
+	ret = spi_nor_write_any_volatile_reg(nor, &op, SNOR_PROTO_8_8_8_DTR);
+	if (ret)
+		return ret;
+
+	/* Read flash ID to make sure the switch was successful. */
+	ret = spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1);
+	if (ret) {
+		dev_dbg(nor->dev, "error %d reading JEDEC ID after disabling 8D-8D-8D mode\n", ret);
+		return ret;
+	}
+
+	if (memcmp(buf, nor->info->id, nor->info->id_len))
+		return -EINVAL;
+
+	return 0;
+}
+
+static int everspin_nor_octal_dtr(struct spi_nor *nor, bool enable)
+{
+	return enable ? everspin_nor_octal_dtr_en(nor) :
+			everspin_nor_octal_dtr_dis(nor);
+}
+
+
+/**
+ * everspin_nor_read_fsr() - Read the Flag Status Register.
+ * @nor:	pointer to 'struct spi_nor'
+ * @fsr:	pointer to a DMA-able buffer where the value of the
+ *              Flag Status Register will be written. Should be at least 2
+ *              bytes.
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int everspin_nor_read_fsr(struct spi_nor *nor, u8 *fsr)
+{
+	int ret;
+
+	if (nor->spimem) {
+		struct spi_mem_op op = EVERSPIN_RDFSR_OP(fsr);
+
+		if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) {
+			op.addr.nbytes = nor->params->rdsr_addr_nbytes;
+			op.dummy.nbytes = nor->params->rdsr_dummy;
+			/*
+			 * We don't want to read only one byte in DTR mode. So,
+			 * read 2 and then discard the second byte.
+			 */
+			op.data.nbytes = 2;
+		}
+
+		spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
+
+		ret = spi_mem_exec_op(nor->spimem, &op);
+	} else {
+		ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDFSR, fsr,
+						      1);
+	}
+
+	if (ret)
+		dev_dbg(nor->dev, "error %d reading FSR\n", ret);
+
+	return ret;
+}
+
+/**
+ * everspin_nor_clear_fsr() - Clear the Flag Status Register.
+ * @nor:	pointer to 'struct spi_nor'.
+ */
+static void everspin_nor_clear_fsr(struct spi_nor *nor)
+{
+	int ret;
+
+	if (nor->spimem) {
+		struct spi_mem_op op = EVERSPIN_CLFSR_OP;
+
+		spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
+
+		ret = spi_mem_exec_op(nor->spimem, &op);
+	} else {
+		ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_CLFSR,
+						       NULL, 0);
+	}
+
+	if (ret)
+		dev_dbg(nor->dev, "error %d clearing FSR\n", ret);
+}
+
+/**
+ * everspin_nor_ready() - Query the Status Register as well as the Flag Status
+ * Register to see if the flash is ready for new commands. If there are any
+ * errors in the FSR clear them.
+ * @nor:	pointer to 'struct spi_nor'.
+ *
+ * Return: 1 if ready, 0 if not ready, -errno on errors.
+ */
+static int everspin_nor_ready(struct spi_nor *nor)
+{
+	int sr_ready, ret;
+
+	sr_ready = spi_nor_sr_ready(nor);
+	if (sr_ready < 0)
+		return sr_ready;
+
+	ret = everspin_nor_read_fsr(nor, nor->bouncebuf);
+	if (ret) {
+		/*
+		 * Some controllers, such as Intel SPI, do not support low
+		 * level operations such as reading the flag status
+		 * register. They only expose small amount of high level
+		 * operations to the software. If this is the case we use
+		 * only the status register value.
+		 */
+		return ret == -EOPNOTSUPP ? sr_ready : ret;
+	}
+
+	if (nor->bouncebuf[0] & (FSR_E_ERR | FSR_P_ERR)) {
+		if (nor->bouncebuf[0] & FSR_E_ERR)
+			dev_err(nor->dev, "Erase operation failed.\n");
+		else
+			dev_err(nor->dev, "Program operation failed.\n");
+
+		if (nor->bouncebuf[0] & FSR_PT_ERR)
+			dev_err(nor->dev,
+				"Attempted to modify a protected sector.\n");
+
+		if (nor->bouncebuf[0] & FSR_CRC_ERR)
+			dev_err(nor->dev,
+				"Computed CRC did not match the user provided CRC code.\n");
+
+		everspin_nor_clear_fsr(nor);
+
+		/*
+		 * WEL bit remains set to one when an erase or page program
+		 * error occurs. Issue a Write Disable command to protect
+		 * against inadvertent writes that can possibly corrupt the
+		 * contents of the memory.
+		 */
+		ret = spi_nor_write_disable(nor);
+		if (ret)
+			return ret;
+
+		return -EIO;
+	}
+
+	return sr_ready && !!(nor->bouncebuf[0] & FSR_READY);
+}
+
 static const struct flash_info everspin_nor_parts[] = {
 	/* Everspin */
 	{ "mr25h128", CAT25_INFO(16 * 1024, 1, 256, 2) },
@@ -16,8 +258,90 @@ static const struct flash_info everspin_nor_parts[] = {
 	{ "mr25h40",  CAT25_INFO(512 * 1024, 1, 256, 3) },
 };
 
+static const struct flash_info everspin_mram_parts[] = {
+	/* Everspin */
+	{ "em256lx",  INFO(0x6bbb19, 0, 32 * 1024 * 1024, 1)
+			FLAGS(SPI_NOR_NO_ERASE)
+	},
+	{ "em128lx",  INFO(0x6bbb18, 0, 16 * 1024 * 1024, 1)
+			FLAGS(SPI_NOR_NO_ERASE)
+	},
+	{ "em064lx",  INFO(0x6bbb17, 0, 8 * 1024 * 1024, 1)
+			FLAGS(SPI_NOR_NO_ERASE)
+	},
+	{ "em032lx",  INFO(0x6bbb16, 0, 4 * 1024 * 1024, 1)
+			FLAGS(SPI_NOR_NO_ERASE)
+	},
+	{ "em016lx",  INFO(0x6bbb15, 0, 2 * 1024 * 1024, 1)
+			FLAGS(SPI_NOR_NO_ERASE)
+	},
+	{ "em008lx",  INFO(0x6bbb14, 0, 1 * 1024 * 1024, 1)
+			FLAGS(SPI_NOR_NO_ERASE)
+	},
+};
+
+static void everspin_mram_default_init(struct spi_nor *nor)
+{
+	struct spi_mem_op op;
+	u8 *buf = nor->bouncebuf;
+
+	/* Use 8 dummy cycles for memory array reads. */
+	*buf = 8;
+	op = (struct spi_mem_op)
+		EVERSPIN_NOR_WR_ANY_REG_OP(3, SPINOR_REG_MT_CFR1V, 1, buf);
+	spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);
+
+	nor->cmd_ext_type = SPI_NOR_EXT_REPEAT;
+	nor->params->rdsr_dummy = 8;
+	nor->params->rdsr_addr_nbytes = 0;
+	// nor->params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode;
+	nor->params->addr_nbytes = 4;
+	nor->params->set_octal_dtr = everspin_nor_octal_dtr;
+
+	if (nor->info->mfr_flags & USE_FSR)
+		nor->params->ready = everspin_nor_ready;
+
+	/* Status Register has only 8 Bits */
+	nor->flags &= ~SNOR_F_HAS_16BIT_SR;
+
+	/*
+	 * The BFPT quad enable field is set to a reserved value so the quad
+	 * enable function is ignored by spi_nor_parse_bfpt(). Make sure we
+	 * disable it.
+	 */
+	nor->params->quad_enable = NULL;
+}
+
+static int everspin_mram_late_init(struct spi_nor *nor)
+{
+	/* Set Read and Write settings. */
+	nor->params->hwcaps.mask |= SNOR_HWCAPS_READ_1_8_8;
+	spi_nor_set_read_settings(&nor->params->reads[SNOR_CMD_READ_1_8_8],
+				  0, 8, SPINOR_OP_READ_1_8_8,
+				  SNOR_PROTO_1_8_8);
+
+	nor->params->hwcaps.mask |= SNOR_HWCAPS_PP_1_8_8;
+	spi_nor_set_pp_settings(&nor->params->page_programs[SNOR_CMD_PP_1_8_8],
+				SPINOR_OP_PP_1_8_8,
+				SNOR_PROTO_1_8_8);
+
+	return 0;
+}
+
+static const struct spi_nor_fixups everspin_mram_fixups = {
+	.default_init = everspin_mram_default_init,
+	.late_init = everspin_mram_late_init,
+};
+
 const struct spi_nor_manufacturer spi_nor_everspin = {
 	.name = "everspin",
 	.parts = everspin_nor_parts,
 	.nparts = ARRAY_SIZE(everspin_nor_parts),
 };
+
+const struct spi_nor_manufacturer spi_mram_everspin = {
+	.name = "everspin_mram",
+	.parts = everspin_mram_parts,
+	.nparts = ARRAY_SIZE(everspin_mram_parts),
+	.fixups = &everspin_mram_fixups,
+};

drivers/net/phy/phy_device.c

@@ -2343,12 +2343,13 @@ EXPORT_SYMBOL(genphy_aneg_done);
  */
 int genphy_update_link(struct phy_device *phydev)
 {
-	int status = 0, bmcr;
+	int status = 0, bmcr, i;
 
 	bmcr = phy_read(phydev, MII_BMCR);
 	if (bmcr < 0)
 		return bmcr;
 
+
 	/* Autoneg is being started, therefore disregard BMSR value and
 	 * report link as down.
 	 */
@@ -2369,9 +2370,19 @@ int genphy_update_link(struct phy_device *phydev)
 	}
 
 	/* Read link and autonegotiation status */
-	status = phy_read(phydev, MII_BMSR);
-	if (status < 0)
-		return status;
+	for (i = 0; i < 20; i++) {
+		status = phy_read(phydev, MII_BMSR);
+		if (status < 0)
+			return status;
+
+		if (status & BMSR_LSTATUS)
+			break;
+
+		cpu_relax();
+	}
+	if (status & BMSR_LSTATUS)
+		if (i >= 1)
+			phydev_info(phydev, "link up after multiple reads: %di\n", i);
 done:
 	phydev->link = status & BMSR_LSTATUS ? 1 : 0;
 	phydev->autoneg_complete = status & BMSR_ANEGCOMPLETE ? 1 : 0;

drivers/nfc/Kconfig

@@ -70,4 +70,5 @@ source "drivers/nfc/st-nci/Kconfig"
 source "drivers/nfc/nxp-nci/Kconfig"
 source "drivers/nfc/s3fwrn5/Kconfig"
 source "drivers/nfc/st95hf/Kconfig"
+source "drivers/nfc/tag/Kconfig"
 endmenu

drivers/nfc/Makefile

@@ -18,3 +18,4 @@ obj-$(CONFIG_NFC_NXP_NCI)	+= nxp-nci/
 obj-$(CONFIG_NFC_S3FWRN5)	+= s3fwrn5/
 obj-$(CONFIG_NFC_ST95HF)	+= st95hf/
 obj-$(CONFIG_NFC_VIRTUAL_NCI)	+= virtual_ncidev.o
+obj-y				+= tag/

drivers/nfc/tag/Kconfig

@@ -0,0 +1,5 @@
+menu "NFC Tag devices"
+	depends on NFC
+
+source "drivers/nfc/tag/st25dv/Kconfig"
+endmenu

drivers/nfc/tag/Makefile

@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Makefile for nfc tag devices
+#
+
+obj-$(CONFIG_NFC_TAG_ST25DV)		+= st25dv/

drivers/nfc/tag/st25dv/Kconfig

@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-only
+config NFC_TAG_ST25DV
+	tristate "STMicroelectronics ST25DVxxK nfc tag driver"
+	depends on I2C
+	help
+	  This is the STMicroelectronics NFC Tag driver for the ST25DVxxK devices.

drivers/nfc/tag/st25dv/Makefile

@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Makefile for ST25DV NFC driver
+#
+
+# st25dv-y += st25dv.o
+obj-$(CONFIG_NFC_TAG_ST25DV)     += st25dv.o

drivers/nfc/tag/st25dv/st25dv.c

@@ -0,0 +1,543 @@
+
+/*
+ * Copyright (C) 2018 Loïc Boban <loic.boban@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/device.h>
+#include <linux/i2c.h>
+#include <linux/uaccess.h>
+#include <linux/delay.h>
+#include <linux/mutex.h>
+
+#define DYN_REG_SIZE		0x8
+#define SYS_MEM_SIZE		0x24
+#define USER_MEM_SIZE		0x200
+#define MAILBOX_MEM_SIZE        0x100
+#define SYS_ADDR		0x57
+#define USER_ADDR		0x53
+#define PWD_OFF			0x0900
+#define DYN_REG_OFF		0x2000
+#define MAILBOX_OFF		0x2008
+#define MAX_TRY			10
+
+#define PWD_REQ_SIZE		0x13
+#define PWD_SIZE		0x08
+#define CMD_PRESENT_PWD		0x09
+#define CMD_WRITE_PWD		0x07
+#define PWD_CMD_POS		10
+#define PWD1_POS		2
+#define PWD2_POS		11
+
+#define MEM_04K                 512
+#define MEM_16K                 2000
+#define MEM_64K                 8000
+
+static const struct bin_attribute st25dv_p_pwd_attr;
+
+enum area_type{
+	USER_AREA = 0,
+	SYS_AREA = 1,
+	DYN_REG_AREA = 2,
+	MAILBOX_AREA = 3,
+};
+
+/*the st25dv eeprom have two areas, the user area, and the system
+area to manage read/write protection for the NFC interface and I2C
+interface. To drive the system area a dummy i2c_client is used*/
+static int mem_config[4] = {MEM_04K, MEM_04K, MEM_16K, MEM_64K};
+static int area_off[4] = {0, 0, DYN_REG_OFF, MAILBOX_OFF};
+
+/*one struct is used for each area*/
+struct st25dv_data {
+	u8 *data;//area data
+	enum area_type type;
+	struct bin_attribute bin_attr;
+	struct i2c_client *client;
+        struct mutex *update_lock;//protect for concurrent updates
+	struct st25dv_data *next;
+};
+
+/* Addresses to scan */
+static const unsigned short normal_i2c[] = { USER_ADDR, SYS_ADDR, I2C_CLIENT_END };
+
+static ssize_t st25dv_read(struct file *filp, struct kobject *kobj,
+			   struct bin_attribute *bin_attr, char *buf, loff_t off, size_t count)
+{
+	int r_size, nack;
+	struct i2c_client *client = to_i2c_client(kobj_to_dev(kobj));
+	struct st25dv_data *data = i2c_get_clientdata(client);
+	u16 cur_off;
+
+	while(&data->bin_attr != bin_attr){
+		data = data->next;
+	}
+	off += area_off[data->type];
+	mutex_lock(data->update_lock);
+	for(cur_off = off; cur_off-off < count; cur_off++){
+		nack = 0;
+retry_:
+		if(nack > MAX_TRY){
+			mutex_unlock(data->update_lock);
+			return r_size;
+		}
+		r_size = i2c_smbus_write_byte_data(client, (cur_off >> 8) & 0x0ff, cur_off & 0x0ff);
+		if(r_size < 0){
+			nack++;
+			udelay(150);
+			goto retry_;
+		}
+		r_size = i2c_smbus_read_byte(client);
+		if(r_size < 0){
+			nack++;
+			udelay(150);
+			goto retry_;
+		}
+		data->data[cur_off] = r_size;
+	}
+	memcpy(buf, &data->data[off], count);
+	mutex_unlock(data->update_lock);
+	//pr_warn("st25dv: %d byte reads.\n",count);
+
+	return count;
+}
+
+#if 0 /* function is not used yet */
+static ssize_t st25dv_write_area(struct file *filp, struct kobject *kobj,
+			struct bin_attribute *bin_attr, char *buf, loff_t off, size_t count)
+{
+	int r_size;
+	struct i2c_client *client = to_i2c_client(kobj_to_dev(kobj));
+	struct st25dv_data *data = i2c_get_clientdata(client);
+	u16 cur_off, tmp;
+	u8 nack;
+
+	while(&data->bin_attr != bin_attr){
+		data = data->next;
+	}
+	off += area_off[data->type];
+	mutex_lock(data->update_lock);
+	memcpy(data->data + off, buf, count);
+	for(cur_off = off; cur_off-off < count; cur_off++){
+		nack = 0;
+		tmp = data->data[cur_off];
+		tmp = (tmp << 8) & 0xff00;
+		tmp |= cur_off & 0x00ff;
+retry_:
+		if(nack > MAX_TRY){
+			mutex_unlock(data->update_lock);
+			return r_size;
+		}
+		r_size = i2c_smbus_write_word_data(client, (cur_off >> 8) & 0x0ff, tmp );
+		if(r_size < 0){
+			nack++;
+			mdelay(1);
+			goto retry_;
+		}
+
+	}
+	mutex_unlock(data->update_lock);
+	//pr_warn("st25dv: %d byte writes.\n",count);
+
+	return count;
+}
+#endif
+
+//I2C_SMBUS_BLOCK_MAX = 9 page writes
+//MAX tw = 9 * 5ms
+//write_block is faster than write single byte but not supported by some adapter
+static ssize_t st25dv_write_block(struct file *filp, struct kobject *kobj,
+				  struct bin_attribute *bin_attr, char *buf, loff_t off, size_t count)
+{
+	int r_size, to_write, not_write;
+	struct i2c_client *client = to_i2c_client(kobj_to_dev(kobj));
+	struct st25dv_data *data = i2c_get_clientdata(client);
+	u16 cur_off, cur_buf_off;
+	u8 nack, tmp[I2C_SMBUS_BLOCK_MAX];
+
+	while(&data->bin_attr != bin_attr){
+		data = data->next;
+	}
+	off += area_off[data->type];
+	mutex_lock(data->update_lock);
+	memcpy(data->data + off, buf, count);
+	not_write = count;
+	cur_off = off;
+	cur_buf_off = 0;
+	while(not_write){
+		nack = 0;
+		to_write = not_write > I2C_SMBUS_BLOCK_MAX-2 ? I2C_SMBUS_BLOCK_MAX-2 : not_write;
+		not_write -= to_write;
+		tmp[1] = cur_off;
+		tmp[0] = cur_off >> 8;
+		memcpy(tmp + 2, buf + cur_buf_off, to_write);
+retry_:
+		if(nack > MAX_TRY){
+			mutex_unlock(data->update_lock);
+			return r_size;
+		}
+		r_size = i2c_master_send(client, tmp, to_write+2);
+		if(r_size < 0){
+			nack++;
+			mdelay(5);
+			goto retry_;
+		}
+		mdelay(20);
+		cur_off += to_write;
+		cur_buf_off += to_write;
+	}
+
+	mutex_unlock(data->update_lock);
+	//pr_warn("st25dv: %d byte writes.\n",count);
+
+	return count;
+}
+
+static ssize_t st25dv_send_pwd_req(struct file *filp, struct kobject *kobj,
+			   struct bin_attribute *bin_attr,
+				   char *buf, loff_t off, size_t count)
+{
+	u8 pwd_req[PWD_REQ_SIZE], cmd, *pwd_ptr1, *pwd_ptr2;
+	int r_size, off_tmp, nack;
+	struct i2c_client *client = to_i2c_client(kobj_to_dev(kobj));
+	struct st25dv_data *data = i2c_get_clientdata(client);
+
+	cmd = bin_attr == &st25dv_p_pwd_attr ? CMD_PRESENT_PWD : CMD_WRITE_PWD;
+	if(count != PWD_SIZE){
+		pr_warn("st25dv: send pwd cmd fail count=%d.\n", (int) count);
+		return count;
+	}
+	nack = 0;
+	pwd_req[0] = 0x09;
+	pwd_req[1] = 0x00;
+	pwd_ptr1 = &pwd_req[PWD1_POS];
+	pwd_ptr2 = &pwd_req[PWD2_POS];
+	pwd_req[PWD_CMD_POS] = cmd;
+	for(off_tmp = PWD_SIZE-1; off_tmp >= 0; off_tmp--){
+		*pwd_ptr1 = buf[off_tmp];
+		*pwd_ptr2 = buf[off_tmp];
+		pwd_ptr1++;
+		pwd_ptr2++;
+	}
+	mutex_lock(data->update_lock);
+retry_:
+	if(nack > MAX_TRY){
+		mutex_unlock(data->update_lock);
+		return r_size;
+	}
+	r_size = i2c_master_send(client, pwd_req, PWD_REQ_SIZE);
+	if(r_size < 0){
+		nack++;
+		mdelay(5);
+		goto retry_;
+	}
+	mutex_unlock(data->update_lock);
+	//pr_warn("st25dv: send pwd cmd send.\n");
+
+	return count;
+}
+
+static struct bin_attribute st25dv_user_attr = {
+	.attr = {
+		.name = "st25dv_user",
+		.mode = S_IRUGO|S_IWUGO,
+	},
+	.size = USER_MEM_SIZE,
+	.read = st25dv_read,
+	.write = st25dv_write_block,
+};
+
+static const struct bin_attribute st25dv_sys_attr = {
+	.attr = {
+		.name = "st25dv_sys",
+		.mode = S_IRUGO|S_IWUSR,
+	},
+	.size = SYS_MEM_SIZE,
+	.read = st25dv_read,
+        .write = st25dv_write_block,
+};
+
+static const struct bin_attribute st25dv_dyn_reg_attr = {
+        .attr = {
+                .name = "st25dv_dyn_reg",
+                .mode = S_IRUGO|S_IWUSR,
+  },
+        .size = DYN_REG_SIZE,
+        .read = st25dv_read,
+        .write = st25dv_write_block,
+};
+
+static const struct bin_attribute st25dv_mailbox_attr = {
+        .attr = {
+                .name = "st25dv_mailbox",
+                .mode = S_IRUGO|S_IWUGO,
+  },
+        .size = MAILBOX_MEM_SIZE,
+        .read = st25dv_read,
+        .write = st25dv_write_block,
+};
+
+static const struct bin_attribute st25dv_w_pwd_attr = {
+	.attr = {
+		.name = "st25dv_write_pwd",
+		.mode = S_IWUSR,
+	},
+	.size = PWD_SIZE,
+	.write = st25dv_send_pwd_req,
+};
+
+static const struct bin_attribute st25dv_p_pwd_attr = {
+	.attr = {
+		.name = "st25dv_present_pwd",
+		.mode = S_IWUSR,
+	},
+	.size = PWD_SIZE,
+	.write = st25dv_send_pwd_req,
+};
+
+/* Return 0 if detection is successful, -ENODEV otherwise */
+static int st25dv_detect(struct i2c_client *client, struct i2c_board_info *info)
+{
+	struct i2c_adapter *adapter = client->adapter;
+
+	if (!(adapter->class & I2C_CLASS_SPD) && (client->addr != USER_ADDR)){
+		pr_warn("not st25dv eeprom.\n");
+		return -ENODEV;
+	}
+	if(!i2c_new_dummy_device(client->adapter, SYS_ADDR)){
+		pr_warn("not st25dv eeprom.\n");
+		return -ENODEV;
+	}
+	if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_READ_WORD_DATA)
+	 && !i2c_check_functionality(adapter, I2C_FUNC_SMBUS_READ_I2C_BLOCK)){
+		pr_warn("st25dv eeprom detect but no functionality.\n");
+		return -ENODEV;
+	}
+	pr_info("st25dv eeprom detect.\n");
+	strlcpy(info->type, "st25dv", I2C_NAME_SIZE);
+
+	return 0;
+}
+
+static int st25dv_probe(struct i2c_client *client)
+{
+	const struct i2c_device_id *id = i2c_client_get_device_id(client);
+	int status;
+	struct mutex *st25dv_lock;
+	struct st25dv_data *data;
+	struct st25dv_data *sys_data;
+	struct st25dv_data *dyn_reg_data;
+	struct st25dv_data *mailbox_data;
+	struct i2c_client *client_sys_area;//i2c_client of the system area
+
+	/*dummy client for the system area at addr 0x57*/
+	client_sys_area = i2c_new_dummy_device(client->adapter, SYS_ADDR);
+	if(!client_sys_area){
+		pr_warn("st25dv sys eeprom not detected.\n");
+		return -ENODEV;
+	}
+	data = devm_kzalloc(&client->dev, sizeof(struct st25dv_data), GFP_KERNEL);
+	if (!data)
+		goto err_mem;
+	data->data = kmalloc(sizeof(u8)*mem_config[id->driver_data], GFP_KERNEL);
+	if (!data->data)
+		goto err_mem7;
+	sys_data = devm_kzalloc(&client_sys_area->dev, sizeof(struct st25dv_data)
+				, GFP_KERNEL);
+	if (!sys_data)
+		goto err_mem6;
+	sys_data->data = kmalloc(sizeof(u8)*SYS_MEM_SIZE, GFP_KERNEL);
+	if (!sys_data->data)
+		goto err_mem5;
+	dyn_reg_data = kmalloc(sizeof(struct st25dv_data), GFP_KERNEL);
+	if(!dyn_reg_data)
+		goto err_mem4;
+	dyn_reg_data->data = kmalloc(sizeof(u8)*DYN_REG_SIZE, GFP_KERNEL);
+	if (!dyn_reg_data->data)
+		goto err_mem3;
+	mailbox_data = kmalloc(sizeof(struct st25dv_data), GFP_KERNEL);
+	if(!mailbox_data)
+		goto err_mem2;
+        mailbox_data->data = kmalloc(sizeof(u8)*MAILBOX_MEM_SIZE, GFP_KERNEL);
+	if (!mailbox_data->data)
+		goto err_mem1;
+
+	st25dv_lock = kmalloc(sizeof(struct mutex), GFP_KERNEL);
+	if (!st25dv_lock)
+	        goto err_mem0;
+	mutex_init(st25dv_lock);
+	data->client =  client;
+	sys_data->client = client_sys_area;
+	mailbox_data->client = client;
+	dyn_reg_data->client = client;
+	memset(data->data, 0xff, mem_config[id->driver_data]);
+	memset(sys_data->data, 0xff, SYS_MEM_SIZE);
+	memset(dyn_reg_data->data, 0xff, DYN_REG_SIZE);
+	memset(mailbox_data->data, 0xff, MAILBOX_MEM_SIZE);
+
+	/*set circular linked list and shared mutex*/
+	data->next = dyn_reg_data;
+	data->update_lock = st25dv_lock;
+	dyn_reg_data->next = mailbox_data;
+	dyn_reg_data->update_lock = st25dv_lock;
+	mailbox_data->next = sys_data;
+        mailbox_data->update_lock = st25dv_lock;
+	sys_data->next = data;
+	sys_data->update_lock = st25dv_lock;
+
+	memcpy(&mailbox_data->bin_attr, &st25dv_mailbox_attr, sizeof(struct bin_attribute));
+	memcpy(&dyn_reg_data->bin_attr, &st25dv_dyn_reg_attr, sizeof(struct bin_attribute));
+	memcpy(&sys_data->bin_attr, &st25dv_sys_attr, sizeof(struct bin_attribute));
+	memcpy(&data->bin_attr, &st25dv_user_attr, sizeof(struct bin_attribute));
+	data->bin_attr.size = mem_config[id->driver_data];
+	data->type = USER_AREA;
+	dyn_reg_data->type = DYN_REG_AREA;
+	sys_data->type = SYS_AREA;
+	mailbox_data->type = MAILBOX_AREA;
+	i2c_set_clientdata(client, data);
+	i2c_set_clientdata(client_sys_area, sys_data);
+
+	/* create tree sysfs eeprom files to for pwd, user area,
+	 system area and dynamic registers */
+	status = sysfs_create_bin_file(&client->dev.kobj, &data->bin_attr);
+	if(status < 0)
+		goto err_sysfs;
+	status = sysfs_create_bin_file(&client_sys_area->dev.kobj, &sys_data->bin_attr);
+	if(status < 0)
+		goto err_sysfs4;
+	status = sysfs_create_bin_file(&client->dev.kobj, &dyn_reg_data->bin_attr);
+	if(status < 0)
+		goto err_sysfs3;
+	status = sysfs_create_bin_file(&client_sys_area->dev.kobj, &st25dv_w_pwd_attr);
+	if(status < 0)
+		goto err_sysfs2;
+	status = sysfs_create_bin_file(&client_sys_area->dev.kobj, &st25dv_p_pwd_attr);
+	if(status < 0)
+		goto err_sysfs1;
+	status = sysfs_create_bin_file(&client->dev.kobj, &mailbox_data->bin_attr);
+	if(status < 0)
+		goto err_sysfs0;
+	pr_warn("st25dv eeprom create bin file.\n");
+	return status;
+err_sysfs0:
+	sysfs_remove_bin_file(&client_sys_area->dev.kobj, &st25dv_p_pwd_attr);
+err_sysfs1:
+	sysfs_remove_bin_file(&client_sys_area->dev.kobj, &st25dv_w_pwd_attr);
+err_sysfs2:
+	sysfs_remove_bin_file(&client->dev.kobj, &dyn_reg_data->bin_attr);
+err_sysfs3:
+	sysfs_remove_bin_file(&client_sys_area->dev.kobj, &sys_data->bin_attr);
+err_sysfs4:
+	sysfs_remove_bin_file(&client->dev.kobj, &data->bin_attr);
+err_sysfs:
+	pr_warn("fail to create bin file.\n");
+err_mem0:
+	kfree(mailbox_data->data);
+err_mem1:
+	kfree(mailbox_data);
+err_mem2:
+	kfree(dyn_reg_data->data);
+err_mem3:
+	kfree(dyn_reg_data);
+err_mem4:
+	kfree(sys_data->data);
+err_mem5:
+	devm_kfree(&client_sys_area->dev, sys_data);
+	i2c_unregister_device(client_sys_area);
+err_mem6:
+	kfree(data->data);
+err_mem7:
+	devm_kfree(&client->dev, data);
+err_mem:
+	pr_warn("not enougth memory.\n");
+	return -ENOMEM;
+}
+
+static void st25dv_remove(struct i2c_client *client)
+{
+	struct st25dv_data *data = i2c_get_clientdata(client);
+	struct st25dv_data *tmp_data2, *tmp_data;
+	struct i2c_client *client_sys_area;
+
+	/*get system area client*/
+	tmp_data = data;
+	while(tmp_data->type != SYS_AREA)
+		 tmp_data = tmp_data->next;
+	client_sys_area = tmp_data->client;
+	/*remove pwd sysfs files*/
+	sysfs_remove_bin_file(&client_sys_area->dev.kobj, &st25dv_p_pwd_attr);
+	sysfs_remove_bin_file(&client_sys_area->dev.kobj, &st25dv_w_pwd_attr);
+	/*free all st25dv data allocations*/
+	tmp_data = data->next;
+	while(tmp_data != data){
+		/*remove areas sysfs files*/
+		sysfs_remove_bin_file(&tmp_data->client->dev.kobj, &tmp_data->bin_attr);
+		tmp_data2 = tmp_data;
+		kfree(tmp_data->data);
+		tmp_data = tmp_data->next;
+		/*sys_area data will be free by i2c_unregister_device*/
+		if(tmp_data2->type != SYS_AREA)
+			kfree(tmp_data2);
+	}
+	/*free st25dv user mem data*/
+	sysfs_remove_bin_file(&data->client->dev.kobj, &tmp_data->bin_attr);
+	kfree(data->data);
+	kfree(data->update_lock);
+	/*unregister dummy device*/
+	i2c_unregister_device(client_sys_area);
+
+	return;
+}
+
+static const struct i2c_device_id st25dv_id[] = {
+	{ "st25dv", 0 },
+	{ "st25dv04k", 1 },
+	{ "st25dv16k", 2 },
+	{ "st25dv64k", 3 },
+	{ }
+};
+
+static struct i2c_driver st25dv_driver = {
+	.driver = {
+		.name	= "st25dv",
+	},
+	.probe		= st25dv_probe,
+	.remove		= st25dv_remove,
+	.id_table	= st25dv_id,
+
+	.class		= I2C_CLASS_DDC | I2C_CLASS_SPD,
+	.detect		= st25dv_detect,
+	.address_list	= normal_i2c,
+};
+
+static int __init st25dv_i2c_init_driver(void)
+{
+	pr_info("init st25dv eeprom driver.\n");
+	return i2c_add_driver(&st25dv_driver);
+}
+
+static void __exit st25dv_i2c_exit_driver(void)
+{
+	pr_info("remove st25dv eeprom driver.\n");
+	i2c_del_driver(&st25dv_driver);
+}
+
+module_init(st25dv_i2c_init_driver);
+module_exit(st25dv_i2c_exit_driver);
+
+MODULE_INFO(intree, "y");
+MODULE_AUTHOR("Loïc Boban <loic.boban@gmail.com>");
+MODULE_DESCRIPTION("nfc/i2c eeprom st25dv driver");
+MODULE_LICENSE("GPL");

drivers/remoteproc/Kconfig

@@ -339,6 +339,19 @@ config TI_K3_DSP_REMOTEPROC
 	  It's safe to say N here if you're not interested in utilizing
 	  the DSP slave processors.
 
+config TI_K3_M4_REMOTEPROC
+	tristate "TI K3 M4 remoteproc support"
+	depends on ARCH_K3 || COMPILE_TEST
+	select MAILBOX
+	select OMAP2PLUS_MBOX
+	help
+	  Say m here to support TI's M4 remote processor subsystems
+	  on various TI K3 family of SoCs through the remote processor
+	  framework.
+
+	  It's safe to say N here if you're not interested in utilizing
+	  a remote processor.
+
 config TI_K3_R5_REMOTEPROC
 	tristate "TI K3 R5 remoteproc support"
 	depends on ARCH_K3

drivers/remoteproc/Makefile

@@ -37,5 +37,6 @@ obj-$(CONFIG_ST_REMOTEPROC)		+= st_remoteproc.o
 obj-$(CONFIG_ST_SLIM_REMOTEPROC)	+= st_slim_rproc.o
 obj-$(CONFIG_STM32_RPROC)		+= stm32_rproc.o
 obj-$(CONFIG_TI_K3_DSP_REMOTEPROC)	+= ti_k3_dsp_remoteproc.o
+obj-$(CONFIG_TI_K3_M4_REMOTEPROC)	+= ti_k3_m4_remoteproc.o
 obj-$(CONFIG_TI_K3_R5_REMOTEPROC)	+= ti_k3_r5_remoteproc.o
 obj-$(CONFIG_XLNX_R5_REMOTEPROC)	+= xlnx_r5_remoteproc.o

drivers/remoteproc/omap_remoteproc.h

@@ -59,7 +59,9 @@ enum omap_rp_mbox_messages {
 	RP_MBOX_SUSPEND_SYSTEM	= 0xFFFFFF11,
 	RP_MBOX_SUSPEND_ACK	= 0xFFFFFF12,
 	RP_MBOX_SUSPEND_CANCEL	= 0xFFFFFF13,
-	RP_MBOX_END_MSG		= 0xFFFFFF14,
+	RP_MBOX_SHUTDOWN        = 0xFFFFFF14,
+	RP_MBOX_SHUTDOWN_ACK    = 0xFFFFFF15,
+	RP_MBOX_END_MSG		= 0xFFFFFF16,
 };
 
 #endif /* _OMAP_RPMSG_H */

drivers/spi/spi-cadence-quadspi.c

@@ -29,6 +29,7 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/spi-mem.h>
 #include <linux/timer.h>
+#include <linux/string.h>
 
 #define CQSPI_NAME			"cadence-qspi"
 #define CQSPI_MAX_CHIPSELECT		16
@@ -1276,6 +1277,10 @@ static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata,
 	 */
 	if (!op->cmd.dtr && cqspi->use_direct_mode &&
 	    cqspi->use_direct_mode_wr && ((to + len) <= cqspi->ahb_size)) {
+		pr_info("TWx: %s:%d - Writing <%lu> bytes with offset <%lld> to ahb_base <%p>\n",
+			__func__, __LINE__, len, to, cqspi->ahb_base + to);
+		print_hex_dump(KERN_INFO, "TWx write buf:", DUMP_PREFIX_OFFSET,
+			       16, 1, buf, len, true);
 		memcpy_toio(cqspi->ahb_base + to, buf, len);
 		return cqspi_wait_idle(cqspi);
 	}
@@ -1701,6 +1706,10 @@ static int cqspi_probe(struct platform_device *pdev)
 	struct cqspi_st *cqspi;
 	int ret;
 	int irq;
+	const u_char *test_buf = "TWX-111-000";
+	loff_t to;
+
+	pr_info("TWx: %s:%d.\n", __func__, __LINE__);
 
 	host = devm_spi_alloc_host(&pdev->dev, sizeof(*cqspi));
 	if (!host) {
@@ -1752,6 +1761,20 @@ static int cqspi_probe(struct platform_device *pdev)
 	cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start;
 	cqspi->ahb_size = resource_size(res_ahb);
 
+	pr_info("TWx: %s:%d ahb_base %p.\n",
+		__func__, __LINE__,
+		cqspi->ahb_base);
+
+	pr_info("TWx: %s:%d mmap_phys_base %pad\n",
+		__func__, __LINE__,
+		&cqspi->mmap_phys_base);
+
+	/* print_hex_dump_bytes("TWx 64 byte ahb_base dump:", DUMP_PREFIX_OFFSET,
+			     cqspi->ahb_base, 64); */
+
+	print_hex_dump(KERN_INFO, "TWx ahb_base:", DUMP_PREFIX_OFFSET,
+		       16, 1, cqspi->ahb_base, 64, true);
+
 	init_completion(&cqspi->transfer_complete);
 
 	/* Obtain IRQ line. */
@@ -1874,7 +1897,27 @@ static int cqspi_probe(struct platform_device *pdev)
 		goto probe_setup_failed;
 	}
 
+	pr_info("TWx: %s:%d cqspi->use_direct_mode (%s).\n",
+		__func__, __LINE__,
+		cqspi->use_direct_mode ? "enabled" : "disabled");
+	pr_info("TWx: %s:%d cqspi->use_direct_mode_wr (%s).\n",
+		__func__, __LINE__,
+		cqspi->use_direct_mode_wr ? "enabled" : "disabled");
+
+	to = 5;
+
+	pr_info("TWx: %s:%d - Writing %s, size %lu to ahb_base %lld\n",
+		__func__, __LINE__,
+		test_buf, strlen(test_buf), to);
+
+	memcpy_toio(cqspi->ahb_base + to, test_buf, strlen(test_buf));
+	cqspi_wait_idle(cqspi);
+
+	print_hex_dump(KERN_INFO, "TWx ahb_base:", DUMP_PREFIX_OFFSET,
+		       16, 1, cqspi->ahb_base, 64, true);
+
 	return 0;
+
 probe_setup_failed:
 	cqspi_controller_enable(cqspi, 0);
 probe_reset_failed:

drivers/spi/spi-kbus.c

@@ -37,6 +37,8 @@
 #define KBUS_DUMMY_BIT_PER_WORD 8
 #define KBUS_DUMMY_SPEED 1000000
 
+#define KBUS_CMD_UPDATE 0xa3
+
 #if KBUS_TESTING
 struct wago_trace_data wago_ktest;
 #endif
@@ -52,7 +54,7 @@ static struct cdev kbus_cdev;
 /* sysfs */
 extern struct class *wsysinit_sysfs_class;
 extern struct device *wsysinit_sysfs_device;
-static struct device *kbus_device;
+static struct device *kbus_device = NULL;
 
 int kbus_wait_for_gpio(int gpio)
 {
@@ -107,7 +109,7 @@ int kbus_wait_for_event(int *event)
 	return 0;
 }
 
-static irqreturn_t kbus_isr(int irq, void *dev)
+static irqreturn_t kbus_infineon_isr(int irq, void *dev)
 {
 	struct kbus_drv_data *kdrvdata = dev_get_drvdata(kbus_device);
 
@@ -121,6 +123,42 @@ static irqreturn_t kbus_isr(int irq, void *dev)
 	return IRQ_HANDLED;
 }
 
+static irqreturn_t kbus_renesas_isr(int irq, void *dev)
+{
+	struct kbus_drv_data *kdrvdata = dev_get_drvdata(kbus_device);
+
+	trace_pxc_kbus(__func__, "kbus-irq:in");
+
+	if (unlikely(kdrvdata->cmdsel)) {
+		if (kdrvdata->kbus_ign_reset_irq) {
+			kdrvdata->kbus_ign_reset_irq = 0;
+			init_waitqueue_head(&kdrvdata->kbus_irq_wq);
+			// trace for command 0xA3 find in libkbusfwload library
+			trace_pxc_kbus(__func__, "kbus-irq: edge falling after command\
+					SCPU_COMMAND_START_UPDATE [0xa3]: ignore irq");
+			return IRQ_HANDLED;
+		}
+
+		int gpio_value = gpiod_get_value(kdrvdata->gpio_nrdy);
+
+		if (gpio_value) {
+			trace_pxc_kbus(__func__, "kbus-irq: edge rising");
+		} else if (kdrvdata->kbus_ign_irq) {
+			trace_pxc_kbus(__func__, "kbus-irq: edge falling during command\
+					SCPU_COMMAND_START_UPDATE [0xa3]");
+			kdrvdata->kbus_ign_reset_irq = 1;
+		} else {
+			trace_pxc_kbus(__func__, "kbus-irq: edge falling");
+		}
+	}
+
+	kdrvdata->kbus_irq_state = 0; /* attention: changed polarisation */
+	wake_up(&kdrvdata->kbus_irq_wq);
+
+	trace_pxc_kbus(__func__, "kbus-irq:out");
+	return IRQ_HANDLED;
+}
+
 static ssize_t kbus_write(struct file *filp, const char __user *buf,
 			  size_t count, loff_t *f_pos)
 {
@@ -185,19 +223,26 @@ static struct task_struct *find_dma_task(void)
 
 void kbus_boost_dma_task(u8 enable)
 {
-	struct kbus_drv_data *kdrvdata = dev_get_drvdata(kbus_device);
-	struct sched_param boost_param = {
-		.sched_priority = enable ? kdrvdata->kbus_dma_boost_prio :
-					   kdrvdata->kbus_dma_normal_prio
-	};
+	struct kbus_drv_data *kdrvdata = NULL;
+	struct sched_param boost_param;
 
-	if (kdrvdata->dma_task) {
-		if ((enable && !kdrvdata->kbus_dma_boost_en) ||
-		    (!enable && kdrvdata->kbus_dma_boost_en)) {
-			kdrvdata->kbus_dma_boost_en =
-				!kdrvdata->kbus_dma_boost_en;
-			sched_setscheduler(kdrvdata->dma_task, SCHED_FIFO,
-					   &boost_param);
+	if (kbus_device) {
+		kdrvdata = dev_get_drvdata(kbus_device);
+
+		if (kdrvdata) {
+			boost_param.sched_priority = enable ?
+				kdrvdata->kbus_dma_boost_prio :
+				kdrvdata->kbus_dma_normal_prio;
+
+			if (kdrvdata->dma_task) {
+				if ((enable && !kdrvdata->kbus_dma_boost_en) ||
+				    (!enable && kdrvdata->kbus_dma_boost_en)) {
+					kdrvdata->kbus_dma_boost_en =
+						!kdrvdata->kbus_dma_boost_en;
+					sched_setscheduler(kdrvdata->dma_task, SCHED_FIFO,
+							   &boost_param);
+				}
+			}
 		}
 	}
 }
@@ -637,11 +682,12 @@ static long kbus_ioctl(struct file *file, uint cmd, ulong arg)
 	struct kbus_drv_data *kdrvdata = dev_get_drvdata(kbus_device);
 	struct spi_device *spi = kdrvdata->spi;
 
+	kdrvdata->kbus_ign_irq = 0;
 	switch (cmd) {
 	case KBUS_IOC_CMD: /* FIXME */
 	{
 		struct kbus_cmd kcmd;
-		struct kbus_cmd __user *kcmd_user;
+		struct kbus_cmd __user *kcmd_user = (struct kbus_cmd __user *)arg;
 
 		trace_pxc_kbus(__func__,
 			       "KCMD: Enter: Set kbus_irq_state to 1.");
@@ -656,13 +702,21 @@ static long kbus_ioctl(struct file *file, uint cmd, ulong arg)
 		/* Indicate Transfer Start */
 		gpiod_set_value(kdrvdata->gpio_nirq, 0);
 
-		kcmd_user = (struct kbus_cmd __user *)arg;
 		if (copy_from_user(&kcmd, kcmd_user, sizeof(kcmd))) {
 			/* release the irq pin */
 			gpiod_set_value(kdrvdata->gpio_nirq, 1);
 			return -EFAULT;
 		}
 
+		u8 tx_byte;
+		if (!copy_from_user(&tx_byte, kcmd.tx_buf, sizeof(tx_byte))) {
+			if ((int)tx_byte == KBUS_CMD_UPDATE) {
+				kdrvdata->kbus_ign_irq = 1;
+				trace_pxc_kbus(__func__, "KCMD: Update cmd (0xa3)");
+				pr_info("%s: KCMD: Update cmd (0xa3)\n", __func__);
+			}
+		}
+
 		ret = kbus_cmd_txrx(&kcmd);
 		if (ret < 0) {
 			/* release the irq pin */
@@ -1071,6 +1125,8 @@ static struct kbus_drv_data *kbus_probe_dt(struct spi_device *spi)
 		}
 	}
 
+	kdrvdata->kbus_renesas = of_property_read_bool(np, "kbus,renesas");
+
 	kdrvdata->kbus_irq = gpiod_to_irq(kdrvdata->gpio_nrdy);
 	kdrvdata->spi = spi;
 
@@ -1098,6 +1154,7 @@ static int kbus_probe(struct spi_device *spi)
 	int ret = 0;
 	u8 save = 0;
 	struct kbus_drv_data *kdrvdata;
+	irqreturn_t (*kbus_isr)(int, void *);
 
 	if (!spi->dev.of_node) {
 		pr_err("WAGO KBUS Driver: No DT node found!\n");
@@ -1110,6 +1167,14 @@ static int kbus_probe(struct spi_device *spi)
 
 	init_waitqueue_head(&kdrvdata->kbus_irq_wq);
 
+	if (kdrvdata->kbus_renesas)
+		kbus_isr = kbus_renesas_isr;
+	else
+		kbus_isr = kbus_infineon_isr;
+
+	pr_info("%s: %s is used\n", __func__, kdrvdata->kbus_renesas?
+		"renesas" : "infineon");
+
 	ret = request_irq(kdrvdata->kbus_irq, kbus_isr,
 			  IRQF_SHARED | IRQ_TYPE_EDGE_BOTH,
 			  "kbus", &kbus_dev);
@@ -1123,6 +1188,9 @@ static int kbus_probe(struct spi_device *spi)
 	KBUS_DISABLE_IRQ(kdrvdata->kbus_irq);
 	kdrvdata->kbus_irq_enabled = 0;
 
+	/* disable ignore of irq after 0xa3 (update) cmd */
+	kdrvdata->kbus_ign_reset_irq = 0;
+
 	/* allocate memory */
 	if (kdrvdata->use_dma) {
 		spi->dev.coherent_dma_mask = ~0; /* why that? */

drivers/spi/spi-omap2-mcspi.c

@@ -657,9 +657,11 @@ omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
 	int			wait_res;
 
 #ifdef CONFIG_SPI_KBUS_OMAP_EXTENSION
-	trace_pxc_kbus(__func__, "enter");
+	if (spi->dev.driver == &kbus_driver.driver) {
+		trace_pxc_kbus(__func__, "enter");
 
-	kbus_boost_dma_task(1);
+		kbus_boost_dma_task(1);
+	}
 #endif
 
 	mcspi = spi_controller_get_devdata(spi->controller);
@@ -777,9 +779,11 @@ omap2_mcspi_txrx_dma_eow(struct spi_device *spi, struct spi_transfer *xfer)
 	int ret;
 
 #ifdef CONFIG_SPI_KBUS_OMAP_EXTENSION
-	trace_pxc_kbus(__func__, "enter");
+	if (spi->dev.driver == &kbus_driver.driver) {
+		trace_pxc_kbus(__func__, "enter");
 
-	kbus_boost_dma_task(1);
+		kbus_boost_dma_task(1);
+	}
 #endif
 
 	mcspi = spi_controller_get_devdata(spi->controller);
@@ -866,10 +870,12 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
 	word_len = cs->word_len;
 
 #ifdef CONFIG_SPI_KBUS_OMAP_EXTENSION
-	trace_pxc_kbus(__func__, "enter");
-	kbus_dbg("%s[%d]: count: %d\n", __func__,__LINE__, count);
+	if (spi->dev.driver == &kbus_driver.driver) {
+		trace_pxc_kbus(__func__, "enter");
+		kbus_dbg("%s[%d]: count: %d\n", __func__,__LINE__, count);
 
-	kbus_boost_dma_task(0);
+		kbus_boost_dma_task(0);
+	}
 #endif
 
 	l = mcspi_cached_chconf0(spi);
@@ -1568,7 +1574,7 @@ static int omap2_mcspi_transfer_one(struct spi_controller *ctlr,
 			kcmd_txbuf = (u16 *) t->tx_buf;
 			/* wait for READYn IRQ from xe164 */
 
-			trace_pxc_kbus(__func__, "TX0");
+			trace_pxc_kbus(__func__, "TX0: Wait for nrdy");
 			kbus_dbg("%s: irq timeout is %dms\n",
 				 __func__, kdrvdata->timeout_ms);
 			tmp_ret = wait_event_interruptible_timeout(kdrvdata->kbus_irq_wq,

drivers/spi/spi.c

@@ -2926,7 +2926,7 @@ struct spi_controller *__spi_alloc_controller(struct device *dev,
 	mutex_init(&ctlr->io_mutex);
 	mutex_init(&ctlr->add_lock);
 	ctlr->bus_num = -1;
-	ctlr->num_chipselect = 1;
+	ctlr->num_chipselect = 4;
 	ctlr->slave = slave;
 	if (IS_ENABLED(CONFIG_SPI_SLAVE) && slave)
 		ctlr->dev.class = &spi_slave_class;

drivers/uio/uio.c

@@ -730,19 +730,25 @@ static int uio_mmap_physical(struct vm_area_struct *vma)
 	int mi = uio_find_mem_index(vma);
 	struct uio_mem *mem;
 
+	pr_info("TWx: %s:%d\n",	__func__, __LINE__);
+
 	if (mi < 0)
 		return -EINVAL;
 	mem = idev->info->mem + mi;
 
+	pr_info("TWx: %s:%d\n",	__func__, __LINE__);
 	if (mem->addr & ~PAGE_MASK)
 		return -ENODEV;
+	pr_info("TWx: %s:%d\n",	__func__, __LINE__);
 	if (vma->vm_end - vma->vm_start > mem->size)
 		return -EINVAL;
 
+	pr_info("TWx: %s:%d\n",	__func__, __LINE__);
 	vma->vm_ops = &uio_physical_vm_ops;
 	if (idev->info->mem[mi].memtype == UIO_MEM_PHYS)
 		vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
 
+	pr_info("TWx: %s:%d\n",	__func__, __LINE__);
 	/*
 	 * We cannot use the vm_iomap_memory() helper here,
 	 * because vma->vm_pgoff is the map index we looked
@@ -800,10 +806,13 @@ static int uio_mmap(struct file *filep, struct vm_area_struct *vma)
 	switch (idev->info->mem[mi].memtype) {
 	case UIO_MEM_IOVA:
 	case UIO_MEM_PHYS:
+		pr_info("TWx: %s:%d\n",	__func__, __LINE__);
 		ret = uio_mmap_physical(vma);
+		pr_info("TWx: %s:%d ret = %d\n",__func__, __LINE__, ret);
 		break;
 	case UIO_MEM_LOGICAL:
 	case UIO_MEM_VIRTUAL:
+		pr_info("TWx: %s:%d\n",	__func__, __LINE__);
 		ret = uio_mmap_logical(vma);
 		break;
 	default:

include/linux/spi/kbus.h

@@ -76,6 +76,8 @@ struct kbus_drv_data {
 	int kbus_irq;
 	int kbus_irq_enabled;
 	int kbus_irq_state;
+	int kbus_ign_irq;
+	int kbus_ign_reset_irq;
 	struct task_struct
 		*dma_task; /* task pointer to boost the dma task if necessary */
 	bool kbus_dma_boost_en;
@@ -96,6 +98,7 @@ struct kbus_drv_data {
 	wait_queue_head_t kbus_irq_wq;
 	struct spi_device *spi;
 	const char *kbus_tty_device_name;
+	bool kbus_renesas;
 };
 
 /* For userspace ioctl communication */

jenkins/am3xxx_pfc_generic.jenkinsfile

@@ -170,18 +170,24 @@ makefileProject {
               "LG_FIRMWARE_PFCXXX_BUILDNUMBER=latest",
               "LG_FIRMWARE_PFCG2_BUILDINFO_BUILDNAME=${artifactoryBuildPFC ?: this.getBuildname(runWrapperPFCG2).replace('/', ' :: ').replace('%2F', ' :: ')}",
               "LG_FIRMWARE_PFCG2_BUILDNUMBER=${buildNumberPFC ?: this.getBuildnumber(runWrapperPFCG2)}",
+              "LG_FIRMWARE_LOCAL_WORKSPACE_PATH=",
+              "LG_FIRMWARE_WORKSPACE=artifactory",
               "LG_BAREBOX_AM335X_BUILDINFO_BUILDNAME=${artifactoryBuildBareboxAm335x ?: this.getBuildname(runWrapperBareboxAM335x).replace('/', ' :: ').replace('%2F', ' :: ')}",
               "LG_BAREBOX_AM335X_BUILDNUMBER=${buildNumberBareboxAm335x ?: this.getBuildnumber(runWrapperBareboxAM335x)}",
+              "LG_BOOTLOADER_LOCAL_WORKSPACE_PATH=",
+              "LG_BOOTLOADER_WORKSPACE=artifactory",
               "LG_BAREBOX_BACKUP_AM335X_BUILDINFO_BUILDNAME=${artifactoryBuildBareboxAm335xBackup}",
               "LG_BAREBOX_BACKUP_AM335X_BUILDNUMBER=${buildNumberBareboxAm335xBackup}",
+              "LG_BOOTLOADER_BACKUP_LOCAL_WORKSPACE_PATH=",
+              "LG_BOOTLOADER_BACKUP_WORKSPACE=artifactory",
               "LG_BAREBOX_AM35XX_BUILDINFO_BUILDNAME=${artifactoryBuildBareboxAm35xx ?: this.getBuildname(runWrapperBareboxAM35xx).replace('/', ' :: ').replace('%2F', ' :: ')}",
               "LG_BAREBOX_AM35XX_BUILDNUMBER=${buildNumberBareboxAm35xx ?: this.getBuildnumber(runWrapperBareboxAM35xx)}",
               "LG_BAREBOX_BACKUP_AM35XX_BUILDINFO_BUILDNAME=${artifactoryBuildBareboxAm35xxBackup}",
               "LG_BAREBOX_BACKUP_AM35XX_BUILDNUMBER=${buildNumberBareboxAm35xxBackup}",
-              "LG_BAREBOX_LOCAL_WORKSPACE_PATH=",
               "LG_KERNEL_AM3XXX_BUILDINFO_BUILDNAME=${artifactoryBuildKernel ?: buildPathKernel.replace('/', ' :: ').replace('%2F', ' :: ')}",
               "LG_KERNEL_AM3XXX_BUILDNUMBER=${buildNumberKernel}",
-              "LG_KERNEL_LOCAL_WORKSPACE_PATH=../../.build/deploy"
+              "LG_KERNEL_LOCAL_WORKSPACE_PATH=../../.build/deploy",
+              "LG_KERNEL_WORKSPACE=local"
             ])
           }
         }

jenkins/am6xxx.jenkinsfile

@@ -149,14 +149,20 @@ makefileProject {
                "LG_DEPLOY_BUDDY_STATE=deploy_firmware_to_flash",
                "LG_FIRMWARE_PFC300_BUILDINFO_BUILDNAME=${artifactoryBuildPFC300 ?: this.getBuildname(runWrapperPFC300).replace('/', ' :: ').replace('%2F', ' :: ')}",
                "LG_FIRMWARE_PFC300_BUILDNUMBER=${buildNumberPFC300 ?: this.getBuildnumber(runWrapperPFC300)}",
+               "LG_FIRMWARE_LOCAL_WORKSPACE_PATH=",
+               "LG_FIRMWARE_WORKSPACE=artifactory",
                "LG_U_BOOT_AM6XXX_BUILDINFO_BUILDNAME=${artifactoryBuildUBoot ?: this.getBuildname(runWrapperUBoot).replace('/', ' :: ').replace('%2F', ' :: ')}",
                "LG_U_BOOT_AM6XXX_BUILDNUMBER=${buildNumberUBoot ?: this.getBuildnumber(runWrapperUBoot)}",
+               "LG_BOOTLOADER_LOCAL_WORKSPACE_PATH=",
+               "LG_BOOTLOADER_WORKSPACE=artifactory",
                "LG_U_BOOT_BACKUP_AM6XXX_BUILDINFO_BUILDNAME=${artifactoryBuildUBootFastboot}",
                "LG_U_BOOT_BACKUP_AM6XXX_BUILDNUMBER=${buildNumberUBootFastboot}",
-               "LG_BAREBOX_LOCAL_WORKSPACE_PATH=",
+               "LG_BOOTLOADER_BACKUP_LOCAL_WORKSPACE_PATH=",
+               "LG_BOOTLOADER_BACKUP_WORKSPACE=artifactory",
                "LG_KERNEL_AM6XXX_BUILDINFO_BUILDNAME=${artifactoryBuildKernel ?: buildPathKernel.replace('/', ' :: ').replace('%2F', ' :: ')}",
                "LG_KERNEL_AM6XXX_BUILDNUMBER=${buildNumberKernel}",
-               "LG_KERNEL_LOCAL_WORKSPACE_PATH=../../.build/deploy"
+               "LG_KERNEL_LOCAL_WORKSPACE_PATH=../../.build/deploy",
+               "LG_KERNEL_WORKSPACE=local"
             ])
           }
         }

jenkins/am6xxx_ems.jenkinsfile

@@ -149,14 +149,20 @@ makefileProject {
       //          "LG_DEPLOY_BUDDY_STATE=deploy_firmware_to_flash",
       //          "LG_FIRMWARE_PFC300_BUILDINFO_BUILDNAME=${artifactoryBuildPFC300 ?: this.getBuildname(runWrapperPFC300).replace('/', ' :: ').replace('%2F', ' :: ')}",
       //          "LG_FIRMWARE_PFC300_BUILDNUMBER=${buildNumberPFC300 ?: this.getBuildnumber(runWrapperPFC300)}",
+      //          "LG_FIRMWARE_LOCAL_WORKSPACE_PATH=",
+      //          "LG_FIRMWARE_WORKSPACE=artifactory",
       //          "LG_U_BOOT_AM6XXX_BUILDINFO_BUILDNAME=${artifactoryBuildUBoot ?: this.getBuildname(runWrapperUBoot).replace('/', ' :: ').replace('%2F', ' :: ')}",
       //          "LG_U_BOOT_AM6XXX_BUILDNUMBER=${buildNumberUBoot ?: this.getBuildnumber(runWrapperUBoot)}",
+      //          "LG_BOOTLOADER_LOCAL_WORKSPACE_PATH=",
+      //          "LG_BOOTLOADER_WORKSPACE=artifactory",
       //          "LG_U_BOOT_BACKUP_AM6XXX_BUILDINFO_BUILDNAME=${artifactoryBuildUBootFastboot}",
       //          "LG_U_BOOT_BACKUP_AM6XXX_BUILDNUMBER=${buildNumberUBootFastboot}",
-      //          "LG_BAREBOX_LOCAL_WORKSPACE_PATH=",
+      //          "LG_BOOTLOADER_BACKUP_LOCAL_WORKSPACE_PATH=",
+      //          "LG_BOOTLOADER_BACKUP_WORKSPACE=artifactory",
       //          "LG_KERNEL_AM6XXX_BUILDINFO_BUILDNAME=${artifactoryBuildKernel ?: buildPathKernel.replace('/', ' :: ').replace('%2F', ' :: ')}",
       //          "LG_KERNEL_AM6XXX_BUILDNUMBER=${buildNumberKernel}",
-      //          "LG_KERNEL_LOCAL_WORKSPACE_PATH=../.build/deploy"
+      //          "LG_KERNEL_LOCAL_WORKSPACE_PATH=../.build/deploy",
+      //          "LG_KERNEL_WORKSPACE=local"
       //       ])
       //     }
       //   }

jenkins/imx6_vtpctp.jenkinsfile

@@ -154,16 +154,22 @@ makefileProject {
               "LG_DEPLOY_BUDDY_STATE=deploy_firmware_to_flash",
               "LG_FIRMWARE_VTPCTP_BUILDINFO_BUILDNAME=${artifactoryBuildPFC ?: this.getBuildname(runWrapperPFC).replace('/', ' :: ').replace('%2F', ' :: ')}",
               "LG_FIRMWARE_VTPCTP_BUILDNUMBER=${buildNumberPFC ?: this.getBuildnumber(runWrapperPFC)}",
+              "LG_FIRMWARE_PFCG2_BUILDINFO_BUILDNAME=firmware :: pfc :: pfc-g2 :: main",
+              "LG_FIRMWARE_PFCG2_BUILDNUMBER=latest",
+              "LG_FIRMWARE_LOCAL_WORKSPACE_PATH=",
+              "LG_FIRMWARE_WORKSPACE=artifactory",
               "LG_BAREBOX_IMX6_BUILDINFO_BUILDNAME=${artifactoryBuildBarebox ?: this.getBuildname(runWrapperBarebox).replace('/', ' :: ').replace('%2F', ' :: ')}",
               "LG_BAREBOX_IMX6_BUILDNUMBER=${buildNumberBarebox ?: this.getBuildnumber(runWrapperBarebox)}",
+              "LG_BOOTLOADER_LOCAL_WORKSPACE_PATH=",
+              "LG_BOOTLOADER_WORKSPACE=artifactory",
               "LG_BAREBOX_BACKUP_IMX6_BUILDINFO_BUILDNAME=${artifactoryBuildBareboxBackup}",
               "LG_BAREBOX_BACKUP_IMX6_BUILDNUMBER=${buildNumberBareboxBackup}",
-              "LG_BAREBOX_LOCAL_WORKSPACE_PATH=",
+              "LG_BOOTLOADER_BACKUP_LOCAL_WORKSPACE_PATH=",
+              "LG_BOOTLOADER_BACKUP_WORKSPACE=artifactory",
               "LG_KERNEL_IMX6_BUILDINFO_BUILDNAME=${artifactoryBuildKernel ?: buildPathKernel.replace('/', ' :: ').replace('%2F', ' :: ')}",
               "LG_KERNEL_IMX6_BUILDNUMBER=${buildNumberKernel}",
               "LG_KERNEL_LOCAL_WORKSPACE_PATH=../../.build/deploy",
-              "LG_FIRMWARE_PFCG2_BUILDINFO_BUILDNAME=firmware :: pfc :: pfc-g2 :: main",
-              "LG_FIRMWARE_PFCG2_BUILDNUMBER=latest",
+              "LG_KERNEL_WORKSPACE=local",
               "LG_BAREBOX_AM335X_BUILDINFO_BUILDNAME=firmware :: pfc :: barebox :: am335x_pfc :: master",
               "LG_BAREBOX_AM335X_BUILDNUMBER=latest",
               "LG_BAREBOX_BACKUP_AM335X_BUILDINFO_BUILDNAME=firmware :: pfc :: barebox :: am335x_pfc :: release_w04.01.09_14",

jenkins/stm32mp1.jenkinsfile

@@ -151,16 +151,22 @@ makefileProject {
               "LG_DEPLOY_BUDDY_STATE=deploy_firmware_to_flash",
               "LG_FIRMWARE_CC100_BUILDINFO_BUILDNAME=${artifactoryBuildPFC ?: this.getBuildname(runWrapperPFC).replace('/', ' :: ').replace('%2F', ' :: ')}",
               "LG_FIRMWARE_CC100_BUILDNUMBER=${buildNumberPFC ?: this.getBuildnumber(runWrapperPFC)}",
+              "LG_FIRMWARE_PFCG2_BUILDINFO_BUILDNAME=firmware :: pfc :: pfc-g2 :: main",
+              "LG_FIRMWARE_PFCG2_BUILDNUMBER=latest",
+              "LG_FIRMWARE_LOCAL_WORKSPACE_PATH=",
+              "LG_FIRMWARE_WORKSPACE=artifactory",
               "LG_BAREBOX_STM32MP1_BUILDINFO_BUILDNAME=${artifactoryBuildBarebox ?: this.getBuildname(runWrapperBarebox).replace('/', ' :: ').replace('%2F', ' :: ')}",
               "LG_BAREBOX_STM32MP1_BUILDNUMBER=${buildNumberBarebox ?: this.getBuildnumber(runWrapperBarebox)}",
+              "LG_BOOTLOADER_LOCAL_WORKSPACE_PATH=",
+              "LG_BOOTLOADER_WORKSPACE=artifactory",
               "LG_BAREBOX_BACKUP_STM32MP1_BUILDINFO_BUILDNAME=${artifactoryBuildBareboxBackup}",
               "LG_BAREBOX_BACKUP_STM32MP1_BUILDNUMBER=${buildNumberBareboxBackup}",
-              "LG_BAREBOX_LOCAL_WORKSPACE_PATH=",
+              "LG_BOOTLOADER_BACKUP_LOCAL_WORKSPACE_PATH=",
+              "LG_BOOTLOADER_BACKUP_WORKSPACE=artifactory",
               "LG_KERNEL_STM32MP1_BUILDINFO_BUILDNAME=${artifactoryBuildKernel ?: buildPathKernel.replace('/', ' :: ').replace('%2F', ' :: ')}",
               "LG_KERNEL_STM32MP1_BUILDNUMBER=${buildNumberKernel}",
               "LG_KERNEL_LOCAL_WORKSPACE_PATH=../../.build/deploy",
-              "LG_FIRMWARE_PFCG2_BUILDINFO_BUILDNAME=firmware :: pfc :: pfc-g2 :: main",
-              "LG_FIRMWARE_PFCG2_BUILDNUMBER=latest",
+              "LG_KERNEL_WORKSPACE=local",
               "LG_BAREBOX_AM335X_BUILDINFO_BUILDNAME=firmware :: pfc :: barebox :: am335x_pfc :: master",
               "LG_BAREBOX_AM335X_BUILDNUMBER=latest",
               "LG_BAREBOX_BACKUP_AM335X_BUILDINFO_BUILDNAME=firmware :: pfc :: barebox :: am335x_pfc :: release_w04.01.09_14",

labgrid.basesoftware

@@ -1 +1 @@
-Subproject commit 284f50148360c4dbd8e243a42b2534a0e0b66804
+Subproject commit f1a3c1f8bb11d0944bb8fd84761ed34fd1cae40a

localversion-wago

@@ -1 +1 @@
--w05.07.06
+-w05.08.01