4b4719437d
clk: mediatek: add drivers for MT7988 SoC
...
Add APMIXED, ETH, INFRACFG and TOPCKGEN clock drivers which are
typical MediaTek designs.
Also add driver for XFIPLL clock generating the 156.25MHz clock for
the XFI SerDes. It needs an undocumented software workaround and has
an unknown internal design.
Signed-off-by: Sam Shih <sam.shih@mediatek.com >
Signed-off-by: Daniel Golle <daniel@makrotopia.org >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Link: https://lore.kernel.org/r/c7574d808e2da1a530182f0fd790c1337c336e1b.1702849494.git.daniel@makrotopia.org
[sboyd@kernel.org: Add module license to infracfg file]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-01-03 15:57:02 -08:00
0d2f2cefba
clk: mediatek: Add MT8188 adsp clock support
...
Add MT8188 adsp clock controller which provides clock gate
control for Audio DSP.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Link: https://lore.kernel.org/r/20230331123621.16167-20-Garmin.Chang@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-31 11:51:22 -07:00
1b5e5299dd
clk: mediatek: Add MT8188 imp i2c wrapper clock support
...
Add MT8188 imp i2c wrapper clock controllers which provide clock gate
control in I2C IP blocks.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Link: https://lore.kernel.org/r/20230331123621.16167-19-Garmin.Chang@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-31 11:51:22 -07:00
f42b9e9a43
clk: mediatek: Add MT8188 wpesys clock support
...
Add MT8188 wpesys clock controllers which provide clock gate
control in Wrapping Engine.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Link: https://lore.kernel.org/r/20230331123621.16167-18-Garmin.Chang@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-31 11:51:22 -07:00
4898e77f47
clk: mediatek: Add MT8188 vppsys1 clock support
...
Add MT8188 vppsys1 clock controller which provides clock gate
controller for Video Processor Pipe.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com >
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Link: https://lore.kernel.org/r/20230331123621.16167-17-Garmin.Chang@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-31 11:51:22 -07:00
eb48cccda0
clk: mediatek: Add MT8188 vppsys0 clock support
...
Add MT8188 vppsys0 clock controller which provides clock gate
controller for Video Processor Pipe.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com >
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Link: https://lore.kernel.org/r/20230331123621.16167-16-Garmin.Chang@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-31 11:51:22 -07:00
bb87c1109c
clk: mediatek: Add MT8188 vencsys clock support
...
Add MT8188 vencsys clock controllers which provide clock gate
control for video encoder.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Link: https://lore.kernel.org/r/20230331123621.16167-15-Garmin.Chang@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-31 11:51:21 -07:00
cfa4609f9b
clk: mediatek: Add MT8188 vdosys1 clock support
...
Add MT8188 vdosys1 clock controller which provides clock gate
control in video system. This is integrated with mtk-mmsys
driver which will populate device by platform_device_register_data
to start vdosys clock driver.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Link: https://lore.kernel.org/r/20230331123621.16167-14-Garmin.Chang@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-31 11:51:21 -07:00
e4aaa60eae
clk: mediatek: Add MT8188 vdosys0 clock support
...
Add MT8188 vdosys0 clock controller which provides clock gate
control in video system. This is integrated with mtk-mmsys
driver which will populate device by platform_device_register_data
to start vdosys clock driver.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Link: https://lore.kernel.org/r/20230331123621.16167-13-Garmin.Chang@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-31 11:51:21 -07:00
7275316389
clk: mediatek: Add MT8188 vdecsys clock support
...
Add MT8188 vdec clock controllers which provide clock gate
control for video decoder.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Link: https://lore.kernel.org/r/20230331123621.16167-12-Garmin.Chang@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-31 11:51:21 -07:00
3e26f30fe4
clk: mediatek: Add MT8188 mfgcfg clock support
...
Add MT8188 mfg clock controller which provides clock gate
control for GPU.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Link: https://lore.kernel.org/r/20230331123621.16167-11-Garmin.Chang@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-31 11:51:21 -07:00
49c9abe1c8
clk: mediatek: Add MT8188 ipesys clock support
...
Add MT8188 ipesys clock controller which provides clock gate
control for Image Process Engine.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Link: https://lore.kernel.org/r/20230331123621.16167-10-Garmin.Chang@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-31 11:51:21 -07:00
b281039a7b
clk: mediatek: Add MT8188 imgsys clock support
...
Add MT8188 imgsys clock controllers which provide clock gate
control for image IP blocks.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Link: https://lore.kernel.org/r/20230331123621.16167-9-Garmin.Chang@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-31 11:51:21 -07:00
87d06fa9d2
clk: mediatek: Add MT8188 ccusys clock support
...
Add MT8188 ccusys clock controller which provides clock gate
control in Camera Computing Unit.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Link: https://lore.kernel.org/r/20230331123621.16167-8-Garmin.Chang@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-31 11:51:21 -07:00
9b42835684
clk: mediatek: Add MT8188 camsys clock support
...
Add MT8188 camsys clock controllers which provide clock gate
control for camera IP blocks.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Link: https://lore.kernel.org/r/20230331123621.16167-7-Garmin.Chang@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-31 11:51:21 -07:00
fce4c7a228
clk: mediatek: Add MT8188 infrastructure clock support
...
Add MT8188 infrastructure clock controller which provides
clock gate control for basic IP like pwm, uart, spi and so on.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Link: https://lore.kernel.org/r/20230331123621.16167-6-Garmin.Chang@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-31 11:51:21 -07:00
643c06dc53
clk: mediatek: Add MT8188 peripheral clock support
...
Add MT8188 peripheral clock controller which provides clock
gate control for ethernet/flashif/pcie/ssusb.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Link: https://lore.kernel.org/r/20230331123621.16167-5-Garmin.Chang@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-31 11:51:20 -07:00
6c0d1dc233
clk: mediatek: Add MT8188 topckgen clock support
...
Add MT8188 topckgen clock controller which provides muxes, dividers
to handle variety clock selection in other IP blocks.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Link: https://lore.kernel.org/r/20230331123621.16167-4-Garmin.Chang@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-31 11:51:20 -07:00
28b2bc99fa
clk: mediatek: Add MT8188 apmixedsys clock support
...
Add MT8188 apmixedsys clock controller which provides Plls
generated from SoC 26m and ssusb clock gate control.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Link: https://lore.kernel.org/r/20230331123621.16167-3-Garmin.Chang@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-31 11:51:20 -07:00
aafcf16c9e
clk: mediatek: mt8135: Move apmixedsys to its own file
...
In preparation for migrating mt8135 clocks to the common simple
probe mechanism, move the apmixedsys clocks to a different file.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Link: https://lore.kernel.org/r/20230306140543.1813621-51-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-13 11:50:18 -07:00
124294ff46
clk: mediatek: mt8192: Move apmixedsys clock driver to its own file
...
This is the last man standing in clk-mt8192.c that won't allow us to
use the module_platform_driver() macro, and for *no* good reason.
Move it to clk-mt8192-apmixedsys.c and while at it, also add a
.remove() callback for it.
Also, since the need for "clk-mt8192-simple" and "clk-mt8192" was
just due to them being in the same file and probing different clocks,
and since now there's just one platform_driver struct per file, it
seemed natural to rename the `-simple` variant to just "clk-mt8192".
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Tested-by: Miles Chen <miles.chen@mediatek.com >
Tested-by: Chen-Yu Tsai <wenst@chromium.org >
Link: https://lore.kernel.org/r/20230306140543.1813621-48-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-13 11:50:17 -07:00
5baf38e06a
clk: mediatek: Split configuration options for MT8186 clock drivers
...
When building clock drivers for MT8186, some may want to build in only
some of them to, for example, get CPUFreq up faster, and some may want
to leave out some clock drivers entirely as a machine may not need the
Warp Engine or the camera ISP (hence, their clock drivers).
Split the various clock drivers in their own configuration options,
keeping MT8186 configuration options consistent with other MediaTek
SoCs.
While at it, also allow building the remaining clock drivers as modules
by switching COMMON_CLK_MT8186 to tristate.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Link: https://lore.kernel.org/r/20230306140543.1813621-47-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-13 11:50:17 -07:00
0f471d31e5
clk: mediatek: Split MT8195 clock drivers and allow module build
...
MT8195 clock drivers were encapsulated in one single (and big) Kconfig
option: there's no reason to do that, as it is totally unnecessary to
build in all or none of them.
Split them out: keep boot-critical clocks as bool and allow choosing
non critical clocks as tristate.
As a note, the dependencies of VDEC/VENCSYS and CAM/IMG/IPE/WPESYS
are not for build-time but rather for runtime, as clocks registered
by those have runtime dependencies on either or both VPP and IMGSYS.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Tested-by: Chen-Yu Tsai <wenst@chromium.org >
Link: https://lore.kernel.org/r/20230306140543.1813621-40-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-13 11:50:17 -07:00
f419069ad8
clk: mediatek: mt8516: Move apmixedsys clock driver to its own file
...
In preparation for migrating mt8516 clocks to the common simple
probe mechanism, convert the apmixedsys to be a separated
platform driver and move it to clk-mt8516-apmixedsys.c.
While at it, also fix some indentation issues.
During the conversion, error handling was added to the apmixedsys
probe function.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Link: https://lore.kernel.org/r/20230306140543.1813621-29-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-13 11:50:15 -07:00
838b86331c
clk: mediatek: mt7622: Move infracfg to clk-mt7622-infracfg.c
...
The infracfg driver cannot be converted to clk_mtk_simple_probe() as
it registers cpumuxes, which is not supported on the common probing
mechanism: for this reason, move it to its own file.
While at it, also convert it to be a platform driver instead; to do
so, also add a .remove() callback for this driver.
During the conversion, error handling was added to the infracfg
probe function.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Link: https://lore.kernel.org/r/20230306140543.1813621-27-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-13 11:50:15 -07:00
9aed98adf6
clk: mediatek: mt7622: Move apmixedsys clock driver to its own file
...
In preparation for migrating mt7622 clocks to the common simple
probe mechanism, move apmixedsys clocks to a different file.
While at it, use the builtin_platform_driver() macro for it.
During the conversion, error handling was added to the apmixedsys
probe function.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Link: https://lore.kernel.org/r/20230306140543.1813621-25-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-13 11:50:15 -07:00
127fadf7a4
clk: mediatek: mt8183: Move apmixedsys clock driver to its own file
...
In preparation for migrating all other mt8183 clocks to the common
mtk_clk_simple_probe(), move apmixedsys clocks to a different file.
While at it, use the builtin_platform_driver() macro for it and fix
some indentation issues in the PLLs table.
During the conversion, error handling was added to the apmixedsys
probe function.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Tested-by: Chen-Yu Tsai <wenst@chromium.org >
Link: https://lore.kernel.org/r/20230306140543.1813621-20-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-13 11:50:14 -07:00
b27284336a
clk: mediatek: mt8167: Move apmixedsys as platform_driver in new file
...
In preparation for migrating all other MT8167 clocks to the common
mtk_clk_simple_probe(), move apmixedsys clocks to a different file.
While at it, also migrate away from the legacy CLK_OF_DECLARE and
convert this clock driver to be a platform_driver instead.
During the conversion, error handling was added to the apmixedsys
probe function.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Link: https://lore.kernel.org/r/20230306140543.1813621-17-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-13 11:50:14 -07:00
ab44c1a70e
clk: mediatek: mt8365: Move apmixedsys clock driver to its own file
...
In preparation for migrating all other mt8365 clocks to the common
mtk_clk_simple_probe(), move apmixedsys clocks to a different file.
While at it, use the builtin_platform_driver() macro for it.
During the conversion, error handling was added to the apmixedsys
probe function.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Link: https://lore.kernel.org/r/20230306140543.1813621-12-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-13 11:50:14 -07:00
ae567c3481
clk: mediatek: mt2712: Move apmixedsys clock driver to its own file
...
The only clock driver that does not support mtk_clk_simple_probe() is
apmixedsys: in preparation for enabling module build of non-critical
mt2712 clocks, move this to its own file.
While at it, also fix some indentation issues in the PLLs table.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org >
Link: https://lore.kernel.org/r/20230306140543.1813621-9-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-03-13 11:50:13 -07:00
813c3b53b5
clk: mediatek: add MT7981 clock support
...
Add MT7981 clock support, include topckgen, apmixedsys, infracfg and
ethernet subsystem clocks.
The drivers are based on clk-mt7981.c which can be found in MediaTek's
SDK sources. To be fit for upstream inclusion the driver has been split
into clock domains and the infracfg part has been significantly
de-bloated by removing all the 1:1 factors (aliases).
Signed-off-by: Jianhui Zhao <zhaojh329@gmail.com >
Signed-off-by: Daniel Golle <daniel@makrotopia.org >
Link: https://lore.kernel.org/r/8136eb5b2049177bc2f6d3e0f2aefecc342d626f.1674703830.git.daniel@makrotopia.org
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
[sboyd@kernel.org: Add module license]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-01-30 16:46:06 -08:00
4c02c9af3c
clk: mediatek: mt8173: Break down clock drivers and allow module build
...
Split the giant clock driver for MT8173 into smaller drivers and
make it possible to build the non boot critical clock controller
drivers as modules by adding remove functions and both module
description and license where needed.
While at it, also change a mtk_register_reset_controller() call
to mtk_register_reset_controller_with_dev() in mt8173-infracfg.
Some spare code style cleanups were also performed.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Link: https://lore.kernel.org/r/20230120092053.182923-11-angelogioacchino.delregno@collabora.com
Tested-by: Mingming Su <mingming.su@mediatek.com >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2023-01-30 16:45:22 -08:00
d7964de8a8
clk: mediatek: Add new clock driver to handle FHCTL hardware
...
To implement frequency hopping and spread spectrum clocking
function, we introduce new clock type and APIs to handle
FHCTL hardware.
Co-developed-by: Edward-JW Yang <edward-jw.yang@mediatek.com >
Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.com >
Signed-off-by: Johnson Wang <johnson.wang@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Link: https://lore.kernel.org/r/20221121122957.21611-4-johnson.wang@mediatek.com
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org >
2022-11-29 14:43:07 +08:00
d46adccb79
clk: mediatek: add driver for MT8365 SoC
...
Add clock drivers for MT8365 SoC.
Signed-off-by: Fabien Parent <fparent@baylibre.com >
Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com >
Link: https://lore.kernel.org/r/20220822152652.3499972-5-msp@baylibre.com
Reported-by: kernel test robot <lkp@intel.com >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2022-09-30 15:08:16 -07:00
0d363282bb
clk: mediatek: Add MediaTek Helio X10 MT6795 clock drivers
...
Add the clock drivers for the entire clock tree of MediaTek Helio X10
MT6795, including system clocks (apmixedsys, infracfg, pericfg, topckgen)
and multimedia clocks (mmsys, mfg, vdecsys, vencsys).
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com >
Reviewed-by: Miles Chen <miles.chen@mediatek.com >
Link: https://lore.kernel.org/r/20220921091455.41327-9-angelogioacchino.delregno@collabora.com
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org >
2022-09-26 11:13:09 +08:00
a677bdf8b6
clk: mediatek: Add MT8186 ipesys clock support
...
Add MT8186 ipesys clock controller which provides clock gate
control for Image Process Engine.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Miles Chen <miles.chen@mediatek.com >
Link: https://lore.kernel.org/r/20220409132251.31725-16-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2022-04-25 16:59:41 -07:00
8c3adc5d2e
clk: mediatek: Add MT8186 mdpsys clock support
...
Add MT8186 mdpsys clock controller which provides clock gate
control in Multimedia Data Path.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Miles Chen <miles.chen@mediatek.com >
Link: https://lore.kernel.org/r/20220409132251.31725-15-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2022-04-25 16:59:40 -07:00
6f2e120824
clk: mediatek: Add MT8186 camsys clock support
...
Add MT8186 camsys clock controllers which provide clock gate
control for camera IP blocks.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Miles Chen <miles.chen@mediatek.com >
Link: https://lore.kernel.org/r/20220409132251.31725-14-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2022-04-25 16:59:40 -07:00
fc21950283
clk: mediatek: Add MT8186 vencsys clock support
...
Add MT8186 vencsys clock controller which provide clock gate
control for video encoder.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Miles Chen <miles.chen@mediatek.com >
Link: https://lore.kernel.org/r/20220409132251.31725-13-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2022-04-25 16:59:40 -07:00
7e23620dff
clk: mediatek: Add MT8186 vdecsys clock support
...
Add MT8186 vdec clock controller which provide clock gate
control for video decoder.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Miles Chen <miles.chen@mediatek.com >
Link: https://lore.kernel.org/r/20220409132251.31725-12-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2022-04-25 16:59:40 -07:00
a6c0c9b8fc
clk: mediatek: Add MT8186 imgsys clock support
...
Add MT8186 imgsys clock controllers which provide clock gate
control for image IP blocks.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Miles Chen <miles.chen@mediatek.com >
Link: https://lore.kernel.org/r/20220409132251.31725-11-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2022-04-25 16:59:40 -07:00
b6da76d6eb
clk: mediatek: Add MT8186 wpesys clock support
...
Add MT8186 wpesys clock controllers which provide clock gate
control in Wrapping Engine.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Miles Chen <miles.chen@mediatek.com >
Link: https://lore.kernel.org/r/20220409132251.31725-10-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2022-04-25 16:59:40 -07:00
c8c36b996f
clk: mediatek: Add MT8186 mmsys clock support
...
Add MT8186 mmsys clock controller which provides clock gate
control in video system. This is integrated with mtk-mmsys
driver which will populate device by platform_device_register_data
to start mmsys clock driver.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Miles Chen <miles.chen@mediatek.com >
Link: https://lore.kernel.org/r/20220409132251.31725-9-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2022-04-25 16:59:40 -07:00
e4a424461c
clk: mediatek: Add MT8186 mfgsys clock support
...
Add MT8186 mfg clock controller which provides clock gate
control for GPU.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Miles Chen <miles.chen@mediatek.com >
Link: https://lore.kernel.org/r/20220409132251.31725-8-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2022-04-25 16:59:39 -07:00
66cd0b4b0c
clk: mediatek: Add MT8186 imp i2c wrapper clock support
...
Add MT8186 imp i2c wrapper clock controllers which provide clock gate
control in i2c IP blocks.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Miles Chen <miles.chen@mediatek.com >
Link: https://lore.kernel.org/r/20220409132251.31725-7-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2022-04-25 16:59:39 -07:00
97f0cc59e5
clk: mediatek: Add MT8186 apmixedsys clock support
...
Add MT8186 apmixedsys clock controller which provides Plls
generated from SoC.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Miles Chen <miles.chen@mediatek.com >
Link: https://lore.kernel.org/r/20220409132251.31725-6-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2022-04-25 16:59:39 -07:00
4d6534ec55
clk: mediatek: Add MT8186 infrastructure clock support
...
Add MT8186 infrastructure clock controller which provides
clock gate control for basic IP like pwm, uart, spi and so on.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Miles Chen <miles.chen@mediatek.com >
Link: https://lore.kernel.org/r/20220409132251.31725-5-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2022-04-25 16:59:39 -07:00
c19df9619e
clk: mediatek: Add MT8186 topckgen clock support
...
Add MT8186 topckgen clock controller which provides muxes, dividers
to handle variety clock selection in other IP blocks.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Miles Chen <miles.chen@mediatek.com >
Link: https://lore.kernel.org/r/20220409132251.31725-4-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2022-04-25 16:59:39 -07:00
1f2967a17c
clk: mediatek: Add MT8186 mcusys clock support
...
Add MT8186 mcusys clock controller which provides muxes
to select the clock source of APMCU.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Reviewed-by: Miles Chen <miles.chen@mediatek.com >
Link: https://lore.kernel.org/r/20220409132251.31725-3-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2022-04-25 16:59:39 -07:00
ec97d23c8e
clk: mediatek: add mt7986 clock support
...
Add MT7986 clock support, include topckgen, apmixedsys,
infracfg, and ethernet subsystem clocks.
Signed-off-by: Sam Shih <sam.shih@mediatek.com >
Link: https://lore.kernel.org/r/20211217121148.6753-4-sam.shih@mediatek.com
Reviewed-by: Ryder Lee <ryder.lee@kernel.org >
[sboyd@kernel.org: Fix typos in Kconfig, there are more existing typos
from where they were copied from of but whatever]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-06 18:37:55 -08:00
Sam Shih