KONKA TV have the problem that hdmi hpd pin leakage leads to hpd
interrupt and trigger incorrectly. When the hdmi cable is not securely
connected, the hdmitx ddc pin will leak electricity back to hdmitx
through the TV's hpd pin and pull up hpd pin voltage to 1.8v.
Because rk3528 hdmi hpd interrupt trigger voltage is 1.5v,
hpd irq will be triggered by mistake, resulting in
edid reading error. Therefore, hdmi ddc io needs to be pull down
before the hpd pin is actually contacted and stabilized.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Id5f859e1de0dde751cf1d522a8d7647558f0b7f8
For compatibility with gki, dw-hdmi use callback
function instead of direct call dw-hdmi-cec wake up function.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I06fb65eadead5e3395bbd69a4dd465c95c684494
When the frequency before and after color switching is the
same, the resolution switching process is not performed.
Instead, go through the following process:
connector atomic check--->set avmute--->config hdmi controller
-->config vop-->connector atomic commit-->clear avmute.
This way the HDMI output will not be interrupted, the black
screen time will be shorter, and the user experience will be
better.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: If2d0d9d21c2c343cd8e2b5135b214bc1a6f6706c
Support system wake up if hpd pin gpio irq occur when hdmi plug in.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I5a3896e8b1b86bccbda6681db26ab4285e3eec72
This patch wrap register access by lock which guarantee the clk
enabled first. and remove the unused CLK status from CMN.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Iba058ad08c71de0b118913216baec1886d8f3819
Adds recommended N and Expected CTS Values for FRL Mode
which defined in chapter 9.2.2 of HDMI Specification 2.1.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I1a21a111a65beeb024e5740c8bd231f9f534c1b5
1.Support phy pll clk enable/disable is separated from
phy signal output.
2.Add avmute set/clear in resolution switching process.
3.To comply with the timing requirements of the HDMI protocol,
HDMI must be enabled in tmds mode according to the following process:
disable FRL -> enable/disable scramble —> power up phy
4.Optimize flt process
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I5f48b3292b434b26ab28a4e7238a87c8d64d5a33
* LPCM: BPCUV insertion by hw
* NLPCM/HBR: BPCUV insertion from stream
when BPCUV is from stream, we should not enable hw channel
status override which will replace CS with the hw one.
This fixes DD+ bitstream.
when BPCUV generated from HW, PBIT_FORCE_EN should be set
for Parity bit calculated internally.
This fixes no sound on some display devices.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I3aa0390d9dd7d217853394c74576749c36b84720
RK3588 dclk is required to access hdmi grf register.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Ia7a2f2ab18d8734696b9493340f206aad0168d4c
Support hdmi frl mode and dsc function.
Support max 8K-60Hz RGB 10bit output.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Ibc2d48e2b25bc94e4be7ffa9703c400436bdee36
This reverts commit 6b7fb9a6c9.
The audio regbank of hdmi-qp is drived by audio interface clk, and had
fixed by commits as follows:
[1] 3a7f369b5c ("arm64: dts: rockchip: rk3588: Add aud clk for hdmi nodes")
[2] e108ff9f6f ("drm/rockchip: dw_hdmi: Handle aud clk for hdmi qp")
OTOH, to make android hal happy, we still allow to access hdmi audio even
hdmi is plugged out.
"hdmi-audio-codec: ASoC: error at snd_soc_dai_startup on i2s-hifi: -19"
Android/Linux should reopen hdmi sound card depends on HPD plug event
to bring back to normal state.
Change-Id: I654fe18a04b750f57c8bd52ef4948a476bc1fa50
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
This patch adds support for Analogix eDP TX IP used on RK3588 SoC.
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I362489fb294673512b6de1913aa2e0b855a98926
Add property to transfer next hdr sink data to userspace.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I926ec6553bdb0b1730a7ca578f46f36926860ebd
To support the rk3588 dsc function, add get edid dsc
info interface.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I33cc4b60183484e7cd15b519cec4c32d7be53deb
To be compatible with GKI, dw-hdmi driver can't call interfaces in
rockchip-drm directly. In order for dp to be usable, get yuv422
format interface should define in rockchip-drm. So hdmi call
get yuv422 format interface in dw_hdmi-rockchip.c.
Fixes: dbd228a254 ("drm/bridge: synopsys: dw-hdmi: Get edid yuv422 info independently")
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Icc879ff4420357a6becba84371b9e3317583960b
When set property hdmi_quant_range, quant range was changed immediately.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Ib8c14404cc3dde645012399b6155d047b4e9609a
For compatibility with GKI, HDR_PANEL_METADATA can't be a global
property. So change HDR_PANEL_METADATA to Rockchip private property.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I7926683a5dc6274e6cab2151e476344fa897b66c
For compatibility with GKI, connector atomic_begin/atomic_flush should
be removed. If hdmi color format has changed, set flag mode_changed
true and start a modeset to config hdmi.
We check whether color format has changed in
dw_hdmi_connector_atomic_check(), but color format variable update in
dw_hdmi_rockchip_encoder_atomic_check(), It runs after
dw_hdmi_connector_atomic_check(). That will lead to misjudgments when
determining whether color format has changed.
To solve this problem, we introduce get_color_changed(). When color
properties are set and color format is changed, get_color_changed()
return true.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Id1fbe80171856f91efa5ae40a0e0608a92ebcbf7
1.Filling the HDMI AVI infoframe quantization range information.
2.If output is limited enable color space conversion to convert.
Change-Id: I75f666424f00f3f6ec695047f7851824e89cd1a5
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Algea Cao