diff --git a/drivers/mtd/spi-nor/everspin.c b/drivers/mtd/spi-nor/everspin.c
index 284c88183c63..3b8bb66a2070 100644
--- a/drivers/mtd/spi-nor/everspin.c
+++ b/drivers/mtd/spi-nor/everspin.c
@@ -104,7 +104,12 @@ static void everspin_mram_default_init(struct spi_nor *nor)
 
 	/* 2. Switch to Octal Mode using the correct VCR0 address and value */
 	dev_info(nor->dev, "Setting VCR0 to Octal STR (0xB7) at address 0x000000...\n");
-	
+
+	/* 1. Set the Address Width to 3 Bytes (mandatory for 1MB MRAM) */
+	nor->params->addr_nbytes = 3;
+	nor->addr_nbytes = 3; 
+
+#if 0
 	/* IMPORTANT: Use 0xB7 for Octal with Data Strobe */
 	ret = everspin_mram_write_reg(nor, SPINOR_REG_EVERSPIN_VCR0, EVERSPIN_OCTAL_STR_B7);
 	
@@ -119,6 +124,11 @@ static void everspin_mram_default_init(struct spi_nor *nor)
 		spi_nor_read_any_reg(nor, &op, nor->reg_proto);
 		dev_info(nor->dev, "SR1 after VCR0 write: 0x%02x\n", nor->bouncebuf[0]);
 	}
+#endif
+
+	/* 3. Ensure NO 4-byte mode is activated */
+	nor->flags &= ~SNOR_F_4B_OPCODES;
+	nor->params->set_4byte_addr_mode = NULL; 
 
 	/* 3. Synchronize kernel parameters */
 	nor->cmd_ext_type = SPI_NOR_EXT_REPEAT;
@@ -128,9 +138,14 @@ static void everspin_mram_default_init(struct spi_nor *nor)
 	nor->flags &= ~SNOR_F_HAS_16BIT_SR;
 	nor->params->quad_enable = NULL;
 
+	nor->params->addr_nbytes = 3;
+	// Manche Cadence-Implementationen brauchen ein explizites Byte-Alignment
+	nor->program_opcode = SPINOR_OP_PP; 
+
 	dev_info(nor->dev, "Standard parameters for OSPI controller set.\n");
 }
 
+#if 0
 static int everspin_mram_late_init(struct spi_nor *nor)
 {
 	dev_info(nor->dev, "Configuring Octal opcodes for Read/Write...\n");
@@ -151,6 +166,30 @@ static int everspin_mram_late_init(struct spi_nor *nor)
 	dev_info(nor->dev, "Everspin MRAM successfully initialized in Octal mode.\n");
 	return 0;
 }
+#endif
+
+static int everspin_mram_late_init(struct spi_nor *nor)
+{
+	dev_info(nor->dev, "Configuring Hybrid Mode: Octal Read / Single Write...\n");
+
+	/* 1. Fast Read Settings: Octal STR (1-8-8) */
+	nor->params->hwcaps.mask |= SNOR_HWCAPS_READ_1_8_8;
+	spi_nor_set_read_settings(&nor->params->reads[SNOR_CMD_READ_1_8_8],
+				  0, 8, SPINOR_OP_READ_1_8_8, SNOR_PROTO_1_8_8);
+
+	/* 2. Stable Write Settings: Force Single-SPI (Standard Page Program) */
+	/* We disable Octal-Write and enable standard PP */
+	nor->params->hwcaps.mask &= ~SNOR_HWCAPS_PP_1_8_8;
+	nor->params->hwcaps.mask |= SNOR_HWCAPS_PP;
+	
+	/* Standard Page Program uses Opcode 02h and Protocol 1-1-1 */
+	spi_nor_set_pp_settings(&nor->params->page_programs[SNOR_CMD_PP],
+				SPINOR_OP_PP, 
+				SNOR_PROTO_1_1_1);
+
+	dev_info(nor->dev, "Hybrid Mode initialized: Read 8-8-8, Write 1-1-1.\n");
+	return 0;
+}
 
 static const struct spi_nor_fixups everspin_mram_fixups = {
 	.default_init = everspin_mram_default_init,