Merge branches 'acerhdf', 'acpi-pci-bind', 'bjorn-pci-root', 'bugzilla-12904', 'bugzilla-13121', 'bugzilla-13396', 'bugzilla-13533', 'bugzilla-13612', 'c3_lock', 'hid-cleanups', 'misc-2.6.31', 'pdc-leak-fix', 'pnpacpi', 'power_nocheck', 'thinkpad_acpi', 'video' and 'wmi' into release
This commit is contained in:
@@ -44,11 +44,7 @@
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static int __initdata acpi_force = 0;
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u32 acpi_rsdt_forced;
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#ifdef CONFIG_ACPI
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int acpi_disabled = 0;
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#else
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int acpi_disabled = 1;
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#endif
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int acpi_disabled;
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EXPORT_SYMBOL(acpi_disabled);
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#ifdef CONFIG_X86_64
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@@ -122,72 +118,6 @@ void __init __acpi_unmap_table(char *map, unsigned long size)
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early_iounmap(map, size);
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}
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#ifdef CONFIG_PCI_MMCONFIG
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static int acpi_mcfg_64bit_base_addr __initdata = FALSE;
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/* The physical address of the MMCONFIG aperture. Set from ACPI tables. */
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struct acpi_mcfg_allocation *pci_mmcfg_config;
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int pci_mmcfg_config_num;
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static int __init acpi_mcfg_oem_check(struct acpi_table_mcfg *mcfg)
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{
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if (!strcmp(mcfg->header.oem_id, "SGI"))
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acpi_mcfg_64bit_base_addr = TRUE;
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return 0;
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}
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int __init acpi_parse_mcfg(struct acpi_table_header *header)
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{
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struct acpi_table_mcfg *mcfg;
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unsigned long i;
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int config_size;
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if (!header)
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return -EINVAL;
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mcfg = (struct acpi_table_mcfg *)header;
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/* how many config structures do we have */
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pci_mmcfg_config_num = 0;
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i = header->length - sizeof(struct acpi_table_mcfg);
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while (i >= sizeof(struct acpi_mcfg_allocation)) {
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++pci_mmcfg_config_num;
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i -= sizeof(struct acpi_mcfg_allocation);
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};
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if (pci_mmcfg_config_num == 0) {
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printk(KERN_ERR PREFIX "MMCONFIG has no entries\n");
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return -ENODEV;
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}
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config_size = pci_mmcfg_config_num * sizeof(*pci_mmcfg_config);
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pci_mmcfg_config = kmalloc(config_size, GFP_KERNEL);
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if (!pci_mmcfg_config) {
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printk(KERN_WARNING PREFIX
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"No memory for MCFG config tables\n");
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return -ENOMEM;
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}
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memcpy(pci_mmcfg_config, &mcfg[1], config_size);
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acpi_mcfg_oem_check(mcfg);
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for (i = 0; i < pci_mmcfg_config_num; ++i) {
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if ((pci_mmcfg_config[i].address > 0xFFFFFFFF) &&
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!acpi_mcfg_64bit_base_addr) {
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printk(KERN_ERR PREFIX
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"MMCONFIG not in low 4GB of memory\n");
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kfree(pci_mmcfg_config);
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pci_mmcfg_config_num = 0;
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return -ENODEV;
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}
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}
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return 0;
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}
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#endif /* CONFIG_PCI_MMCONFIG */
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#ifdef CONFIG_X86_LOCAL_APIC
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static int __init acpi_parse_madt(struct acpi_table_header *table)
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{
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@@ -1517,14 +1447,6 @@ static struct dmi_system_id __initdata acpi_dmi_table[] = {
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DMI_MATCH(DMI_PRODUCT_NAME, "Workstation W8000"),
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},
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},
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{
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.callback = force_acpi_ht,
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.ident = "ASUS P4B266",
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.matches = {
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DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
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DMI_MATCH(DMI_BOARD_NAME, "P4B266"),
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},
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},
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{
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.callback = force_acpi_ht,
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.ident = "ASUS P2B-DS",
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@@ -34,12 +34,22 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
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flags->bm_check = 1;
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else if (c->x86_vendor == X86_VENDOR_INTEL) {
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/*
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* Today all CPUs that support C3 share cache.
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* TBD: This needs to look at cache shared map, once
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* multi-core detection patch makes to the base.
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* Today all MP CPUs that support C3 share cache.
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* And caches should not be flushed by software while
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* entering C3 type state.
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*/
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flags->bm_check = 1;
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}
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/*
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* On all recent Intel platforms, ARB_DISABLE is a nop.
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* So, set bm_control to zero to indicate that ARB_DISABLE
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* is not required while entering C3 type state on
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* P4, Core and beyond CPUs
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*/
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if (c->x86_vendor == X86_VENDOR_INTEL &&
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(c->x86 > 0x6 || (c->x86 == 6 && c->x86_model >= 14)))
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flags->bm_control = 0;
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}
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EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
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@@ -72,6 +72,7 @@ static void init_intel_pdc(struct acpi_processor *pr, struct cpuinfo_x86 *c)
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return;
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}
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/* Initialize _PDC data based on the CPU vendor */
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void arch_acpi_processor_init_pdc(struct acpi_processor *pr)
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{
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@@ -85,3 +86,15 @@ void arch_acpi_processor_init_pdc(struct acpi_processor *pr)
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}
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EXPORT_SYMBOL(arch_acpi_processor_init_pdc);
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void arch_acpi_processor_cleanup_pdc(struct acpi_processor *pr)
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{
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if (pr->pdc) {
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kfree(pr->pdc->pointer->buffer.pointer);
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kfree(pr->pdc->pointer);
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kfree(pr->pdc);
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pr->pdc = NULL;
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}
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}
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EXPORT_SYMBOL(arch_acpi_processor_cleanup_pdc);
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