Merge branches 'clk-bindings', 'clk-cleanup', 'clk-pwm', 'clk-hw-device', 'clk-xilinx' and 'clk-adi' into clk-next
- Support atomic PWMs in the PWM clk driver - clk_hw_get_dev() and clk_hw_get_of_node() helpers * clk-bindings: (30 commits) dt-bindings: clock: convert lpc1850-cgu.txt to yaml format dt-bindings: clock: Convert qca,ath79-pll to DT schema dt-bindings: clock: Convert nuvoton,npcm750-clk to DT schema dt-bindings: clock: Convert moxa,moxart-clock to DT schema dt-bindings: clock: Convert microchip,pic32mzda-clk to DT schema dt-bindings: clock: Convert maxim,max9485 to DT schema dt-bindings: clock: Convert qcom,krait-cc to DT schema dt-bindings: clock: qcom: Remove double colon from description dt-bindings: clock: convert lpc1850-ccu.txt to yaml format dt-bindings: clock: Convert alphascale,asm9260-clock-controller to DT schema dt-bindings: clock: Convert marvell,armada-370-corediv-clock to DT schema dt-bindings: clock: Convert marvell,armada-3700-periph-clock to DT schema dt-bindings: clock: Convert marvell,mvebu-core-clock to DT schema dt-bindings: clock: Convert marvell,berlin2-clk to DT schema dt-bindings: clock: Convert marvell,dove-divider-clock to DT schema dt-bindings: clock: Convert marvell,armada-3700-tbg-clock to DT schema dt-bindings: clock: Convert marvell-armada-370-gating-clock to DT schema dt-bindings: clock: Convert marvell,armada-xp-cpu-clock to DT schema dt-bindings: clock: Convert TI-NSPIRE clocks to DT schema dt-bindings: clock: Convert lsi,axm5516-clks to DT schema ... * clk-cleanup: (29 commits) clk: clocking-wizard: Fix the round rate handling for versal clk: Fix typos clk: tegra: periph: Make tegra_clk_periph_ops static clk: tegra: periph: Fix error handling and resolve unsigned compare warning clk: imx: scu: convert from round_rate() to determine_rate() clk: imx: pllv4: convert from round_rate() to determine_rate() clk: imx: pllv3: convert from round_rate() to determine_rate() clk: imx: pllv2: convert from round_rate() to determine_rate() clk: imx: pll14xx: convert from round_rate() to determine_rate() clk: imx: pfd: convert from round_rate() to determine_rate() clk: imx: frac-pll: convert from round_rate() to determine_rate() clk: imx: fracn-gppll: convert from round_rate() to determine_rate() clk: imx: fixup-div: convert from round_rate() to determine_rate() clk: imx: cpu: convert from round_rate() to determine_rate() clk: imx: busy: convert from round_rate() to determine_rate() clk: imx: composite-93: remove round_rate() in favor of determine_rate() clk: imx: composite-8m: remove round_rate() in favor of determine_rate() clk: bcm: bcm2835: convert from round_rate() to determine_rate() MAINTAINERS: Include clk.py under COMMON CLK FRAMEWORK entry clk: ti: Simplify ti_find_clock_provider() ... * clk-pwm: clk: pwm: Make use of non-sleeping PWMs clk: pwm: Don't reconfigure running PWM at probe time clk: pwm: Convert to use pwm_apply_might_sleep() clk: pwm: Let .get_duty_cycle() return the real duty cycle * clk-hw-device: clk: tests: add clk_hw_get_dev() and clk_hw_get_of_node() tests clk: tests: Make clk_register_clk_parent_data_device_driver() common clk: add a clk_hw helpers to get the clock device or device_node * clk-xilinx: clk: xilinx: vcu: Update vcu init/reset sequence clk: xilinx: vcu: unregister pll_post only if registered correctly * clk-adi: clk: clk-axi-clkgen: fix coding style issues clk: clk-axi-clkgen move to min/max() clk: clk-axi-clkgen: detect axi_clkgen_limits at runtime include: adi-axi-common: add new helper macros include: linux: move adi-axi-common.h out of fpga clk: clk-axi-clkgen: make sure to include mod_devicetable.h clk: clk-axi-clkgen: fix fpfd_max frequency for zynq
This commit is contained in:
+19
-23
@@ -30,39 +30,43 @@ use crate::ffi::c_ulong;
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pub struct Hertz(pub c_ulong);
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impl Hertz {
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const KHZ_TO_HZ: c_ulong = 1_000;
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const MHZ_TO_HZ: c_ulong = 1_000_000;
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const GHZ_TO_HZ: c_ulong = 1_000_000_000;
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/// Create a new instance from kilohertz (kHz)
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pub fn from_khz(khz: c_ulong) -> Self {
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Self(khz * 1_000)
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pub const fn from_khz(khz: c_ulong) -> Self {
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Self(khz * Self::KHZ_TO_HZ)
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}
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/// Create a new instance from megahertz (MHz)
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pub fn from_mhz(mhz: c_ulong) -> Self {
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Self(mhz * 1_000_000)
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pub const fn from_mhz(mhz: c_ulong) -> Self {
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Self(mhz * Self::MHZ_TO_HZ)
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}
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/// Create a new instance from gigahertz (GHz)
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pub fn from_ghz(ghz: c_ulong) -> Self {
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Self(ghz * 1_000_000_000)
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pub const fn from_ghz(ghz: c_ulong) -> Self {
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Self(ghz * Self::GHZ_TO_HZ)
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}
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/// Get the frequency in hertz
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pub fn as_hz(&self) -> c_ulong {
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pub const fn as_hz(&self) -> c_ulong {
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self.0
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}
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/// Get the frequency in kilohertz
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pub fn as_khz(&self) -> c_ulong {
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self.0 / 1_000
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pub const fn as_khz(&self) -> c_ulong {
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self.0 / Self::KHZ_TO_HZ
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}
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/// Get the frequency in megahertz
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pub fn as_mhz(&self) -> c_ulong {
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self.0 / 1_000_000
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pub const fn as_mhz(&self) -> c_ulong {
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self.0 / Self::MHZ_TO_HZ
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}
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/// Get the frequency in gigahertz
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pub fn as_ghz(&self) -> c_ulong {
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self.0 / 1_000_000_000
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pub const fn as_ghz(&self) -> c_ulong {
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self.0 / Self::GHZ_TO_HZ
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}
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}
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@@ -132,11 +136,7 @@ mod common_clk {
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///
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/// [`clk_get`]: https://docs.kernel.org/core-api/kernel-api.html#c.clk_get
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pub fn get(dev: &Device, name: Option<&CStr>) -> Result<Self> {
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let con_id = if let Some(name) = name {
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name.as_ptr()
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} else {
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ptr::null()
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};
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let con_id = name.map_or(ptr::null(), |n| n.as_ptr());
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// SAFETY: It is safe to call [`clk_get`] for a valid device pointer.
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//
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@@ -304,11 +304,7 @@ mod common_clk {
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/// [`clk_get_optional`]:
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/// https://docs.kernel.org/core-api/kernel-api.html#c.clk_get_optional
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pub fn get(dev: &Device, name: Option<&CStr>) -> Result<Self> {
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let con_id = if let Some(name) = name {
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name.as_ptr()
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} else {
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ptr::null()
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};
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let con_id = name.map_or(ptr::null(), |n| n.as_ptr());
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// SAFETY: It is safe to call [`clk_get_optional`] for a valid device pointer.
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//
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