From f1c0d82ea3b0f6b069e79744ebffc0ffb71250a2 Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Fri, 15 Dec 2023 10:19:46 +0800 Subject: [PATCH] arm64: dts: rockchip: rk3588-evb: add edp 8lane display board EDP panel M280DCA supports 3840x2160p144 with 8lanes. Signed-off-by: Damon Ding Change-Id: I90cb80d6534c1c56610a55b8e6e90f5c9a712b5a --- arch/arm64/boot/dts/rockchip/Makefile | 1 + ...rk3588-evb1-lp4-v10-edp-8lanes-M280DCA.dts | 229 ++++++++++++++++++ 2 files changed, 230 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4-v10-edp-8lanes-M280DCA.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 7687ee40c071..5163c441e2c4 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -209,6 +209,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-v1-evb-display-super-frame-dsi0-co dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-v1-evb-display-super-frame-dsi0-command2lvds0-lp4x-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10-dsi-dsc-MV2100UZ1.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10-edp-8lanes-M280DCA.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10-ipc-6x-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10-linux-amp.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4-v10-edp-8lanes-M280DCA.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4-v10-edp-8lanes-M280DCA.dts new file mode 100644 index 000000000000..65afa35b2d48 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4-v10-edp-8lanes-M280DCA.dts @@ -0,0 +1,229 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-evb1-lp4.dtsi" +#include "rk3588-evb1-imx415.dtsi" +#include "rk3588-android.dtsi" + +/ { + model = "Rockchip RK3588 EVB1 LP4 V10 Board + RK3588 EDP 8LANES V10 Ext Board"; + compatible = "rockchip,rk3588-evb1-lp4-v10-edp-8lanes-M280DCA", "rockchip,rk3588"; + + panel-edp { + compatible = "simple-panel"; + backlight = <&backlight>; + power-supply = <&vcc3v3_edp>; + enable-gpios = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>; + prepare-delay-ms = <120>; + enable-delay-ms = <120>; + unprepare-delay-ms = <120>; + disable-delay-ms = <120>; + + display-timings { + native-mode = <&timing_4kp144>; + timing_4kp144: timing0 { + clock-frequency = <1360800000>; + hactive = <3840>; + vactive = <2160>; + hfront-porch = <160>; + hsync-len = <40>; + hback-porch = <160>; + vfront-porch = <40>; + vsync-len = <10>; + vback-porch = <40>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + timing_4kp120: timing1 { + clock-frequency = <1188000000>; + hactive = <3840>; + vactive = <2160>; + hfront-porch = <240>; + hsync-len = <80>; + hback-porch = <240>; + vfront-porch = <40>; + vsync-len = <10>; + vback-porch = <40>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + port { + panel_in_edp: endpoint { + remote-endpoint = <&edp1_out_panel>; + }; + }; + }; + + vcc3v3_edp_bl: vcc3v3-edp-bl { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_edp_bl"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio4 RK_PC0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc3v3_edp: vcc3v3-edp { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_edp"; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc12v_dcin>; + }; +}; + +&bt_sco { + status = "okay"; +}; + +&bt_sound { + status = "okay"; +}; + +&dsi0 { + status = "disabled"; +}; + +&edp0 { + force-hpd; + status = "okay"; +}; + +&edp0_in_vp0 { + status = "okay"; +}; + +&edp0_in_vp1 { + status = "disabled"; +}; + +&edp0_in_vp2 { + status = "disabled"; +}; + +&edp1 { + force-hpd; + status = "okay"; + dual-channel; + + ports { + port@1 { + reg = <1>; + + edp1_out_panel: endpoint { + remote-endpoint = <&panel_in_edp>; + }; + }; + }; +}; + +&edp1_in_vp0 { + status = "okay"; +}; + +&edp1_in_vp1 { + status = "disabled"; +}; + +&edp1_in_vp2 { + status = "disabled"; +}; + +&hdmi0 { + status = "disabled"; +}; + +&hdmi0_in_vp0 { + status = "disabled"; +}; + +&hdmi0_sound { + status = "disabled"; +}; + +&hdmi1 { + status = "disabled"; +}; + +&hdmi1_in_vp1 { + status = "disabled"; +}; + +&hdmi1_sound { + status = "disabled"; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&hdptxphy1 { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "disabled"; +}; + +&hdptxphy_hdmi1 { + status = "disabled"; +}; + +&i2s2_2ch { + status = "okay"; +}; + +&route_dsi0 { + status = "disabled"; +}; + +&route_edp0 { + status = "okay"; + connect = <&vp0_out_edp0>; +}; + +&route_edp1 { + status = "okay"; + connect = <&vp0_out_edp1>; +}; + +&route_hdmi0 { + status = "disabled"; +}; + +&route_hdmi1 { + status = "disabled"; +}; + +&vop { + assigned-clocks = <&cru ACLK_VOP>; + assigned-clock-rates = <800000000>; +}; + +&vp0 { + assigned-clocks = <&cru DCLK_VOP0_SRC>; + assigned-clock-parents = <&cru PLL_V0PLL>; +}; + +&vp2 { + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; +};