Merge tag 'drm-for-v4.11-less-shouty' of git://people.freedesktop.org/~airlied/linux
Pull drm updates from Dave Airlie: "This is the main drm pull request for v4.11. Nothing too major, the tinydrm and mmu-less support should make writing smaller drivers easier for some of the simpler platforms, and there are a bunch of documentation updates. Intel grew displayport MST audio support which is hopefully useful to people, and FBC is on by default for GEN9+ (so people know where to look for regressions). AMDGPU has a lot of fixes that would like new firmware files installed for some GPUs. Other than that it's pretty scattered all over. I may have a follow up pull request as I know BenH has a bunch of AST rework and fixes and I'd like to get those in once they've been tested by AST, and I've got at least one pull request I'm just trying to get the author to fix up. Core: - drm_mm reworked - Connector list locking and iterators - Documentation updates - Format handling rework - MMU-less support for fbdev helpers - drm_crtc_from_index helper - Core CRC API - Remove drm_framebuffer_unregister_private - Debugfs cleanup - EDID/Infoframe fixes - Release callback - Tinydrm support (smaller drivers for simple hw) panel: - Add support for some new simple panels i915: - FBC by default for gen9+ - Shared dpll cleanups and docs - GEN8 powerdomain cleanup - DMC support on GLK - DP MST audio support - HuC loading support - GVT init ordering fixes - GVT IOMMU workaround fix amdgpu/radeon: - Power/clockgating improvements - Preliminary SR-IOV support - TTM buffer priority and eviction fixes - SI DPM quirks removed due to firmware fixes - Powerplay improvements - VCE/UVD powergating fixes - Cleanup SI GFX code to match CI/VI - Support for > 2 displays on 3/5 crtc asics - SI headless fixes nouveau: - Rework securre boot code in prep for GP10x secure boot - Channel recovery improvements - Initial power budget code - MMU rework preperation vmwgfx: - Bunch of fixes and cleanups exynos: - Runtime PM support for MIC driver - Cleanups to use atomic helpers - UHD Support for TM2/TM2E boards - Trigger mode fix for Rinato board etnaviv: - Shader performance fix - Command stream validator fixes - Command buffer suballocator rockchip: - CDN DisplayPort support - IOMMU support for arm64 platform imx-drm: - Fix i.MX5 TV encoder probing - Remove lower fb size limits msm: - Support for HW cursor on MDP5 devices - DSI encoder cleanup - GPU DT bindings cleanup sti: - stih410 cleanups - Create fbdev at binding - HQVDP fixes - Remove stih416 chip functionality - DVI/HDMI mode selection fixes - FPS statistic reporting omapdrm: - IRQ code cleanup dwi-hdmi bridge: - Cleanups and fixes adv-bridge: - Updates for nexus sii8520 bridge: - Add interlace mode support - Rework HDMI and lots of fixes qxl: - probing/teardown cleanups ZTE drm: - HDMI audio via SPDIF interface - Video Layer overlay plane support - Add TV encoder output device atmel-hlcdc: - Rework fbdev creation logic tegra: - OF node fix fsl-dcu: - Minor fixes mali-dp: - Assorted fixes sunxi: - Minor fix" [ This was the "fixed" pull, that still had build warnings due to people not even having build tested the result. I'm not a happy camper I've fixed the things I noticed up in this merge. - Linus ] * tag 'drm-for-v4.11-less-shouty' of git://people.freedesktop.org/~airlied/linux: (1177 commits) lib/Kconfig: make PRIME_NUMBERS not user selectable drm/tinydrm: helpers: Properly fix backlight dependency drm/tinydrm: mipi-dbi: Fix field width specifier warning drm/tinydrm: mipi-dbi: Silence: ‘cmd’ may be used uninitialized drm/sti: fix build warnings in sti_drv.c and sti_vtg.c files drm/amd/powerplay: fix PSI feature on Polars12 drm/amdgpu: refuse to reserve io mem for split VRAM buffers drm/ttm: fix use-after-free races in vm fault handling drm/tinydrm: Add support for Multi-Inno MI0283QT display dt-bindings: Add Multi-Inno MI0283QT binding dt-bindings: display/panel: Add common rotation property of: Add vendor prefix for Multi-Inno drm/tinydrm: Add MIPI DBI support drm/tinydrm: Add helper functions drm: Add DRM support for tiny LCD displays drm/amd/amdgpu: post card if there is real hw resetting performed drm/nouveau/tmr: provide backtrace when a timeout is hit drm/nouveau/pci/g92: Fix rearm drm/nouveau/drm/therm/fan: add a fallback if no fan control is specified in the vbios drm/nouveau/hwmon: expose power_max and power_crit ..
This commit is contained in:
Linus Torvalds
@@ -9,6 +9,7 @@ header-y += i810_drm.h
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header-y += i915_drm.h
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header-y += mga_drm.h
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header-y += nouveau_drm.h
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header-y += omap_drm.h
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header-y += qxl_drm.h
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header-y += r128_drm.h
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header-y += radeon_drm.h
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@@ -528,6 +528,8 @@ struct drm_amdgpu_cs_chunk_data {
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#define AMDGPU_INFO_VBIOS_SIZE 0x1
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/* Subquery id: Query vbios image */
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#define AMDGPU_INFO_VBIOS_IMAGE 0x2
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/* Query UVD handles */
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#define AMDGPU_INFO_NUM_HANDLES 0x1C
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#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
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#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
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@@ -719,6 +721,13 @@ struct drm_amdgpu_info_hw_ip {
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__u32 _pad;
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};
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struct drm_amdgpu_info_num_handles {
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/** Max handles as supported by firmware for UVD */
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__u32 uvd_max_handles;
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/** Handles currently in use for UVD */
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__u32 uvd_used_handles;
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};
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#define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6
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struct drm_amdgpu_info_vce_clock_table_entry {
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@@ -41,10 +41,17 @@ extern "C" {
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/* 8 bpp Red */
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#define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
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/* 16 bpp Red */
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#define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */
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/* 16 bpp RG */
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#define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */
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#define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */
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/* 32 bpp RG */
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#define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */
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#define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */
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/* 8 bpp RGB */
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#define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */
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#define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */
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@@ -154,11 +161,13 @@ extern "C" {
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/* Vendor Ids: */
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#define DRM_FORMAT_MOD_NONE 0
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#define DRM_FORMAT_MOD_VENDOR_NONE 0
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#define DRM_FORMAT_MOD_VENDOR_INTEL 0x01
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#define DRM_FORMAT_MOD_VENDOR_AMD 0x02
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#define DRM_FORMAT_MOD_VENDOR_NV 0x03
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#define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
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#define DRM_FORMAT_MOD_VENDOR_QCOM 0x05
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#define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
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/* add more to the end as needed */
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#define fourcc_mod_code(vendor, val) \
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@@ -172,6 +181,16 @@ extern "C" {
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* authoritative source for all of these.
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*/
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/*
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* Linear Layout
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*
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* Just plain linear layout. Note that this is different from no specifying any
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* modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl),
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* which tells the driver to also take driver-internal information into account
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* and so might actually result in a tiled framebuffer.
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*/
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#define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0)
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/* Intel framebuffer modifiers */
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/*
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@@ -233,6 +252,46 @@ extern "C" {
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*/
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#define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
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/* Vivante framebuffer modifiers */
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/*
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* Vivante 4x4 tiling layout
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*
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* This is a simple tiled layout using tiles of 4x4 pixels in a row-major
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* layout.
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*/
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#define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1)
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/*
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* Vivante 64x64 super-tiling layout
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*
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* This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
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* contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
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* major layout.
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*
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* For more information: see
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* https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling
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*/
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#define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2)
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/*
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* Vivante 4x4 tiling layout for dual-pipe
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*
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* Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
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* different base address. Offsets from the base addresses are therefore halved
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* compared to the non-split tiled layout.
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*/
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#define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3)
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/*
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* Vivante 64x64 super-tiling layout for dual-pipe
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*
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* Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
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* starts at a different base address. Offsets from the base addresses are
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* therefore halved compared to the non-split super-tiled layout.
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*/
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#define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
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#if defined(__cplusplus)
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}
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#endif
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@@ -258,6 +258,7 @@ typedef struct _drm_i915_sarea {
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#define DRM_I915_GEM_USERPTR 0x33
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#define DRM_I915_GEM_CONTEXT_GETPARAM 0x34
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#define DRM_I915_GEM_CONTEXT_SETPARAM 0x35
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#define DRM_I915_PERF_OPEN 0x36
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#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
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#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
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@@ -311,6 +312,7 @@ typedef struct _drm_i915_sarea {
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#define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr)
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#define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param)
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#define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param)
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#define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param)
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/* Allow drivers to submit batchbuffers directly to hardware, relying
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* on the security mechanisms provided by hardware.
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@@ -393,6 +395,7 @@ typedef struct drm_i915_irq_wait {
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* priorities and the driver will attempt to execute batches in priority order.
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*/
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#define I915_PARAM_HAS_SCHEDULER 41
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#define I915_PARAM_HUC_STATUS 42
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typedef struct drm_i915_getparam {
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__s32 param;
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@@ -1224,9 +1227,142 @@ struct drm_i915_gem_context_param {
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#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2
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#define I915_CONTEXT_PARAM_GTT_SIZE 0x3
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#define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4
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#define I915_CONTEXT_PARAM_BANNABLE 0x5
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__u64 value;
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};
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enum drm_i915_oa_format {
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I915_OA_FORMAT_A13 = 1,
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I915_OA_FORMAT_A29,
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I915_OA_FORMAT_A13_B8_C8,
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I915_OA_FORMAT_B4_C8,
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I915_OA_FORMAT_A45_B8_C8,
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I915_OA_FORMAT_B4_C8_A16,
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I915_OA_FORMAT_C4_B8,
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I915_OA_FORMAT_MAX /* non-ABI */
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};
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enum drm_i915_perf_property_id {
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/**
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* Open the stream for a specific context handle (as used with
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* execbuffer2). A stream opened for a specific context this way
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* won't typically require root privileges.
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*/
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DRM_I915_PERF_PROP_CTX_HANDLE = 1,
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/**
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* A value of 1 requests the inclusion of raw OA unit reports as
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* part of stream samples.
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*/
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DRM_I915_PERF_PROP_SAMPLE_OA,
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/**
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* The value specifies which set of OA unit metrics should be
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* be configured, defining the contents of any OA unit reports.
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*/
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DRM_I915_PERF_PROP_OA_METRICS_SET,
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/**
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* The value specifies the size and layout of OA unit reports.
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*/
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DRM_I915_PERF_PROP_OA_FORMAT,
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/**
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* Specifying this property implicitly requests periodic OA unit
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* sampling and (at least on Haswell) the sampling frequency is derived
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* from this exponent as follows:
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*
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* 80ns * 2^(period_exponent + 1)
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*/
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DRM_I915_PERF_PROP_OA_EXPONENT,
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DRM_I915_PERF_PROP_MAX /* non-ABI */
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};
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struct drm_i915_perf_open_param {
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__u32 flags;
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#define I915_PERF_FLAG_FD_CLOEXEC (1<<0)
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#define I915_PERF_FLAG_FD_NONBLOCK (1<<1)
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#define I915_PERF_FLAG_DISABLED (1<<2)
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/** The number of u64 (id, value) pairs */
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__u32 num_properties;
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/**
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* Pointer to array of u64 (id, value) pairs configuring the stream
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* to open.
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*/
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__u64 properties_ptr;
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};
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/**
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* Enable data capture for a stream that was either opened in a disabled state
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* via I915_PERF_FLAG_DISABLED or was later disabled via
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* I915_PERF_IOCTL_DISABLE.
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*
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* It is intended to be cheaper to disable and enable a stream than it may be
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* to close and re-open a stream with the same configuration.
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*
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* It's undefined whether any pending data for the stream will be lost.
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*/
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#define I915_PERF_IOCTL_ENABLE _IO('i', 0x0)
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/**
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* Disable data capture for a stream.
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*
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* It is an error to try and read a stream that is disabled.
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*/
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#define I915_PERF_IOCTL_DISABLE _IO('i', 0x1)
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/**
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* Common to all i915 perf records
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*/
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struct drm_i915_perf_record_header {
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__u32 type;
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__u16 pad;
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__u16 size;
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};
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enum drm_i915_perf_record_type {
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/**
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* Samples are the work horse record type whose contents are extensible
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* and defined when opening an i915 perf stream based on the given
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* properties.
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*
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* Boolean properties following the naming convention
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* DRM_I915_PERF_SAMPLE_xyz_PROP request the inclusion of 'xyz' data in
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* every sample.
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*
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* The order of these sample properties given by userspace has no
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* affect on the ordering of data within a sample. The order is
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* documented here.
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*
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* struct {
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* struct drm_i915_perf_record_header header;
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*
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* { u32 oa_report[]; } && DRM_I915_PERF_PROP_SAMPLE_OA
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* };
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*/
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DRM_I915_PERF_RECORD_SAMPLE = 1,
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/*
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* Indicates that one or more OA reports were not written by the
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* hardware. This can happen for example if an MI_REPORT_PERF_COUNT
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* command collides with periodic sampling - which would be more likely
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* at higher sampling frequencies.
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*/
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DRM_I915_PERF_RECORD_OA_REPORT_LOST = 2,
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/**
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* An error occurred that resulted in all pending OA reports being lost.
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*/
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DRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3,
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DRM_I915_PERF_RECORD_MAX /* non-ABI */
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};
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#if defined(__cplusplus)
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}
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#endif
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@@ -110,6 +110,7 @@ header-y += dlm_netlink.h
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header-y += dlm_plock.h
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header-y += dm-ioctl.h
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header-y += dm-log-userspace.h
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header-y += dma-buf.h
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header-y += dn.h
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header-y += dqblk_xfs.h
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header-y += edd.h
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