From 724d52a3cd33774570c43cff06403b4cdda00abe Mon Sep 17 00:00:00 2001 From: Ivaylo Ivanov Date: Fri, 20 Sep 2024 18:45:02 +0300 Subject: [PATCH 01/11] dt-bindings: pinctrl: samsung: Add compatible for Exynos8895 SoC Add compatible for Exynos8895 SoC. Signed-off-by: Ivaylo Ivanov Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240920154508.1618410-5-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml index 242dd13c276b..a2af2c88a331 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml @@ -53,6 +53,7 @@ properties: - samsung,exynos7-pinctrl - samsung,exynos7885-pinctrl - samsung,exynos850-pinctrl + - samsung,exynos8895-pinctrl - samsung,exynosautov9-pinctrl - samsung,exynosautov920-pinctrl - tesla,fsd-pinctrl From e2d58d1e1c61c1e1d4af400cc0ebcebf98efb49f Mon Sep 17 00:00:00 2001 From: Ivaylo Ivanov Date: Fri, 20 Sep 2024 18:45:04 +0300 Subject: [PATCH 02/11] dt-bindings: pinctrl: samsung: add exynos8895-wakeup-eint compatible Add a dedicated compatible for exynos8895. Signed-off-by: Ivaylo Ivanov Acked-by: Rob Herring (Arm) Acked-by: Linus Walleij Link: https://lore.kernel.org/r/20240920154508.1618410-7-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml index 4dfb49b0e07f..91516fedc872 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml @@ -42,6 +42,7 @@ properties: - samsung,exynos5433-wakeup-eint - samsung,exynos7885-wakeup-eint - samsung,exynos850-wakeup-eint + - samsung,exynos8895-wakeup-eint - const: samsung,exynos7-wakeup-eint - items: - enum: From eed2e79221e2b4a1d1469aa522f658889cd640ee Mon Sep 17 00:00:00 2001 From: Ivaylo Ivanov Date: Fri, 20 Sep 2024 18:45:03 +0300 Subject: [PATCH 03/11] pinctrl: samsung: Add exynos8895 SoC pinctrl configuration Add support for the pin-controller found on the Exynos8895 SoC used in Samsung Galaxy S8 and S8 Plus phones. It has a newly applied pinctrl register layer for FSYS0 with a different bank type offset that consists of the following bit fields: CON: 4, DAT: 1, PUD: 2, DRV: 3, CONPDN: 2, PUDPDN: 2 Signed-off-by: Ivaylo Ivanov Reviewed-by: Sam Protsenko Acked-by: Linus Walleij Link: https://lore.kernel.org/r/20240920154508.1618410-6-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../pinctrl/samsung/pinctrl-exynos-arm64.c | 137 ++++++++++++++++++ drivers/pinctrl/samsung/pinctrl-exynos.h | 10 ++ drivers/pinctrl/samsung/pinctrl-samsung.c | 2 + drivers/pinctrl/samsung/pinctrl-samsung.h | 1 + 4 files changed, 150 insertions(+) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c index 5480e0884abe..c5df4f1bc600 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -58,6 +58,15 @@ static const struct samsung_pin_bank_type exynos850_bank_type_alive = { .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, }; +/* + * Bank type for non-alive type. Bit fields: + * CON: 4, DAT: 1, PUD: 2, DRV: 3, CONPDN: 2, PUDPDN: 2 + */ +static const struct samsung_pin_bank_type exynos8895_bank_type_off = { + .fld_width = { 4, 1, 2, 3, 2, 2, }, + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, +}; + /* Pad retention control code for accessing PMU regmap */ static atomic_t exynos_shared_retention_refcnt; @@ -866,6 +875,134 @@ const struct samsung_pinctrl_of_match_data exynosautov920_of_data __initconst = .num_ctrl = ARRAY_SIZE(exynosautov920_pin_ctrl), }; +/* pin banks of exynos8895 pin-controller 0 (ALIVE) */ +static const struct samsung_pin_bank_data exynos8895_pin_banks0[] __initconst = { + EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa0", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa1", 0x04), + EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa2", 0x08), + EXYNOS_PIN_BANK_EINTW(8, 0x080, "gpa3", 0x0c), + EXYNOS_PIN_BANK_EINTW(7, 0x0a0, "gpa4", 0x24), +}; + +/* pin banks of exynos8895 pin-controller 1 (ABOX) */ +static const struct samsung_pin_bank_data exynos8895_pin_banks1[] __initconst = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gph0", 0x00), + EXYNOS_PIN_BANK_EINTG(7, 0x020, "gph1", 0x04), + EXYNOS_PIN_BANK_EINTG(4, 0x040, "gph3", 0x08), +}; + +/* pin banks of exynos8895 pin-controller 2 (VTS) */ +static const struct samsung_pin_bank_data exynos8895_pin_banks2[] __initconst = { + EXYNOS_PIN_BANK_EINTG(3, 0x000, "gph2", 0x00), +}; + +/* pin banks of exynos8895 pin-controller 3 (FSYS0) */ +static const struct samsung_pin_bank_data exynos8895_pin_banks3[] __initconst = { + EXYNOS8895_PIN_BANK_EINTG(3, 0x000, "gpi0", 0x00), + EXYNOS8895_PIN_BANK_EINTG(8, 0x020, "gpi1", 0x04), +}; + +/* pin banks of exynos8895 pin-controller 4 (FSYS1) */ +static const struct samsung_pin_bank_data exynos8895_pin_banks4[] __initconst = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj1", 0x00), + EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpj0", 0x04), +}; + +/* pin banks of exynos8895 pin-controller 5 (BUSC) */ +static const struct samsung_pin_bank_data exynos8895_pin_banks5[] __initconst = { + EXYNOS_PIN_BANK_EINTG(2, 0x000, "gpb2", 0x00), +}; + +/* pin banks of exynos8895 pin-controller 6 (PERIC0) */ +static const struct samsung_pin_bank_data exynos8895_pin_banks6[] __initconst = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpd0", 0x00), + EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpd1", 0x04), + EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpd2", 0x08), + EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpd3", 0x0C), + EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10), + EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpe7", 0x14), + EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpf1", 0x18), +}; + +/* pin banks of exynos8895 pin-controller 7 (PERIC1) */ +static const struct samsung_pin_bank_data exynos8895_pin_banks7[] __initconst = { + EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpb0", 0x00), + EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpc0", 0x04), + EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpc1", 0x08), + EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpc2", 0x0C), + EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpc3", 0x10), + EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpk0", 0x14), + EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpe5", 0x18), + EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpe6", 0x1C), + EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe2", 0x20), + EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpe3", 0x24), + EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe4", 0x28), + EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpf0", 0x2C), + EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe1", 0x30), + EXYNOS_PIN_BANK_EINTG(2, 0x1a0, "gpg0", 0x34), +}; + +static const struct samsung_pin_ctrl exynos8895_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 ALIVE data */ + .pin_banks = exynos8895_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos8895_pin_banks0), + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 1 ABOX data */ + .pin_banks = exynos8895_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos8895_pin_banks1), + }, { + /* pin-controller instance 2 VTS data */ + .pin_banks = exynos8895_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos8895_pin_banks2), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 3 FSYS0 data */ + .pin_banks = exynos8895_pin_banks3, + .nr_banks = ARRAY_SIZE(exynos8895_pin_banks3), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 4 FSYS1 data */ + .pin_banks = exynos8895_pin_banks4, + .nr_banks = ARRAY_SIZE(exynos8895_pin_banks4), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 5 BUSC data */ + .pin_banks = exynos8895_pin_banks5, + .nr_banks = ARRAY_SIZE(exynos8895_pin_banks5), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 6 PERIC0 data */ + .pin_banks = exynos8895_pin_banks6, + .nr_banks = ARRAY_SIZE(exynos8895_pin_banks6), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 7 PERIC1 data */ + .pin_banks = exynos8895_pin_banks7, + .nr_banks = ARRAY_SIZE(exynos8895_pin_banks7), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, +}; + +const struct samsung_pinctrl_of_match_data exynos8895_of_data __initconst = { + .ctrl = exynos8895_pin_ctrl, + .num_ctrl = ARRAY_SIZE(exynos8895_pin_ctrl), +}; + /* * Pinctrl driver data for Tesla FSD SoC. FSD SoC includes three * gpio/pin-mux/pinconfig controllers. diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h index 305cb1d31de4..7b7ff7ffeb56 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.h +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h @@ -141,6 +141,16 @@ .name = id \ } +#define EXYNOS8895_PIN_BANK_EINTG(pins, reg, id, offs) \ + { \ + .type = &exynos8895_bank_type_off, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_GPIO, \ + .eint_offset = offs, \ + .name = id \ + } + #define EXYNOSV920_PIN_BANK_EINTG(pins, reg, id, con_offs, mask_offs, pend_offs) \ { \ .type = &exynos850_bank_type_off, \ diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index 675efa5d86a9..86c7de109bca 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -1477,6 +1477,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { .data = &exynos7885_of_data }, { .compatible = "samsung,exynos850-pinctrl", .data = &exynos850_of_data }, + { .compatible = "samsung,exynos8895-pinctrl", + .data = &exynos8895_of_data }, { .compatible = "samsung,exynosautov9-pinctrl", .data = &exynosautov9_of_data }, { .compatible = "samsung,exynosautov920-pinctrl", diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h index a1e7377bd890..dc930d620f55 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -384,6 +384,7 @@ extern const struct samsung_pinctrl_of_match_data exynos5433_of_data; extern const struct samsung_pinctrl_of_match_data exynos7_of_data; extern const struct samsung_pinctrl_of_match_data exynos7885_of_data; extern const struct samsung_pinctrl_of_match_data exynos850_of_data; +extern const struct samsung_pinctrl_of_match_data exynos8895_of_data; extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data; extern const struct samsung_pinctrl_of_match_data exynosautov920_of_data; extern const struct samsung_pinctrl_of_match_data fsd_of_data; From ffb30875172eabff727e2896f097ccd4bb68723f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 15 Oct 2024 08:58:47 +0200 Subject: [PATCH 04/11] dt-bindings: pinctrl: samsung: Fix interrupt constraint for variants with fallbacks Commit 904140fa4553 ("dt-bindings: pinctrl: samsung: use Exynos7 fallbacks for newer wake-up controllers") added samsung,exynos7-wakeup-eint fallback to some compatibles, so the intention in the if:then: conditions was to handle the cases: 1. Single Exynos7 compatible or Exynos5433+Exynos7 or Exynos7885+Exynos7: only one interrupt 2. Exynos850+Exynos7: no interrupts This was not implemented properly however and if:then: block matches only single Exynos5433 or Exynos7885 compatibles, which do not exist in DTS anymore, so basically is a no-op and no enforcement on number of interrupts is made by the binding. Fix the if:then: condition so interrupts in the Exynos5433 and Exynos7885 wake-up pin controller will be properly constrained. Fixes: 904140fa4553 ("dt-bindings: pinctrl: samsung: use Exynos7 fallbacks for newer wake-up controllers") Cc: stable@vger.kernel.org Acked-by: Rob Herring (Arm) Reviewed-by: Linus Walleij Link: https://lore.kernel.org/r/20241015065848.29429-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../samsung,pinctrl-wakeup-interrupt.yaml | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml index 91516fedc872..49cb2b1a3d28 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml @@ -92,14 +92,17 @@ allOf: - if: properties: compatible: - # Match without "contains", to skip newer variants which are still - # compatible with samsung,exynos7-wakeup-eint - enum: - - samsung,s5pv210-wakeup-eint - - samsung,exynos4210-wakeup-eint - - samsung,exynos5433-wakeup-eint - - samsung,exynos7-wakeup-eint - - samsung,exynos7885-wakeup-eint + oneOf: + # Match without "contains", to skip newer variants which are still + # compatible with samsung,exynos7-wakeup-eint + - enum: + - samsung,exynos4210-wakeup-eint + - samsung,exynos7-wakeup-eint + - samsung,s5pv210-wakeup-eint + - contains: + enum: + - samsung,exynos5433-wakeup-eint + - samsung,exynos7885-wakeup-eint then: properties: interrupts: From e0f89ba1e04307a0060b354c40d29d008a3fef6e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 15 Oct 2024 08:58:48 +0200 Subject: [PATCH 05/11] dt-bindings: pinctrl: samsung: Add missing constraint for Exynos8895 interrupts Expect only one interrupt on Exynos8895 wake-up pin controller. Fixes: e2d58d1e1c61 ("dt-bindings: pinctrl: samsung: add exynos8895-wakeup-eint compatible") Acked-by: Rob Herring (Arm) Reviewed-by: Linus Walleij Link: https://lore.kernel.org/r/20241015065848.29429-2-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml index 49cb2b1a3d28..b7c2692f0ac3 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml @@ -103,6 +103,7 @@ allOf: enum: - samsung,exynos5433-wakeup-eint - samsung,exynos7885-wakeup-eint + - samsung,exynos8895-wakeup-eint then: properties: interrupts: From 5b653cb60275e1ad1a85f0d056a3084c4635623c Mon Sep 17 00:00:00 2001 From: Igor Belwon Date: Wed, 16 Oct 2024 17:48:36 +0200 Subject: [PATCH 06/11] dt-bindings: pinctrl: samsung: Add exynos990-pinctrl compatible Add a dedicated compatible for the exynos990-pinctrl node. Signed-off-by: Igor Belwon Link: https://lore.kernel.org/r/20241016154838.64515-2-igor.belwon@mentallysanemainliners.org Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml index a2af2c88a331..7e6ef8249de6 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml @@ -54,6 +54,7 @@ properties: - samsung,exynos7885-pinctrl - samsung,exynos850-pinctrl - samsung,exynos8895-pinctrl + - samsung,exynos990-pinctrl - samsung,exynosautov9-pinctrl - samsung,exynosautov920-pinctrl - tesla,fsd-pinctrl From e690012f4f924f4ef4e105427b04ea3d496c6a38 Mon Sep 17 00:00:00 2001 From: Igor Belwon Date: Wed, 16 Oct 2024 17:48:37 +0200 Subject: [PATCH 07/11] dt-bindings: pinctrl: samsung: Add exynos990-wakeup-eint compatible Add a dedicated compatible for the exynos990-wakeup-eint node. This SoC pin controller does not mux interrupts. It's compatible with Exynos 850's node, while also being compatible with the Exynos7 fallback. Signed-off-by: Igor Belwon Link: https://lore.kernel.org/r/20241016154838.64515-3-igor.belwon@mentallysanemainliners.org Signed-off-by: Krzysztof Kozlowski --- .../bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml index b7c2692f0ac3..565cacadb6be 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml @@ -47,6 +47,7 @@ properties: - items: - enum: - google,gs101-wakeup-eint + - samsung,exynos990-wakeup-eint - samsung,exynosautov9-wakeup-eint - const: samsung,exynos850-wakeup-eint - const: samsung,exynos7-wakeup-eint From 2193074458dee3c4382c023740d86578db050bd8 Mon Sep 17 00:00:00 2001 From: Igor Belwon Date: Wed, 16 Oct 2024 17:48:38 +0200 Subject: [PATCH 08/11] pinctrl: samsung: Add Exynos 990 SoC pinctrl configuration Add SoC pinctrl configuration for the Exynos 990. The bank types used are the same as Exynos 850, so we can reuse its macros. Signed-off-by: Igor Belwon Link: https://lore.kernel.org/r/20241016154838.64515-4-igor.belwon@mentallysanemainliners.org Signed-off-by: Krzysztof Kozlowski --- .../pinctrl/samsung/pinctrl-exynos-arm64.c | 140 ++++++++++++++++++ drivers/pinctrl/samsung/pinctrl-samsung.c | 2 + drivers/pinctrl/samsung/pinctrl-samsung.h | 1 + 3 files changed, 143 insertions(+) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c index c5df4f1bc600..f07c26d37442 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -627,6 +627,146 @@ const struct samsung_pinctrl_of_match_data exynos850_of_data __initconst = { .num_ctrl = ARRAY_SIZE(exynos850_pin_ctrl), }; +/* pin banks of exynos990 pin-controller 0 (ALIVE) */ +static struct samsung_pin_bank_data exynos990_pin_banks0[] = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS850_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), + EXYNOS850_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), + EXYNOS850_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), + EXYNOS850_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), + EXYNOS850_PIN_BANK_EINTW(2, 0x080, "gpa4", 0x10), + EXYNOS850_PIN_BANK_EINTN(7, 0x0A0, "gpq0"), +}; + +/* pin banks of exynos990 pin-controller 1 (CMGP) */ +static struct samsung_pin_bank_data exynos990_pin_banks1[] = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS850_PIN_BANK_EINTN(1, 0x000, "gpm0"), + EXYNOS850_PIN_BANK_EINTN(1, 0x020, "gpm1"), + EXYNOS850_PIN_BANK_EINTN(1, 0x040, "gpm2"), + EXYNOS850_PIN_BANK_EINTN(1, 0x060, "gpm3"), + EXYNOS850_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x00), + EXYNOS850_PIN_BANK_EINTW(1, 0x0A0, "gpm5", 0x04), + EXYNOS850_PIN_BANK_EINTW(1, 0x0C0, "gpm6", 0x08), + EXYNOS850_PIN_BANK_EINTW(1, 0x0E0, "gpm7", 0x0c), + EXYNOS850_PIN_BANK_EINTW(1, 0x100, "gpm8", 0x10), + EXYNOS850_PIN_BANK_EINTW(1, 0x120, "gpm9", 0x14), + EXYNOS850_PIN_BANK_EINTW(1, 0x140, "gpm10", 0x18), + EXYNOS850_PIN_BANK_EINTW(1, 0x160, "gpm11", 0x1c), + EXYNOS850_PIN_BANK_EINTW(1, 0x180, "gpm12", 0x20), + EXYNOS850_PIN_BANK_EINTW(1, 0x1A0, "gpm13", 0x24), + EXYNOS850_PIN_BANK_EINTW(1, 0x1C0, "gpm14", 0x28), + EXYNOS850_PIN_BANK_EINTW(1, 0x1E0, "gpm15", 0x2c), + EXYNOS850_PIN_BANK_EINTW(1, 0x200, "gpm16", 0x30), + EXYNOS850_PIN_BANK_EINTW(1, 0x220, "gpm17", 0x34), + EXYNOS850_PIN_BANK_EINTW(1, 0x240, "gpm18", 0x38), + EXYNOS850_PIN_BANK_EINTW(1, 0x260, "gpm19", 0x3c), + EXYNOS850_PIN_BANK_EINTW(1, 0x280, "gpm20", 0x40), + EXYNOS850_PIN_BANK_EINTW(1, 0x2A0, "gpm21", 0x44), + EXYNOS850_PIN_BANK_EINTW(1, 0x2C0, "gpm22", 0x48), + EXYNOS850_PIN_BANK_EINTW(1, 0x2E0, "gpm23", 0x4c), + EXYNOS850_PIN_BANK_EINTW(1, 0x300, "gpm24", 0x50), + EXYNOS850_PIN_BANK_EINTW(1, 0x320, "gpm25", 0x54), + EXYNOS850_PIN_BANK_EINTW(1, 0x340, "gpm26", 0x58), + EXYNOS850_PIN_BANK_EINTW(1, 0x360, "gpm27", 0x5c), + EXYNOS850_PIN_BANK_EINTW(1, 0x380, "gpm28", 0x60), + EXYNOS850_PIN_BANK_EINTW(1, 0x3A0, "gpm29", 0x64), + EXYNOS850_PIN_BANK_EINTW(1, 0x3C0, "gpm30", 0x68), + EXYNOS850_PIN_BANK_EINTW(1, 0x3E0, "gpm31", 0x6c), + EXYNOS850_PIN_BANK_EINTW(1, 0x400, "gpm32", 0x70), + EXYNOS850_PIN_BANK_EINTW(1, 0x420, "gpm33", 0x74), + +}; + +/* pin banks of exynos990 pin-controller 2 (HSI1) */ +static struct samsung_pin_bank_data exynos990_pin_banks2[] = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpf0", 0x00), + EXYNOS850_PIN_BANK_EINTG(6, 0x020, "gpf1", 0x04), + EXYNOS850_PIN_BANK_EINTG(3, 0x040, "gpf2", 0x08), +}; + +/* pin banks of exynos990 pin-controller 3 (HSI2) */ +static struct samsung_pin_bank_data exynos990_pin_banks3[] = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS850_PIN_BANK_EINTG(2, 0x000, "gpf3", 0x00), +}; + +/* pin banks of exynos990 pin-controller 4 (PERIC0) */ +static struct samsung_pin_bank_data exynos990_pin_banks4[] = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp0", 0x00), + EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp1", 0x04), + EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpp2", 0x08), + EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpp3", 0x0C), + EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpp4", 0x10), + EXYNOS850_PIN_BANK_EINTG(2, 0x0A0, "gpg0", 0x14), +}; + +/* pin banks of exynos990 pin-controller 5 (PERIC1) */ +static struct samsung_pin_bank_data exynos990_pin_banks5[] = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp5", 0x00), + EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp6", 0x04), + EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpp7", 0x08), + EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpp8", 0x0C), + EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpp9", 0x10), + EXYNOS850_PIN_BANK_EINTG(6, 0x0A0, "gpc0", 0x14), + EXYNOS850_PIN_BANK_EINTG(4, 0x0C0, "gpg1", 0x18), + EXYNOS850_PIN_BANK_EINTG(8, 0x0E0, "gpb0", 0x1C), + EXYNOS850_PIN_BANK_EINTG(8, 0x100, "gpb1", 0x20), + EXYNOS850_PIN_BANK_EINTG(8, 0x120, "gpb2", 0x24), +}; + +/* pin banks of exynos990 pin-controller 6 (VTS) */ +static struct samsung_pin_bank_data exynos990_pin_banks6[] = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS850_PIN_BANK_EINTG(7, 0x000, "gpv0", 0x00), +}; + +static const struct samsung_pin_ctrl exynos990_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 ALIVE data */ + .pin_banks = exynos990_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos990_pin_banks0), + .eint_wkup_init = exynos_eint_wkup_init, + }, { + /* pin-controller instance 1 CMGP data */ + .pin_banks = exynos990_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos990_pin_banks1), + .eint_wkup_init = exynos_eint_wkup_init, + }, { + /* pin-controller instance 2 HSI1 data */ + .pin_banks = exynos990_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos990_pin_banks2), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 3 HSI2 data */ + .pin_banks = exynos990_pin_banks3, + .nr_banks = ARRAY_SIZE(exynos990_pin_banks3), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 4 PERIC0 data */ + .pin_banks = exynos990_pin_banks4, + .nr_banks = ARRAY_SIZE(exynos990_pin_banks4), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 5 PERIC1 data */ + .pin_banks = exynos990_pin_banks5, + .nr_banks = ARRAY_SIZE(exynos990_pin_banks5), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 6 VTS data */ + .pin_banks = exynos990_pin_banks6, + .nr_banks = ARRAY_SIZE(exynos990_pin_banks6), + }, +}; + +const struct samsung_pinctrl_of_match_data exynos990_of_data __initconst = { + .ctrl = exynos990_pin_ctrl, + .num_ctrl = ARRAY_SIZE(exynos990_pin_ctrl), +}; + /* pin banks of exynosautov9 pin-controller 0 (ALIVE) */ static const struct samsung_pin_bank_data exynosautov9_pin_banks0[] __initconst = { EXYNOS850_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index 86c7de109bca..42e40860841b 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -1479,6 +1479,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { .data = &exynos850_of_data }, { .compatible = "samsung,exynos8895-pinctrl", .data = &exynos8895_of_data }, + { .compatible = "samsung,exynos990-pinctrl", + .data = &exynos990_of_data }, { .compatible = "samsung,exynosautov9-pinctrl", .data = &exynosautov9_of_data }, { .compatible = "samsung,exynosautov920-pinctrl", diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h index dc930d620f55..615048f94524 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -385,6 +385,7 @@ extern const struct samsung_pinctrl_of_match_data exynos7_of_data; extern const struct samsung_pinctrl_of_match_data exynos7885_of_data; extern const struct samsung_pinctrl_of_match_data exynos850_of_data; extern const struct samsung_pinctrl_of_match_data exynos8895_of_data; +extern const struct samsung_pinctrl_of_match_data exynos990_of_data; extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data; extern const struct samsung_pinctrl_of_match_data exynosautov920_of_data; extern const struct samsung_pinctrl_of_match_data fsd_of_data; From 47c3309d58b5e6fd3fc425253491c1ce014538c0 Mon Sep 17 00:00:00 2001 From: Markuss Broks Date: Sat, 26 Oct 2024 23:32:34 +0300 Subject: [PATCH 09/11] dt-bindings: pinctrl: samsung: Add compatible for Exynos9810 SoC Add a compatible for Samsung Exynos9810 pinctrl block to the schema. Exynos9810 has 9 total pin banks and it's similar to other Samsung SoC pinctrl blocks. Co-developed-by: Maksym Holovach Signed-off-by: Maksym Holovach Signed-off-by: Markuss Broks Link: https://lore.kernel.org/r/20241026-exynos9810-v3-3-b89de9441ea8@gmail.com Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml index 7e6ef8249de6..5296a9e4faae 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml @@ -54,6 +54,7 @@ properties: - samsung,exynos7885-pinctrl - samsung,exynos850-pinctrl - samsung,exynos8895-pinctrl + - samsung,exynos9810-pinctrl - samsung,exynos990-pinctrl - samsung,exynosautov9-pinctrl - samsung,exynosautov920-pinctrl From e830431e0ad0501c2e6dcb3c65dabc053e3ce5e4 Mon Sep 17 00:00:00 2001 From: Markuss Broks Date: Sat, 26 Oct 2024 23:32:35 +0300 Subject: [PATCH 10/11] dt-bindings: pinctrl: samsung: Add compatible for exynos9810-wakeup-eint Add the compatible for Samsung Exynos9810 pinctrl eint block to the schema. It is compatible with Exynos850 EINT controller, and doesn't have a dedicated IRQ line. Co-developed-by: Maksym Holovach Signed-off-by: Maksym Holovach Signed-off-by: Markuss Broks Link: https://lore.kernel.org/r/20241026-exynos9810-v3-4-b89de9441ea8@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml index 565cacadb6be..68ed714eb0a1 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml @@ -47,6 +47,7 @@ properties: - items: - enum: - google,gs101-wakeup-eint + - samsung,exynos9810-wakeup-eint - samsung,exynos990-wakeup-eint - samsung,exynosautov9-wakeup-eint - const: samsung,exynos850-wakeup-eint From 6d2dbd4cec8939ad2b813b8052eb12406db528d7 Mon Sep 17 00:00:00 2001 From: Markuss Broks Date: Sat, 26 Oct 2024 23:32:39 +0300 Subject: [PATCH 11/11] pinctrl: samsung: Add Exynos9810 SoC specific data Add Samsung Exynos9810 SoC specific data to enable pinctrl support for platforms based on Exynos9810. Co-developed-by: Maksym Holovach Signed-off-by: Maksym Holovach Signed-off-by: Markuss Broks Link: https://lore.kernel.org/r/20241026-exynos9810-v3-8-b89de9441ea8@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../pinctrl/samsung/pinctrl-exynos-arm64.c | 154 ++++++++++++++++++ drivers/pinctrl/samsung/pinctrl-samsung.c | 2 + drivers/pinctrl/samsung/pinctrl-samsung.h | 1 + 3 files changed, 157 insertions(+) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c index f07c26d37442..3ea7106ce5ea 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -767,6 +767,160 @@ const struct samsung_pinctrl_of_match_data exynos990_of_data __initconst = { .num_ctrl = ARRAY_SIZE(exynos990_pin_ctrl), }; +/* pin banks of exynos9810 pin-controller 0 (ALIVE) */ +static const struct samsung_pin_bank_data exynos9810_pin_banks0[] __initconst = { + EXYNOS850_PIN_BANK_EINTN(6, 0x000, "etc1"), + EXYNOS850_PIN_BANK_EINTW(8, 0x020, "gpa0", 0x00), + EXYNOS850_PIN_BANK_EINTW(8, 0x040, "gpa1", 0x04), + EXYNOS850_PIN_BANK_EINTW(8, 0x060, "gpa2", 0x08), + EXYNOS850_PIN_BANK_EINTW(8, 0x080, "gpa3", 0x0c), + EXYNOS850_PIN_BANK_EINTN(6, 0x0A0, "gpq0"), + EXYNOS850_PIN_BANK_EINTW(2, 0x0C0, "gpa4", 0x10), +}; + +/* pin banks of exynos9810 pin-controller 1 (AUD) */ +static const struct samsung_pin_bank_data exynos9810_pin_banks1[] __initconst = { + EXYNOS850_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), + EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpb1", 0x04), + EXYNOS850_PIN_BANK_EINTG(4, 0x040, "gpb2", 0x08), +}; + +/* pin banks of exynos9810 pin-controller 2 (CHUB) */ +static const struct samsung_pin_bank_data exynos9810_pin_banks2[] __initconst = { + EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gph0", 0x00), + EXYNOS850_PIN_BANK_EINTG(5, 0x020, "gph1", 0x04), +}; + +/* pin banks of exynos9810 pin-controller 3 (CMGP) */ +static const struct samsung_pin_bank_data exynos9810_pin_banks3[] __initconst = { + EXYNOS850_PIN_BANK_EINTW(1, 0x000, "gpm0", 0x00), + EXYNOS850_PIN_BANK_EINTW(1, 0x020, "gpm1", 0x04), + EXYNOS850_PIN_BANK_EINTW(1, 0x040, "gpm2", 0x08), + EXYNOS850_PIN_BANK_EINTW(1, 0x060, "gpm3", 0x0C), + EXYNOS850_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x10), + EXYNOS850_PIN_BANK_EINTW(1, 0x0A0, "gpm5", 0x14), + EXYNOS850_PIN_BANK_EINTW(1, 0x0C0, "gpm6", 0x18), + EXYNOS850_PIN_BANK_EINTW(1, 0x0E0, "gpm7", 0x1C), + EXYNOS850_PIN_BANK_EINTW(1, 0x100, "gpm10", 0x20), + EXYNOS850_PIN_BANK_EINTW(1, 0x120, "gpm11", 0x24), + EXYNOS850_PIN_BANK_EINTW(1, 0x140, "gpm12", 0x28), + EXYNOS850_PIN_BANK_EINTW(1, 0x160, "gpm13", 0x2C), + EXYNOS850_PIN_BANK_EINTW(1, 0x180, "gpm14", 0x30), + EXYNOS850_PIN_BANK_EINTW(1, 0x1A0, "gpm15", 0x34), + EXYNOS850_PIN_BANK_EINTW(1, 0x1C0, "gpm16", 0x38), + EXYNOS850_PIN_BANK_EINTW(1, 0x1E0, "gpm17", 0x3C), + EXYNOS850_PIN_BANK_EINTW(1, 0x200, "gpm40", 0x40), + EXYNOS850_PIN_BANK_EINTW(1, 0x220, "gpm41", 0x44), + EXYNOS850_PIN_BANK_EINTW(1, 0x240, "gpm42", 0x48), + EXYNOS850_PIN_BANK_EINTW(1, 0x260, "gpm43", 0x4C), +}; + +/* pin banks of exynos9810 pin-controller 4 (FSYS0) */ +static const struct samsung_pin_bank_data exynos9810_pin_banks4[] __initconst = { + EXYNOS850_PIN_BANK_EINTG(2, 0x000, "gpf0", 0x00), +}; + +/* pin banks of exynos9810 pin-controller 5 (FSYS1) */ +static const struct samsung_pin_bank_data exynos9810_pin_banks5[] __initconst = { + EXYNOS850_PIN_BANK_EINTG(7, 0x000, "gpf1", 0x00), + EXYNOS850_PIN_BANK_EINTG(6, 0x020, "gpf2", 0x04), +}; + +/* pin banks of exynos9810 pin-controller 6 (PERIC0) */ +static const struct samsung_pin_bank_data exynos9810_pin_banks6[] __initconst = { + EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp0", 0x00), + EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp1", 0x04), + EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpp2", 0x08), + EXYNOS850_PIN_BANK_EINTG(4, 0x060, "gpp3", 0x0C), + EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10), + EXYNOS850_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14), + EXYNOS850_PIN_BANK_EINTG(8, 0x0C0, "gpg2", 0x18), +}; + +/* pin banks of exynos9810 pin-controller 7 (PERIC1) */ +static const struct samsung_pin_bank_data exynos9810_pin_banks7[] __initconst = { + EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp4", 0x00), + EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp5", 0x04), + EXYNOS850_PIN_BANK_EINTG(4, 0x040, "gpp6", 0x08), + EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpc0", 0x0C), + EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpc1", 0x10), + EXYNOS850_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14), + EXYNOS850_PIN_BANK_EINTG(7, 0x0C0, "gpg3", 0x18), +}; + +/* pin banks of exynos9810 pin-controller 8 (VTS) */ +static const struct samsung_pin_bank_data exynos9810_pin_banks8[] __initconst = { + EXYNOS850_PIN_BANK_EINTG(3, 0x000, "gpt0", 0x00), +}; + +static const struct samsung_pin_ctrl exynos9810_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 ALIVE data */ + .pin_banks = exynos9810_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos9810_pin_banks0), + .eint_wkup_init = exynos_eint_wkup_init, + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 1 AUD data */ + .pin_banks = exynos9810_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos9810_pin_banks1), + }, { + /* pin-controller instance 2 CHUB data */ + .pin_banks = exynos9810_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos9810_pin_banks2), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 3 CMGP data */ + .pin_banks = exynos9810_pin_banks3, + .nr_banks = ARRAY_SIZE(exynos9810_pin_banks3), + .eint_wkup_init = exynos_eint_wkup_init, + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 4 FSYS0 data */ + .pin_banks = exynos9810_pin_banks4, + .nr_banks = ARRAY_SIZE(exynos9810_pin_banks4), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 5 FSYS1 data */ + .pin_banks = exynos9810_pin_banks5, + .nr_banks = ARRAY_SIZE(exynos9810_pin_banks5), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 6 PERIC0 data */ + .pin_banks = exynos9810_pin_banks6, + .nr_banks = ARRAY_SIZE(exynos9810_pin_banks6), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 7 PERIC1 data */ + .pin_banks = exynos9810_pin_banks7, + .nr_banks = ARRAY_SIZE(exynos9810_pin_banks7), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 8 VTS data */ + .pin_banks = exynos9810_pin_banks8, + .nr_banks = ARRAY_SIZE(exynos9810_pin_banks8), + }, +}; + +const struct samsung_pinctrl_of_match_data exynos9810_of_data __initconst = { + .ctrl = exynos9810_pin_ctrl, + .num_ctrl = ARRAY_SIZE(exynos9810_pin_ctrl), +}; + /* pin banks of exynosautov9 pin-controller 0 (ALIVE) */ static const struct samsung_pin_bank_data exynosautov9_pin_banks0[] __initconst = { EXYNOS850_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index 42e40860841b..bbedd980ec67 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -1479,6 +1479,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { .data = &exynos850_of_data }, { .compatible = "samsung,exynos8895-pinctrl", .data = &exynos8895_of_data }, + { .compatible = "samsung,exynos9810-pinctrl", + .data = &exynos9810_of_data }, { .compatible = "samsung,exynos990-pinctrl", .data = &exynos990_of_data }, { .compatible = "samsung,exynosautov9-pinctrl", diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h index 615048f94524..bb0689d52ea0 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -385,6 +385,7 @@ extern const struct samsung_pinctrl_of_match_data exynos7_of_data; extern const struct samsung_pinctrl_of_match_data exynos7885_of_data; extern const struct samsung_pinctrl_of_match_data exynos850_of_data; extern const struct samsung_pinctrl_of_match_data exynos8895_of_data; +extern const struct samsung_pinctrl_of_match_data exynos9810_of_data; extern const struct samsung_pinctrl_of_match_data exynos990_of_data; extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data; extern const struct samsung_pinctrl_of_match_data exynosautov920_of_data;