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Merge tag 'riscv-for-linus-6.8-mw4' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

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Pull more RISC-V updates from Palmer Dabbelt:

 - Support for tuning for systems with fast misaligned accesses.

 - Support for SBI-based suspend.

 - Support for the new SBI debug console extension.

 - The T-Head CMOs now use PA-based flushes.

 - Support for enabling the V extension in kernel code.

 - Optimized IP checksum routines.

 - Various ftrace improvements.

 - Support for archrandom, which depends on the Zkr extension.

 - The build is no longer broken under NET=n, KUNIT=y for ports that
   don't define their own ipv6 checksum.

* tag 'riscv-for-linus-6.8-mw4' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (56 commits)
  lib: checksum: Fix build with CONFIG_NET=n
  riscv: lib: Check if output in asm goto supported
  riscv: Fix build error on rv32 + XIP
  riscv: optimize ELF relocation function in riscv
  RISC-V: Implement archrandom when Zkr is available
  riscv: Optimize hweight API with Zbb extension
  riscv: add dependency among Image(.gz), loader(.bin), and vmlinuz.efi
  samples: ftrace: Add RISC-V support for SAMPLE_FTRACE_DIRECT[_MULTI]
  riscv: ftrace: Add DYNAMIC_FTRACE_WITH_DIRECT_CALLS support
  riscv: ftrace: Make function graph use ftrace directly
  riscv: select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY
  lib/Kconfig.debug: Update AS_HAS_NON_CONST_LEB128 comment and name
  riscv: Restrict DWARF5 when building with LLVM to known working versions
  riscv: Hoist linker relaxation disabling logic into Kconfig
  kunit: Add tests for csum_ipv6_magic and ip_fast_csum
  riscv: Add checksum library
  riscv: Add checksum header
  riscv: Add static key for misaligned accesses
  asm-generic: Improve csum_fold
  RISC-V: selftests: cbo: Ensure asm operands match constraints
  ...
This commit is contained in:
Linus Torvalds
2024-01-20 11:06:04 -08:00
parent c25b24fa72 f24a70106d
commit e5075d8ec5
71 changed files with 2678 additions and 215 deletions
Download Patch File Download Diff File Expand all files Collapse all files
samples/ftrace/ftrace-direct-modify.c
+35
View File
@@ -24,6 +24,41 @@ extern void my_tramp2(void *);
static unsigned long my_ip = (unsigned long)schedule;
#ifdef CONFIG_RISCV
#include <asm/asm.h>
asm (
" .pushsection .text, \"ax\", @progbits\n"
" .type my_tramp1, @function\n"
" .globl my_tramp1\n"
" my_tramp1:\n"
" addi sp,sp,-2*"SZREG"\n"
" "REG_S" t0,0*"SZREG"(sp)\n"
" "REG_S" ra,1*"SZREG"(sp)\n"
" call my_direct_func1\n"
" "REG_L" t0,0*"SZREG"(sp)\n"
" "REG_L" ra,1*"SZREG"(sp)\n"
" addi sp,sp,2*"SZREG"\n"
" jr t0\n"
" .size my_tramp1, .-my_tramp1\n"
" .type my_tramp2, @function\n"
" .globl my_tramp2\n"
" my_tramp2:\n"
" addi sp,sp,-2*"SZREG"\n"
" "REG_S" t0,0*"SZREG"(sp)\n"
" "REG_S" ra,1*"SZREG"(sp)\n"
" call my_direct_func2\n"
" "REG_L" t0,0*"SZREG"(sp)\n"
" "REG_L" ra,1*"SZREG"(sp)\n"
" addi sp,sp,2*"SZREG"\n"
" jr t0\n"
" .size my_tramp2, .-my_tramp2\n"
" .popsection\n"
);
#endif /* CONFIG_RISCV */
#ifdef CONFIG_X86_64
#include <asm/ibt.h>
samples/ftrace/ftrace-direct-multi-modify.c
+41
View File
@@ -22,6 +22,47 @@ void my_direct_func2(unsigned long ip)
extern void my_tramp1(void *);
extern void my_tramp2(void *);
#ifdef CONFIG_RISCV
#include <asm/asm.h>
asm (
" .pushsection .text, \"ax\", @progbits\n"
" .type my_tramp1, @function\n"
" .globl my_tramp1\n"
" my_tramp1:\n"
" addi sp,sp,-3*"SZREG"\n"
" "REG_S" a0,0*"SZREG"(sp)\n"
" "REG_S" t0,1*"SZREG"(sp)\n"
" "REG_S" ra,2*"SZREG"(sp)\n"
" mv a0,t0\n"
" call my_direct_func1\n"
" "REG_L" a0,0*"SZREG"(sp)\n"
" "REG_L" t0,1*"SZREG"(sp)\n"
" "REG_L" ra,2*"SZREG"(sp)\n"
" addi sp,sp,3*"SZREG"\n"
" jr t0\n"
" .size my_tramp1, .-my_tramp1\n"
" .type my_tramp2, @function\n"
" .globl my_tramp2\n"
" my_tramp2:\n"
" addi sp,sp,-3*"SZREG"\n"
" "REG_S" a0,0*"SZREG"(sp)\n"
" "REG_S" t0,1*"SZREG"(sp)\n"
" "REG_S" ra,2*"SZREG"(sp)\n"
" mv a0,t0\n"
" call my_direct_func2\n"
" "REG_L" a0,0*"SZREG"(sp)\n"
" "REG_L" t0,1*"SZREG"(sp)\n"
" "REG_L" ra,2*"SZREG"(sp)\n"
" addi sp,sp,3*"SZREG"\n"
" jr t0\n"
" .size my_tramp2, .-my_tramp2\n"
" .popsection\n"
);
#endif /* CONFIG_RISCV */
#ifdef CONFIG_X86_64
#include <asm/ibt.h>
samples/ftrace/ftrace-direct-multi.c
+25
View File
@@ -17,6 +17,31 @@ void my_direct_func(unsigned long ip)
extern void my_tramp(void *);
#ifdef CONFIG_RISCV
#include <asm/asm.h>
asm (
" .pushsection .text, \"ax\", @progbits\n"
" .type my_tramp, @function\n"
" .globl my_tramp\n"
" my_tramp:\n"
" addi sp,sp,-3*"SZREG"\n"
" "REG_S" a0,0*"SZREG"(sp)\n"
" "REG_S" t0,1*"SZREG"(sp)\n"
" "REG_S" ra,2*"SZREG"(sp)\n"
" mv a0,t0\n"
" call my_direct_func\n"
" "REG_L" a0,0*"SZREG"(sp)\n"
" "REG_L" t0,1*"SZREG"(sp)\n"
" "REG_L" ra,2*"SZREG"(sp)\n"
" addi sp,sp,3*"SZREG"\n"
" jr t0\n"
" .size my_tramp, .-my_tramp\n"
" .popsection\n"
);
#endif /* CONFIG_RISCV */
#ifdef CONFIG_X86_64
#include <asm/ibt.h>
samples/ftrace/ftrace-direct-too.c
+28
View File
@@ -19,6 +19,34 @@ void my_direct_func(struct vm_area_struct *vma, unsigned long address,
extern void my_tramp(void *);
#ifdef CONFIG_RISCV
#include <asm/asm.h>
asm (
" .pushsection .text, \"ax\", @progbits\n"
" .type my_tramp, @function\n"
" .globl my_tramp\n"
" my_tramp:\n"
" addi sp,sp,-5*"SZREG"\n"
" "REG_S" a0,0*"SZREG"(sp)\n"
" "REG_S" a1,1*"SZREG"(sp)\n"
" "REG_S" a2,2*"SZREG"(sp)\n"
" "REG_S" t0,3*"SZREG"(sp)\n"
" "REG_S" ra,4*"SZREG"(sp)\n"
" call my_direct_func\n"
" "REG_L" a0,0*"SZREG"(sp)\n"
" "REG_L" a1,1*"SZREG"(sp)\n"
" "REG_L" a2,2*"SZREG"(sp)\n"
" "REG_L" t0,3*"SZREG"(sp)\n"
" "REG_L" ra,4*"SZREG"(sp)\n"
" addi sp,sp,5*"SZREG"\n"
" jr t0\n"
" .size my_tramp, .-my_tramp\n"
" .popsection\n"
);
#endif /* CONFIG_RISCV */
#ifdef CONFIG_X86_64
#include <asm/ibt.h>
samples/ftrace/ftrace-direct.c
+24
View File
@@ -16,6 +16,30 @@ void my_direct_func(struct task_struct *p)
extern void my_tramp(void *);
#ifdef CONFIG_RISCV
#include <asm/asm.h>
asm (
" .pushsection .text, \"ax\", @progbits\n"
" .type my_tramp, @function\n"
" .globl my_tramp\n"
" my_tramp:\n"
" addi sp,sp,-3*"SZREG"\n"
" "REG_S" a0,0*"SZREG"(sp)\n"
" "REG_S" t0,1*"SZREG"(sp)\n"
" "REG_S" ra,2*"SZREG"(sp)\n"
" call my_direct_func\n"
" "REG_L" a0,0*"SZREG"(sp)\n"
" "REG_L" t0,1*"SZREG"(sp)\n"
" "REG_L" ra,2*"SZREG"(sp)\n"
" addi sp,sp,3*"SZREG"\n"
" jr t0\n"
" .size my_tramp, .-my_tramp\n"
" .popsection\n"
);
#endif /* CONFIG_RISCV */
#ifdef CONFIG_X86_64
#include <asm/ibt.h>