A few clk driver fixes for Samsung and Qualcomm clk drivers

- Suspend on Google GS101 crashes when trying to save some clk
    registers that we shouldn't be saving so we don't do that anymore
 
  - The PLL lock time was wrong on the Tesla FSD which could lead to the
    PLL never locking
 
  - Qualcomm's display clk controller on SM8750 was trying to change the
    frequency of a parent clk for the DSI device when it should have
    stopped and adjusted the divider. The failure is that the clk
    frequency was half what was expected, leading to broken display.
 -----BEGIN PGP SIGNATURE-----
 
 iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmfTfQYRHHNib3lkQGtl
 cm5lbC5vcmcACgkQrQKIl8bklSW2YBAArHpBcdJKRhm+8QO1KDSR0wB09t/nxbTY
 MUsGh1hnPKaPXHWgQO6uwb6jM/Zw+bNabhmo2DhGn4tT9dRHH9CD3JQ2KNYybC0R
 /VCxd0M8Smr4DZAWd0F0VQPIbRO72eGI9jBT8mg59RJGmslNkThkBBBDXB5FNoyN
 X0FZCOY4qbNtI+kJL28CdTFTIgESGBWJKjYVX3GUbKyZGL2z8RwY9OziqQQIeSqV
 AAypiMgLw9gTPz+wlDx0z04ulehe0xJcyV9+69pIpdGlio4SgL+kfSvgcVttAPqY
 /h4ZXBL/FWUNhOhyo4CmU+kWyxD81sqvHmBqCksSVuH+Y0w3SQ9KDREiv2nuIc5K
 TVOkjNJk0Ts6XtIrm8E8r9WNed9tWZfOZPLAfUt1PUVzXWQR9Hnat+jiETKXWbor
 pEQR8vNxFq7z5i4vlytMu1FN1/3N9G+ppB+c/GhImV33IWnybzVaep/+wjj0Pdw+
 bxSRhcHsjBJfEp+PCzzJbXj5AY0ozWy5hoENtX1uJCesrE/JLMErFx2hQkIXD7WI
 9d20Nf23OngietozL77NCQ46KkqGij2TyhtHm3apiPK7wEjNmQbBFwU6i0Yjfyf7
 BtdMGbxQ6s5ny54GbOrXte+jol47njOQGL2BBUp0v6lAIXzLY2E8pStNYU1D8Icw
 o5WH0PPlyt8=
 =bKlG
 -----END PGP SIGNATURE-----

Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk fixes from Stephen Boyd:
 "A few clk driver fixes for Samsung and Qualcomm clk drivers:

   - Suspend on Google GS101 crashes when trying to save some clk
     registers that we shouldn't be saving so we don't do that anymore

   - The PLL lock time was wrong on the Tesla FSD which could lead to
     the PLL never locking

   - Qualcomm's display clk controller on SM8750 was trying to change
     the frequency of a parent clk for the DSI device when it should
     have stopped and adjusted the divider. The failure is that the clk
     frequency was half what was expected, leading to broken display"

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: samsung: update PLL locktime for PLL142XX used on FSD platform
  clk: samsung: gs101: fix synchronous external abort in samsung_clk_save()
  clk: qcom: dispcc-sm8750: Drop incorrect CLK_SET_RATE_PARENT on byte intf parent

drivers/clk/qcom/dispcc-sm8750.c

@@ -827,7 +827,6 @@ static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
 			&disp_cc_mdss_byte0_clk_src.clkr.hw,
 		},
 		.num_parents = 1,
-		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_regmap_div_ops,
 	},
 };
@@ -842,7 +841,6 @@ static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = {
 			&disp_cc_mdss_byte1_clk_src.clkr.hw,
 		},
 		.num_parents = 1,
-		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_regmap_div_ops,
 	},
 };

drivers/clk/samsung/clk-gs101.c

@@ -382,17 +382,9 @@ static const unsigned long cmu_top_clk_regs[] __initconst = {
 	EARLY_WAKEUP_DPU_DEST,
 	EARLY_WAKEUP_CSIS_DEST,
 	EARLY_WAKEUP_SW_TRIG_APM,
-	EARLY_WAKEUP_SW_TRIG_APM_SET,
-	EARLY_WAKEUP_SW_TRIG_APM_CLEAR,
 	EARLY_WAKEUP_SW_TRIG_CLUSTER0,
-	EARLY_WAKEUP_SW_TRIG_CLUSTER0_SET,
-	EARLY_WAKEUP_SW_TRIG_CLUSTER0_CLEAR,
 	EARLY_WAKEUP_SW_TRIG_DPU,
-	EARLY_WAKEUP_SW_TRIG_DPU_SET,
-	EARLY_WAKEUP_SW_TRIG_DPU_CLEAR,
 	EARLY_WAKEUP_SW_TRIG_CSIS,
-	EARLY_WAKEUP_SW_TRIG_CSIS_SET,
-	EARLY_WAKEUP_SW_TRIG_CSIS_CLEAR,
 	CLK_CON_MUX_MUX_CLKCMU_BO_BUS,
 	CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS,
 	CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS,

drivers/clk/samsung/clk-pll.c

@@ -206,6 +206,7 @@ static const struct clk_ops samsung_pll3000_clk_ops = {
  */
 /* Maximum lock time can be 270 * PDIV cycles */
 #define PLL35XX_LOCK_FACTOR	(270)
+#define PLL142XX_LOCK_FACTOR	(150)
 
 #define PLL35XX_MDIV_MASK       (0x3FF)
 #define PLL35XX_PDIV_MASK       (0x3F)
@@ -272,7 +273,11 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
 	}
 
 	/* Set PLL lock time. */
-	writel_relaxed(rate->pdiv * PLL35XX_LOCK_FACTOR,
+	if (pll->type == pll_142xx)
+		writel_relaxed(rate->pdiv * PLL142XX_LOCK_FACTOR,
+			pll->lock_reg);
+	else
+		writel_relaxed(rate->pdiv * PLL35XX_LOCK_FACTOR,
 			pll->lock_reg);
 
 	/* Change PLL PMS values */