From e18601f84a05c1310cf2bfbdbcbc5f9fd4a4890c Mon Sep 17 00:00:00 2001 From: Heinrich Toews Date: Tue, 17 Feb 2026 12:22:47 +0100 Subject: [PATCH] spi: spi-cadence-quadspi: add missing octal str init Signed-off-by: Heinrich Toews --- drivers/mtd/spi-nor/everspin.c | 101 ++++++++++++++++++++++++++++++--- 1 file changed, 94 insertions(+), 7 deletions(-) diff --git a/drivers/mtd/spi-nor/everspin.c b/drivers/mtd/spi-nor/everspin.c index d18d23ee7c9e..25ab621d6470 100644 --- a/drivers/mtd/spi-nor/everspin.c +++ b/drivers/mtd/spi-nor/everspin.c @@ -5,9 +5,95 @@ */ #include - #include "core.h" +/* Opcodes und Register-Definitionen */ +#define SPINOR_OP_EVERSPIN_WRAR 0x71 /* Write Any Register */ +#define SPINOR_OP_EVERSPIN_RDAR 0x65 /* Read Any Register */ +#define SPINOR_REG_EVERSPIN_CFR1V 0x00800002 /* Volatile CFR1 Adresse */ +#define EVERSPIN_OCTAL_STR_ENABLE 0x01 /* Wert für Octal STR Modus */ + +/** + * everspin_mram_write_reg - Hilfsfunktion zum Schreiben von Registern + */ +static int everspin_mram_write_reg(struct spi_nor *nor, u32 addr, u8 val) +{ + struct spi_mem_op op = + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_EVERSPIN_WRAR, 1), + SPI_MEM_OP_ADDR(3, addr, 1), + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_DATA_OUT(1, &val, 1)); + + return spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); +} + +static void everspin_mram_default_init(struct spi_nor *nor) +{ + struct spi_mem_op op; + u8 sr1; + int ret; + + dev_info(nor->dev, "Starte Everspin MRAM Initialisierung (STR Octal)...\n"); + + /* 1. Status Register 1 (SR1) auslesen zur Diagnose der BP-Bits */ + op = (struct spi_mem_op) + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR, 1), + SPI_MEM_OP_NO_ADDR, + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_DATA_IN(1, &sr1, 1)); + + ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); + if (ret) { + dev_err(nor->dev, "Fehler beim Lesen des SR1 Registers (%d)\n", ret); + } else { + u8 bp_bits = (sr1 & GENMASK(5, 2)) >> 2; + dev_info(nor->dev, "SR1: 0x%02x | BP-Bits: 0x%x (0 = kein Schutz)\n", sr1, bp_bits); + if (bp_bits) + dev_warn(nor->dev, "Hardware-Schreibschutz (BP-Bits) aktiv!\n"); + } + + /* 2. Umschalten in den Octal Modus via CFR1V */ + dev_info(nor->dev, "Schalte CFR1V auf Octal STR (Adresse 0x%x)...\n", SPINOR_REG_EVERSPIN_CFR1V); + ret = everspin_mram_write_reg(nor, SPINOR_REG_EVERSPIN_CFR1V, EVERSPIN_OCTAL_STR_ENABLE); + if (ret) + dev_err(nor->dev, "Fehler beim Schreiben des CFR1V Modus-Registers (%d)\n", ret); + else + dev_info(nor->dev, "CFR1V erfolgreich auf Octal STR gesetzt.\n"); + + /* 3. Kernel-Parameter synchronisieren */ + nor->cmd_ext_type = SPI_NOR_EXT_REPEAT; + nor->params->rdsr_dummy = 8; + nor->params->rdsr_addr_nbytes = 0; + nor->params->addr_nbytes = 4; + nor->flags &= ~SNOR_F_HAS_16BIT_SR; + nor->params->quad_enable = NULL; + + dev_info(nor->dev, "Standard-Parameter für OSPI-Controller gesetzt.\n"); +} + +static int everspin_mram_late_init(struct spi_nor *nor) +{ + dev_info(nor->dev, "Konfiguriere Octal Opcodes für Read/Write...\n"); + + /* Read Settings: 1-8-8 STR */ + nor->params->hwcaps.mask |= SNOR_HWCAPS_READ_1_8_8; + spi_nor_set_read_settings(&nor->params->reads[SNOR_CMD_READ_1_8_8], + 0, 8, SPINOR_OP_READ_1_8_8, SNOR_PROTO_1_8_8); + + /* Write Settings: 1-8-8 STR */ + nor->params->hwcaps.mask |= SNOR_HWCAPS_PP_1_8_8; + spi_nor_set_pp_settings(&nor->params->page_programs[SNOR_CMD_PP_1_8_8], + SPINOR_OP_PP_1_8_8, SNOR_PROTO_1_8_8); + + dev_info(nor->dev, "Everspin MRAM erfolgreich im Octal-Modus initialisiert.\n"); + return 0; +} + +static const struct spi_nor_fixups everspin_mram_fixups = { + .default_init = everspin_mram_default_init, + .late_init = everspin_mram_late_init, +}; + static const struct flash_info everspin_nor_parts[] = { /* Everspin */ { "mr25h128", CAT25_INFO(16 * 1024, 1, 256, 2) }, @@ -19,22 +105,23 @@ static const struct flash_info everspin_nor_parts[] = { static const struct flash_info everspin_mram_parts[] = { /* Everspin */ { "em256lx", INFO(0x6bbb19, 0, 32 * 1024 * 1024, 1) - FLAGS(SPI_NOR_NO_ERASE) + FLAGS(SPI_NOR_NO_ERASE) }, { "em128lx", INFO(0x6bbb18, 0, 16 * 1024 * 1024, 1) - FLAGS(SPI_NOR_NO_ERASE) + FLAGS(SPI_NOR_NO_ERASE) }, { "em064lx", INFO(0x6bbb17, 0, 8 * 1024 * 1024, 1) - FLAGS(SPI_NOR_NO_ERASE) + FLAGS(SPI_NOR_NO_ERASE) }, { "em032lx", INFO(0x6bbb16, 0, 4 * 1024 * 1024, 1) - FLAGS(SPI_NOR_NO_ERASE) + FLAGS(SPI_NOR_NO_ERASE) }, { "em016lx", INFO(0x6bbb15, 0, 2 * 1024 * 1024, 1) - FLAGS(SPI_NOR_NO_ERASE) + FLAGS(SPI_NOR_NO_ERASE) }, { "em008lx", INFO(0x6bbb14, 0, 1 * 1024 * 1024, 1) - FLAGS(SPI_NOR_NO_ERASE) + FLAGS(SPI_NOR_NO_ERASE) + .fixups = &everspin_mram_fixups, }, };