From df1a7c2ca7202b8d758df0c20548d73827758dfb Mon Sep 17 00:00:00 2001 From: Heinrich Toews Date: Fri, 19 Dec 2025 11:17:23 +0100 Subject: [PATCH] spi: cadence-qspi: fix a wrong DTR/wr_completion handling In case of a DTR (double transfer rate) the controller seems to have a problem to handle dummy bytes correctly while do a busy wait for write completion. The code up to this point was disabling direct-mode if write completion is enabled and is assuming that DTR is enabled. During wirtes direct mode is only triggered if DTR is disabled. This is configuration mismatch in case of STR and wr_completion enabled. This commit fixes this behaviour and disables direct-mode writes only if both DTR and wr_completion is enabled. Signed-off-by: Heinrich Toews --- drivers/spi/spi-cadence-quadspi.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index bf9b816637d0..ca56b5dbca3f 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -992,6 +992,9 @@ static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata, reg = readl(reg_base + CQSPI_REG_WR_COMPLETION_CTRL); reg |= CQSPI_REG_WR_DISABLE_AUTO_POLL; writel(reg, reg_base + CQSPI_REG_WR_COMPLETION_CTRL); + } + + if (op->cmd.dtr && cqspi->wr_completion) { /* * DAC mode require auto polling as flash needs to be polled * for write completion in case of bubble in SPI transaction @@ -1274,7 +1277,7 @@ static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata, * mode. So, we can not use direct mode when in DTR mode for writing * data. */ - if (!op->cmd.dtr && cqspi->use_direct_mode && + if (cqspi->use_direct_mode && cqspi->use_direct_mode_wr && ((to + len) <= cqspi->ahb_size)) { memcpy_toio(cqspi->ahb_base + to, buf, len); return cqspi_wait_idle(cqspi);