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powerpc: Replace mfmsr instructions with load from PACA kernel_msr field

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On 64-bit, the mfmsr instruction can be quite slow, slower
than loading a field from the cache-hot PACA, which happens
to already contain the value we want in most cases.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Benjamin Herrenschmidt
2012-03-02 11:33:52 +11:00
parent 9424fabf86
commit d9ada91ae2
4 changed files with 10 additions and 15 deletions
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arch/powerpc/include/asm/exception-64s.h
+1 -1
View File
@@ -298,7 +298,7 @@ label##_hv: \
/* Exception addition: Keep interrupt state */
#define ENABLE_INTS \
mfmsr r11; \
ld r11,PACAKMSR(r13); \
ld r12,_MSR(r1); \
rlwimi r11,r12,0,MSR_EE; \
mtmsrd r11,1
arch/powerpc/include/asm/hw_irq.h
+2 -2
View File
@@ -68,8 +68,8 @@ static inline bool arch_irqs_disabled(void)
#define __hard_irq_enable() asm volatile("wrteei 1" : : : "memory");
#define __hard_irq_disable() asm volatile("wrteei 0" : : : "memory");
#else
#define __hard_irq_enable() __mtmsrd(mfmsr() | MSR_EE, 1)
#define __hard_irq_disable() __mtmsrd(mfmsr() & ~MSR_EE, 1)
#define __hard_irq_enable() __mtmsrd(local_paca->kernel_msr | MSR_EE, 1)
#define __hard_irq_disable() __mtmsrd(local_paca->kernel_msr, 1)
#endif
#define hard_irq_disable() \