drm/i915: implement WADP0ClockGatingDisable
Found in Bspec vol4h South Display Engine Registers [CPT, PPT], section "5.3.1 TRANS_CHICKEN_1—Transcoder Chicken Bits 1" v2: Make it compile. Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@@ -3824,6 +3824,10 @@
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#define TRANS_6BPC (2<<5)
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#define TRANS_6BPC (2<<5)
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#define TRANS_12BPC (3<<5)
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#define TRANS_12BPC (3<<5)
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#define _TRANSA_CHICKEN1 0xf0060
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#define _TRANSB_CHICKEN1 0xf1060
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#define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
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#define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4)
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#define _TRANSA_CHICKEN2 0xf0064
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#define _TRANSA_CHICKEN2 0xf0064
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#define _TRANSB_CHICKEN2 0xf1064
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#define _TRANSB_CHICKEN2 0xf1064
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#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
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#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
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@@ -3794,6 +3794,7 @@ static void ibx_init_clock_gating(struct drm_device *dev)
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static void cpt_init_clock_gating(struct drm_device *dev)
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static void cpt_init_clock_gating(struct drm_device *dev)
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{
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_i915_private *dev_priv = dev->dev_private;
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int pipe;
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/*
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/*
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* On Ibex Peak and Cougar Point, we need to disable clock
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* On Ibex Peak and Cougar Point, we need to disable clock
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@@ -3803,6 +3804,11 @@ static void cpt_init_clock_gating(struct drm_device *dev)
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I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
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I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
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I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
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I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
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DPLS_EDP_PPS_FIX_DIS);
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DPLS_EDP_PPS_FIX_DIS);
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/* WADP0ClockGatingDisable */
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for_each_pipe(pipe) {
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I915_WRITE(TRANS_CHICKEN1(pipe),
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TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
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}
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}
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}
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void intel_init_clock_gating(struct drm_device *dev)
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void intel_init_clock_gating(struct drm_device *dev)
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