From 3b003f5a7f73a618711acc203bb748659677b8fa Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 23 Oct 2024 18:02:52 -0400 Subject: [PATCH 01/84] arm64: dts: imx8mq-librem5: remove undocument property 'extcon' for usb-pd@3f Remove undocment property 'extcon' for usb-pd@3f to fix below CHECK_DTBS warnings: arch/arm64/boot/dts/freescale/imx8mq-librem5-r2.dtb: usb-pd@3f: 'extcon' does not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/usb/ti,tps6598x.yaml# Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index bb37a32ce461..c19ffa8e8a79 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -794,7 +794,6 @@ interrupt-parent = <&gpio1>; interrupts = <10 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "irq"; - extcon = <&usb3_phy0>; wakeup-source; connector { From 0418189d27693bc3206032f500856fa1f62a2fe9 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Tue, 29 Oct 2024 11:26:13 -0400 Subject: [PATCH 02/84] arm64: dts: imx8qm-mek: add audio-codec cs42888 and related nodes Add audio-codec cs42888, enable esai0 and asrc0. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 80 ++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts index 50fd3370f7dc..5096ca8d7d1c 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -155,6 +155,13 @@ enable-active-high; }; + reg_audio: regulator-audio { + compatible = "regulator-fixed"; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + reg_fec2_supply: regulator-fec2-nvcc { compatible = "regulator-fixed"; regulator-name = "fec2_nvcc"; @@ -244,6 +251,26 @@ }; }; + sound-cs42888 { + compatible = "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + audio-cpu = <&esai0>; + audio-codec = <&cs42888>; + audio-asrc = <&asrc0>; + audio-routing = "Line Out Jack", "AOUT1L", + "Line Out Jack", "AOUT1R", + "Line Out Jack", "AOUT2L", + "Line Out Jack", "AOUT2R", + "Line Out Jack", "AOUT3L", + "Line Out Jack", "AOUT3R", + "Line Out Jack", "AOUT4L", + "Line Out Jack", "AOUT4R", + "AIN1L", "Line In Jack", + "AIN1R", "Line In Jack", + "AIN2L", "Line In Jack", + "AIN2R", "Line In Jack"; + }; + sound-wm8960 { compatible = "fsl,imx-audio-wm8960"; model = "wm8960-audio"; @@ -322,12 +349,44 @@ gpio-controller; #gpio-cells = <2>; }; + + cs42888: audio-codec@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cs42888_reset>; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + reset-gpios = <&lsio_gpio4 25 GPIO_ACTIVE_LOW>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg IMX_LPCG_CLK_0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + }; }; &cm41_intmux { status = "okay"; }; +&esai0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&esai0_lpcg IMX_LPCG_CLK_4>; + assigned-clock-parents = <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; + status = "okay"; +}; + &hsio_phy { fsl,hsio-cfg = "pciea-pcieb-sata"; fsl,refclk-pad-mode = "input"; @@ -718,6 +777,12 @@ >; }; + pinctrl_cs42888_reset: cs42888_resetgrp { + fsl,pins = < + IMX8QM_QSPI1A_DATA1_LSIO_GPIO4_IO25 0x0600004c + >; + }; + pinctrl_i2c0: i2c0grp { fsl,pins = < IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0x06000021 @@ -752,6 +817,21 @@ >; }; + pinctrl_esai0: esai0grp { + fsl,pins = < + IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR 0xc6000040 + IMX8QM_ESAI0_FST_AUD_ESAI0_FST 0xc6000040 + IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc6000040 + IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc6000040 + IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0 0xc6000040 + IMX8QM_ESAI0_TX1_AUD_ESAI0_TX1 0xc6000040 + IMX8QM_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 0xc6000040 + IMX8QM_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 0xc6000040 + IMX8QM_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 0xc6000040 + IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc6000040 + >; + }; + pinctrl_fec1: fec1grp { fsl,pins = < IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020 From 8e2fae4e287c3f4f9e1f7541250050eb29036f9d Mon Sep 17 00:00:00 2001 From: Xu Yang Date: Wed, 4 Dec 2024 13:09:06 +0800 Subject: [PATCH 03/84] arm64: dts: imx95: add usb3 related nodes Add usb3 phy and controller nodes for imx95. Signed-off-by: Xu Yang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx95.dtsi | 42 ++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index 6b8470cb3461..0b64a1df3c7a 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -1537,6 +1537,48 @@ }; }; + usb3: usb@4c010010 { + compatible = "fsl,imx95-dwc3", "fsl,imx8mp-dwc3"; + reg = <0x0 0x4c010010 0x0 0x04>, + <0x0 0x4c1f0000 0x0 0x20>; + clocks = <&scmi_clk IMX95_CLK_HSIO>, + <&scmi_clk IMX95_CLK_32K>; + clock-names = "hsio", "suspend"; + interrupts = ; + #address-cells = <2>; + #size-cells = <2>; + ranges; + power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; + dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; + status = "disabled"; + + usb3_dwc3: usb@4c100000 { + compatible = "snps,dwc3"; + reg = <0x0 0x4c100000 0x0 0x10000>; + clocks = <&scmi_clk IMX95_CLK_HSIO>, + <&scmi_clk IMX95_CLK_24M>, + <&scmi_clk IMX95_CLK_32K>; + clock-names = "bus_early", "ref", "suspend"; + interrupts = ; + phys = <&usb3_phy>, <&usb3_phy>; + phy-names = "usb2-phy", "usb3-phy"; + snps,gfladj-refclk-lpm-sel-quirk; + snps,parkmode-disable-ss-quirk; + iommus = <&smmu 0xe>; + }; + }; + + usb3_phy: phy@4c1f0040 { + compatible = "fsl,imx95-usb-phy", "fsl,imx8mp-usb-phy"; + reg = <0x0 0x4c1f0040 0x0 0x40>, + <0x0 0x4c1fc000 0x0 0x100>; + clocks = <&scmi_clk IMX95_CLK_HSIO>; + clock-names = "phy"; + #phy-cells = <0>; + power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; + status = "disabled"; + }; + pcie0: pcie@4c300000 { compatible = "fsl,imx95-pcie"; reg = <0 0x4c300000 0 0x10000>, From 18e5ff7aabfd7616504648473fb983a468e21f84 Mon Sep 17 00:00:00 2001 From: Xu Yang Date: Wed, 4 Dec 2024 13:09:07 +0800 Subject: [PATCH 04/84] arm64: dts: imx95-19x19-evk: add typec nodes and enable usb3 node This board has one Type-C port which has USB3 capability. This will add typec nodes and enable usb3 node. Signed-off-by: Xu Yang Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx95-19x19-evk.dts | 83 +++++++++++++++++++ 1 file changed, 83 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts index 8bc066c3760c..25ac331f0318 100644 --- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts @@ -6,6 +6,7 @@ /dts-v1/; #include +#include #include "imx95.dtsi" #define FALLING_EDGE 1 @@ -317,6 +318,48 @@ interrupt-parent = <&gpio5>; interrupts = <16 IRQ_TYPE_LEVEL_LOW>; }; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x50>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + interrupt-parent = <&gpio5>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + + typec_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <0>; + self-powered; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec_con_hs: endpoint { + remote-endpoint = <&usb3_data_hs>; + }; + }; + + port@1 { + reg = <1>; + + typec_con_ss: endpoint { + remote-endpoint = <&usb3_data_ss>; + }; + }; + }; + }; + }; }; &lpuart1 { @@ -418,6 +461,40 @@ status = "okay"; }; +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + role-switch-default-mode = "peripheral"; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + status = "okay"; + + port { + usb3_data_hs: endpoint { + remote-endpoint = <&typec_con_hs>; + }; + }; +}; + +&usb3_phy { + fsl,phy-tx-preemp-amp-tune-microamp = <600>; + orientation-switch; + status = "okay"; + + port { + usb3_data_ss: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; +}; + &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; pinctrl-0 = <&pinctrl_usdhc1>; @@ -676,6 +753,12 @@ >; }; + pinctrl_typec: typecgrp { + fsl,pins = < + IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x31e + >; + }; + pinctrl_usdhc2_gpio: usdhc2gpiogrp { fsl,pins = < IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e From 8472751c4d96b558d60d0f6aede6b24b64bcb3c9 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Wed, 18 Dec 2024 16:27:30 +0100 Subject: [PATCH 05/84] arm64: dts: imx8mm-kontron: Add support for reading SD_VSEL signal This fixes the LDO5 regulator handling of the pca9450 driver by taking the status of the SD_VSEL into account to determine which configuration register is used for the voltage setting. Even without this change there is no functional issue, as the code for switching the voltage in sdhci.c currently switches both, the VSELECT/SD_VSEL signal and the regulator voltage at the same time and doesn't run into an invalid corner case. We should still make sure, that we always use the correct register when controlling the regulator. At least in U-Boot this fixes an actual bug where the wrong IO voltage is used and it makes sure that the correct voltage can be read from sysfs. Signed-off-by: Frieder Schrempf Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts | 10 +++++++--- .../arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi | 7 ++++--- 2 files changed, 11 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts index a8ef4fba16a9..d16490d87687 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts @@ -254,6 +254,10 @@ status = "okay"; }; +®_nvcc_sd { + sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; @@ -454,7 +458,7 @@ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x40000d0 >; }; @@ -467,7 +471,7 @@ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x40000d0 >; }; @@ -480,7 +484,7 @@ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x40000d0 >; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi index 663ae52b4852..d45542965230 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi @@ -342,6 +342,7 @@ regulator-name = "NVCC_SD (LDO5)"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; + sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; }; }; }; @@ -794,7 +795,7 @@ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 /* SDIO_A_D2 */ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 /* SDIO_A_D3 */ MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 /* SDIO_A_WP */ - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x40000090 >; }; @@ -807,7 +808,7 @@ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 /* SDIO_A_D2 */ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 /* SDIO_A_D3 */ MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 /* SDIO_A_WP */ - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x40000090 >; }; @@ -820,7 +821,7 @@ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 /* SDIO_A_D2 */ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 /* SDIO_A_D3 */ MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 /* SDIO_A_WP */ - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x40000090 >; }; From 427ad6e2117f7161a19b0a641b167723461a822f Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Wed, 18 Dec 2024 16:27:31 +0100 Subject: [PATCH 06/84] arm64: dts: imx93-kontron: Fix SD card IO voltage control The OSM-S i.MX93 SoM doesn't have the VSELECT signal of the USDHC controller connected to the PMICs SD_VSEL input. Instead SD_VSEL is hardwired to low level. Let the driver know this in order to use the proper register for reading and writing the voltage level. This fixes SD card access with the latest hardware revision of the Kontron OSM-S i.MX93 SoM. Signed-off-by: Frieder Schrempf Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi b/arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi index 47c1363a2f99..119a16207059 100644 --- a/arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi @@ -189,6 +189,7 @@ regulator-name = "NVCC_SD (LDO5)"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; + nxp,sd-vsel-fixed-low; }; }; }; @@ -282,6 +283,7 @@ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; vmmc-supply = <®_usdhc2_vcc>; + vqmmc-supply = <®_nvcc_sd>; cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; }; @@ -553,7 +555,6 @@ MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382 /* SDIO_A_D1 */ MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382 /* SDIO_A_D2 */ MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382 /* SDIO_A_D3 */ - MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x1d0 >; }; @@ -565,7 +566,6 @@ MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e /* SDIO_A_D1 */ MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e /* SDIO_A_D2 */ MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e /* SDIO_A_D3 */ - MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x1d0 >; }; @@ -577,7 +577,6 @@ MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe /* SDIO_A_D1 */ MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe /* SDIO_A_D2 */ MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe /* SDIO_A_D3 */ - MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x1d0 >; }; From 39e4189d9d63a0b6fc15458ce0136e99ecdfb1b8 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Wed, 18 Dec 2024 16:27:32 +0100 Subject: [PATCH 07/84] arm64: dts: imx8mp-kontron: Add support for reading SD_VSEL signal This fixes the LDO5 regulator handling of the pca9450 driver by taking the status of the SD_VSEL into account to determine which configuration register is used for the voltage setting. Even without this change there is no functional issue, as the code for switching the voltage in sdhci.c currently switches both, the VSELECT/SD_VSEL signal and the regulator voltage at the same time and doesn't run into an invalid corner case. We should still make sure, that we always use the correct register when controlling the regulator. At least in U-Boot this fixes an actual bug where the wrong IO voltage is used and it makes sure that the correct voltage can be read from sysfs. Signed-off-by: Frieder Schrempf Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-kontron-osm-s.dtsi | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-kontron-osm-s.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-kontron-osm-s.dtsi index e0e9f6f7616d..b97bfeb1c30f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-kontron-osm-s.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-kontron-osm-s.dtsi @@ -311,6 +311,7 @@ regulator-name = "NVCC_SD (LDO5)"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; + sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; }; }; }; @@ -808,7 +809,7 @@ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 /* SDIO_A_D1 */ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 /* SDIO_A_D2 */ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 /* SDIO_A_D3 */ - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x400001d0 >; }; @@ -820,7 +821,7 @@ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 /* SDIO_A_D1 */ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 /* SDIO_A_D2 */ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 /* SDIO_A_D3 */ - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x400001d0 >; }; @@ -832,7 +833,7 @@ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 /* SDIO_A_D1 */ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 /* SDIO_A_D2 */ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 /* SDIO_A_D3 */ - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x400001d0 >; }; From d19a6f79961df1c29d8b2ac93b01b96788f209fa Mon Sep 17 00:00:00 2001 From: Ahmad Fatoum Date: Mon, 6 Jan 2025 17:06:36 +0100 Subject: [PATCH 08/84] arm64: dts: imx8mp-skov: correct PMIC board limits The PMIC voltage constraints in the device tree currently describe the permissible range of the PMIC. This is unnecessary as this information already exists in the driver and wrong as it doesn't account for board-specific constraints, e.g. a 2.1V on VDD_SOC would fry the SoC and a maximum voltage of 3.4V on the VDD_3V3 rail may be unexpected across the board. Fix this by adjusting constraints to reflect the board limits. Fixes: 6d382d51d979 ("arm64: dts: freescale: Add SKOV IMX8MP CPU revB board") Signed-off-by: Ahmad Fatoum Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mp-skov-reva.dtsi | 24 +++++++++---------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi index 59813ef8e2bb..ae82166b5c26 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi @@ -247,8 +247,8 @@ reg_vdd_arm: BUCK2 { regulator-name = "VDD_ARM"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <2187500>; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; vin-supply = <®_5v_p>; regulator-boot-on; regulator-always-on; @@ -259,8 +259,8 @@ reg_vdd_3v3: BUCK4 { regulator-name = "VDD_3V3"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; vin-supply = <®_5v_p>; regulator-boot-on; regulator-always-on; @@ -268,8 +268,8 @@ reg_vdd_1v8: BUCK5 { regulator-name = "VDD_1V8"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; vin-supply = <®_5v_p>; regulator-boot-on; regulator-always-on; @@ -277,8 +277,8 @@ reg_nvcc_dram_1v1: BUCK6 { regulator-name = "NVCC_DRAM_1V1"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; vin-supply = <®_5v_p>; regulator-boot-on; regulator-always-on; @@ -286,8 +286,8 @@ reg_nvcc_snvs_1v8: LDO1 { regulator-name = "NVCC_SNVS_1V8"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; vin-supply = <®_5v_p>; regulator-boot-on; regulator-always-on; @@ -295,8 +295,8 @@ reg_vdda_1v8: LDO3 { regulator-name = "VDDA_1V8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; vin-supply = <®_5v_p>; regulator-boot-on; regulator-always-on; From 3d8ffe5702b24a0bd9d97446c0740110325f379b Mon Sep 17 00:00:00 2001 From: Ahmad Fatoum Date: Mon, 6 Jan 2025 17:06:37 +0100 Subject: [PATCH 09/84] arm64: dts: imx8mp-skov: operate CPU at 850 mV by default The Skov i.MX8MP boards are passively cooled and heatsink is specced for continuous operation at 1.2 GHz only. Short bouts of 1.6 GHz are ok, but these should be invoked intentionally, not as part of suspend/resume cycles. Therefore, configure RUN frequency as 850 mV and remove the higher voltage operating points from those permissible for suspend. Fixes: 6d382d51d979 ("arm64: dts: freescale: Add SKOV IMX8MP CPU revB board") Signed-off-by: Ahmad Fatoum Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mp-skov-reva.dtsi | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi index ae82166b5c26..7ae686d37dda 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi @@ -163,6 +163,19 @@ }; }; +/* + * Board is passively cooled and heatsink is specced for continuous operation + * at 1.2 GHz only. Short bouts of 1.6 GHz are ok, but these should be done + * intentionally, not as part of suspend/resume cycles. + */ +&{/opp-table/opp-1600000000} { + /delete-property/ opp-suspend; +}; + +&{/opp-table/opp-1800000000} { + /delete-property/ opp-suspend; +}; + &A53_0 { cpu-supply = <®_vdd_arm>; }; @@ -253,7 +266,7 @@ regulator-boot-on; regulator-always-on; regulator-ramp-delay = <3125>; - nxp,dvs-run-voltage = <950000>; + nxp,dvs-run-voltage = <850000>; nxp,dvs-standby-voltage = <850000>; }; From 68e008f256e9ebfd5d970cf03ed19742e1ffb542 Mon Sep 17 00:00:00 2001 From: Ahmad Fatoum Date: Mon, 6 Jan 2025 17:06:38 +0100 Subject: [PATCH 10/84] arm64: dts: imx8mp-skov: use I2C5 for DDC The HDMI DDC pads can be muxed either to an i.MX I2C controller or to a limited I2C controller within the Designware HDMI bridge. So far, the pads were muxed to the HDMI bridge, but the i.MX I2C controller is the better choice: - The Designware HDMI I2C controller doesn't support multi-byte requests and the Linux driver refuses[1] transfers to/from address 0x37, but these are required for display/brightness configuration, - The driver doesn't support I2C bus recovery, but some HDMI panels used with the board can be flaky and require it. As the i.MX I2C controller and driver don't have either of these limitations, let's make use of it instead. [1]: https://lore.kernel.org/all/20190722181945.244395-1-mka@chromium.org/ Signed-off-by: Ahmad Fatoum Signed-off-by: Shawn Guo --- .../dts/freescale/imx8mp-skov-revb-hdmi.dts | 26 +++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-hdmi.dts b/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-hdmi.dts index c1ca69da3cb8..206116be8166 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-hdmi.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-hdmi.dts @@ -9,12 +9,34 @@ compatible = "skov,imx8mp-skov-revb-hdmi", "fsl,imx8mp"; }; +&i2c5 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c5>; + pinctrl-1 = <&pinctrl_i2c5_gpio>; + scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + clock-frequency = <100000>; + status = "okay"; +}; + &iomuxc { pinctrl_hdmi: hdmigrp { fsl,pins = < - MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c3 - MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x1c3 MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x19 >; }; + + pinctrl_i2c5: i2c5grp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL 0x400001c2 + MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA 0x400001c2 + >; + }; + + pinctrl_i2c5_gpio: i2c5gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 0x400001c2 + MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 0x400001c2 + >; + }; }; From 507b6de306eefe1354878704739e1dd2e107485f Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Mon, 6 Jan 2025 17:06:39 +0100 Subject: [PATCH 11/84] arm64: dts: imx8mp-skov: describe HDMI display pipeline Back when this device tree was first added, there were no i.MX8MP HDMI bindings upstream yet. This has changed now, so let's use them to describe the HDMI on the imx8mp-skov-revb-hdmi board. Signed-off-by: Oleksij Rempel Signed-off-by: Ahmad Fatoum Signed-off-by: Shawn Guo --- .../dts/freescale/imx8mp-skov-revb-hdmi.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-hdmi.dts b/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-hdmi.dts index 206116be8166..32a429437cbd 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-hdmi.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-hdmi.dts @@ -9,6 +9,21 @@ compatible = "skov,imx8mp-skov-revb-hdmi", "fsl,imx8mp"; }; +&hdmi_pvi { + status = "okay"; +}; + +&hdmi_tx { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; + ddc-i2c-bus = <&i2c5>; + status = "okay"; +}; + +&hdmi_tx_phy { + status = "okay"; +}; + &i2c5 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c5>; @@ -19,6 +34,10 @@ status = "okay"; }; +&lcdif3 { + status = "okay"; +}; + &iomuxc { pinctrl_hdmi: hdmigrp { fsl,pins = < From 6e887c950cb26b555ddf274120b97ace670d7696 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Mon, 6 Jan 2025 17:06:41 +0100 Subject: [PATCH 12/84] arm64: dts: imx8mp-skov: describe LVDS display pipeline The Skov i.MX8MP LT6 device tree so far described the touch screen, but didn't describe the screen itself. Fill out these missing pieces. Signed-off-by: Oleksij Rempel Signed-off-by: Ahmad Fatoum Signed-off-by: Shawn Guo --- .../dts/freescale/imx8mp-skov-revb-lt6.dts | 60 +++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-lt6.dts b/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-lt6.dts index ccbd3abedd69..baecf768a2ee 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-lt6.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-lt6.dts @@ -8,6 +8,45 @@ model = "SKOV IMX8MP CPU revB - LT6"; compatible = "skov,imx8mp-skov-revb-lt6", "fsl,imx8mp"; + lvds-decoder { + compatible = "ti,sn65lvds822", "lvds-decoder"; + power-supply = <®_3v3>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + in_lvds1: endpoint { + data-mapping = "vesa-24"; + remote-endpoint = <&ldb_lvds_ch1>; + }; + }; + + port@1 { + reg = <1>; + + lvds_decoder_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; + + panel { + compatible = "logictechno,lttd800480070-l6wh-rt"; + backlight = <&backlight>; + power-supply = <®_tft_vcom>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds_decoder_out>; + }; + }; + }; + touchscreen { compatible = "resistive-adc-touch"; io-channels = <&adc_ts 1>, <&adc_ts 3>, <&adc_ts 4>, <&adc_ts 5>; @@ -78,6 +117,27 @@ }; }; +&lcdif2 { + status = "okay"; +}; + +&lvds_bridge { + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>, + <&clk IMX8MP_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; + /* IMX8MP_VIDEO_PLL1 = IMX8MP_CLK_MEDIA_DISP2_PIX * 2 * 7 */ + assigned-clock-rates = <0>, <462000000>; + status = "okay"; + + ports { + port@2 { + ldb_lvds_ch1: endpoint { + remote-endpoint = <&in_lvds1>; + }; + }; + }; +}; + &pwm1 { status = "okay"; }; From 4252ede53d46e945b07ea370aca07e2b3e44726e Mon Sep 17 00:00:00 2001 From: Ahmad Fatoum Date: Mon, 6 Jan 2025 17:06:42 +0100 Subject: [PATCH 13/84] arm64: dts: imx8mp-skov: configure uart1 for RS485 uart1 TX, RX and RTS signals go off the base board and to a RS485 transceiver. Describe this in the device tree. Signed-off-by: Ahmad Fatoum Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi index 7ae686d37dda..bce23d62cd27 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi @@ -404,6 +404,13 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; status = "okay"; + /* + * While there is no CTS line, the property "uart-has-rtscts" is still + * the right thing to do to enable the UART to do RS485. In RS485-Mode + * CTS isn't used anyhow and there is no dedicated property + * "uart-has-rts-but-no-cts". + */ + uart-has-rtscts; }; &uart2 { @@ -618,6 +625,8 @@ MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 MX8MP_IOMUXC_UART3_RXD__UART1_DTE_RTS 0x140 + /* CTS pin is not connected, but needed as workaround */ + MX8MP_IOMUXC_UART3_TXD__UART1_DTE_CTS 0x140 >; }; From fc8efdf8fa4d100153cbeb2892af27442b288428 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Mon, 6 Jan 2025 17:06:43 +0100 Subject: [PATCH 14/84] arm64: dts: imx8mp-skov: describe mains fail detection The main 24V regulator will toggle GPIO4_IO23 to signal imminent voltage loss. Reflect this in the DT, so the OS can take appropriate action when this happens. Signed-off-by: Oleksij Rempel Signed-off-by: Ahmad Fatoum Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi index bce23d62cd27..80d212acc0c3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi @@ -116,6 +116,11 @@ regulator-name = "24V"; regulator-min-microvolt = <24000000>; regulator-max-microvolt = <24000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg24v>; + interrupts-extended = <&gpio4 23 IRQ_TYPE_EDGE_FALLING>; + system-critical-regulator; + regulator-uv-less-critical-window-ms = <50>; }; reg_can2rs: regulator-can2rs { @@ -591,6 +596,12 @@ >; }; + pinctrl_reg24v: reg24vgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x154 + >; + }; + pinctrl_reg_vsd_3v3: regvsd3v3grp { fsl,pins = < MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 From bce3edf81c2d3cc2bd29ef6141674c0579de9f56 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Mon, 6 Jan 2025 17:06:44 +0100 Subject: [PATCH 15/84] arm64: dts: imx8mp-skov: fix phy-mode Use rgmii-rxid instead of rgmii-txid. It should have no effect here, because we have a fixed-link, but rxid reflects the board design. Signed-off-by: Oleksij Rempel Signed-off-by: Ahmad Fatoum Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi index 80d212acc0c3..a683f46fcbab 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi @@ -215,7 +215,7 @@ &eqos { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_eqos>; - phy-mode = "rgmii-txid"; + phy-mode = "rgmii-rxid"; status = "okay"; fixed-link { From 587098514a0e09f3e75d88522a57bcbb453dc2e9 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Mon, 6 Jan 2025 17:06:45 +0100 Subject: [PATCH 16/84] arm64: dts: imx8mp-skov: increase I2C clock frequency for RTC The NXP PCF85063TP RTC is capable of 400 kHz of SCL clock frequency, so use that instead of the current 100 kHz. Signed-off-by: Oleksij Rempel Signed-off-by: Ahmad Fatoum Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi index a683f46fcbab..ec7857db7bf0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi @@ -333,7 +333,7 @@ }; &i2c3 { - clock-frequency = <100000>; + clock-frequency = <400000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; From aadfff7b13d4fd83a2f597121c9243d435b33e52 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 6 Jan 2025 13:51:16 -0300 Subject: [PATCH 17/84] arm64: dts: imx8mn-bsh-smm-s2pro: Remove invalid audio codec clock According to ti,tlv320dac3100.yaml, 'clocks' is not a valid property. Remove it to fix the following dt-schema warning: Unevaluated properties are not allowed ('clocks' was unexpected) Signed-off-by: Fabio Estevam Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts index c6ad65becc97..475cbf9e0d1e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts @@ -64,7 +64,6 @@ DVDD-supply = <&buck5_reg>; reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; ai31xx-micbias-vg = ; - clocks = <&clk IMX8MN_CLK_SAI3_ROOT>; }; }; From f9893c3460593794669a62c498d554757259d5c5 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 7 Jan 2025 15:01:06 +0100 Subject: [PATCH 18/84] arm64: dts: imx8-ss-hsio: Wire up DMA IRQ for PCIe IRQ mapping is already present. Add the missing DMA interrupt. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi index 70a8aa1a6791..4bdfc15487cb 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi @@ -57,8 +57,9 @@ hsio_subsys: bus@5f000000 { ranges = <0x81000000 0 0x00000000 0x8ff80000 0 0x00010000>, <0x82000000 0 0x80000000 0x80000000 0 0x0ff00000>; #interrupt-cells = <1>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + ; + interrupt-names = "msi", "dma"; #address-cells = <3>; #size-cells = <2>; clocks = <&pcieb_lpcg IMX_LPCG_CLK_6>, From c3d79d64c0fef2e1fd98280396a633f60a5622e1 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 7 Jan 2025 15:01:07 +0100 Subject: [PATCH 19/84] arm64: dts: tqma8xx: Add vcc-supply for spi-nor (Q)SPI NOR flash is supplied by 1.8V. Add the corresponding supply. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/tqma8xx.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/tqma8xx.dtsi b/arch/arm64/boot/dts/freescale/tqma8xx.dtsi index 366912bf3d5e..86b4e2b75adb 100644 --- a/arch/arm64/boot/dts/freescale/tqma8xx.dtsi +++ b/arch/arm64/boot/dts/freescale/tqma8xx.dtsi @@ -65,6 +65,7 @@ spi-max-frequency = <66000000>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; + vcc-supply = <®_1v8>; partitions { compatible = "fixed-partitions"; From 11dcabb083f059a720c8e3f3011d0b76f8af5964 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 7 Jan 2025 15:01:08 +0100 Subject: [PATCH 20/84] arm64: dts: tqma8xx: enable jpeg encode and decode Enable jpeg encode and decode. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/tqma8xx.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/tqma8xx.dtsi b/arch/arm64/boot/dts/freescale/tqma8xx.dtsi index 86b4e2b75adb..50aa41e3b6d5 100644 --- a/arch/arm64/boot/dts/freescale/tqma8xx.dtsi +++ b/arch/arm64/boot/dts/freescale/tqma8xx.dtsi @@ -115,6 +115,15 @@ }; }; +&jpegdec { + status = "okay"; +}; + +&jpegenc { + status = "okay"; +}; + + &mu_m0 { status = "okay"; }; From c58128a8a8ddb99741769c704e6df8708377a666 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 7 Jan 2025 15:01:09 +0100 Subject: [PATCH 21/84] arm64: dts: tqma8xx: Remove GPU TODO Since commit 6196fe777513b ("arm64: dts: imx8qxp: add GPU nodes") GPUs are supported. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/tqma8xx.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/tqma8xx.dtsi b/arch/arm64/boot/dts/freescale/tqma8xx.dtsi index 50aa41e3b6d5..58693b774d4c 100644 --- a/arch/arm64/boot/dts/freescale/tqma8xx.dtsi +++ b/arch/arm64/boot/dts/freescale/tqma8xx.dtsi @@ -75,8 +75,6 @@ }; }; -/* TODO GPU */ - &i2c1 { #address-cells = <1>; #size-cells = <0>; From c63a0bfd1190573c6e857c6cc907ba8a2c68f257 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 7 Jan 2025 15:01:10 +0100 Subject: [PATCH 22/84] arm64: dts: mba8xx: Add PCIe support Add PCIe support for TQMa8Xx on MBa8Xx board. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/mba8xx.dtsi | 32 +++++++++++++++++++---- 1 file changed, 27 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/mba8xx.dtsi b/arch/arm64/boot/dts/freescale/mba8xx.dtsi index 276d1683b03b..117f65728319 100644 --- a/arch/arm64/boot/dts/freescale/mba8xx.dtsi +++ b/arch/arm64/boot/dts/freescale/mba8xx.dtsi @@ -36,6 +36,13 @@ stdout-path = &lpuart1; }; + /* Non-controllable PCIe reference clock generator */ + pcie_refclk: clock-pcie-ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -208,6 +215,12 @@ status = "okay"; }; +&hsio_phy { + fsl,hsio-cfg = "pciea-x2-pcieb"; + fsl,refclk-pad-mode = "input"; + status = "okay"; +}; + &i2c1 { tlv320aic3x04: audio-codec@18 { compatible = "ti,tlv320aic32x4"; @@ -309,7 +322,16 @@ "", "", "", ""; }; -/* TODO: Mini-PCIe */ +&pcieb { + phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; + phy-names = "pcie-phy"; + pinctrl-0 = <&pinctrl_pcieb>; + pinctrl-names = "default"; + reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; + disable-gpio = <&expander 7 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_pcie_1v5>; + status = "okay"; +}; &sai1 { assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, @@ -467,10 +489,10 @@ fsl,pins = ; }; - pinctrl_pcieb: pcieagrp { - fsl,pins = , - , - ; + pinctrl_pcieb: pciebgrp { + fsl,pins = , + , + ; }; pinctrl_reg_pcie_1v5: regpcie1v5grp { From 584b427f42520ef7172d25f78aec96452d228212 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 7 Jan 2025 15:11:15 +0100 Subject: [PATCH 23/84] arm64: dts: freescale: imx93-tqma9352-mba93xxca: sort pinctrl nodes Sort the entries alphabetically. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- .../freescale/imx93-tqma9352-mba93xxca.dts | 26 +++++++++---------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts index 8e939d716aac..861a028a1b16 100644 --- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts @@ -755,12 +755,6 @@ >; }; - pinctrl_pcf85063: pcf85063grp { - fsl,pins = < - MX93_PAD_SAI1_RXD0__GPIO1_IO14 0x1000 - >; - }; - pinctrl_mipi_csi: mipicsigrp { fsl,pins = < MX93_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 0x051e /* MCLK */ @@ -769,6 +763,12 @@ >; }; + pinctrl_pcf85063: pcf85063grp { + fsl,pins = < + MX93_PAD_SAI1_RXD0__GPIO1_IO14 0x1000 + >; + }; + pinctrl_pexp_irq: pexpirqgrp { fsl,pins = < /* HYS | FSEL_0 | No DSE */ @@ -783,13 +783,6 @@ >; }; - pinctrl_temp_sensor_som: tempsensorsomgrp { - fsl,pins = < - /* HYS | FSEL_0 | no DSE */ - MX93_PAD_SAI1_TXFS__GPIO1_IO11 0x1000 - >; - }; - pinctrl_tc9595: tc9595-grp { fsl,pins = < /* HYS | PD | FSEL_0 | no DSE */ @@ -797,6 +790,13 @@ >; }; + pinctrl_temp_sensor_som: tempsensorsomgrp { + fsl,pins = < + /* HYS | FSEL_0 | no DSE */ + MX93_PAD_SAI1_TXFS__GPIO1_IO11 0x1000 + >; + }; + pinctrl_tpm5: tpm5grp { fsl,pins = < MX93_PAD_GPIO_IO06__TPM5_CH0 0x57e From db55b909e1a575f330e41ff0a4f810c643b323fb Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 7 Jan 2025 15:11:16 +0100 Subject: [PATCH 24/84] arm64: dts: mba93xxca: Do not assert power-down pins Change the output to inactive (output-low) for active-low pins, resulting in high-voltage of power-down pins. Thus this enables the attached devices. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- .../freescale/imx93-tqma9352-mba93xxca.dts | 24 +++++++++---------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts index 861a028a1b16..b8ccc946c62d 100644 --- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts @@ -448,38 +448,38 @@ "WLAN_PERST#", "12V_EN"; /* - * Controls the WiFi card PD pin which is low active - * as power down signal. The output-high states, the signal - * is active, e.g. card is powered down + * Controls the WiFi card's low-active power down pin. + * The output-low states, the signal is inactive, + * resulting in high signal at power-down pin */ wlan-pd-hog { gpio-hog; gpios = <4 GPIO_ACTIVE_LOW>; - output-high; + output-low; line-name = "WLAN_PD#"; }; /* - * Controls the WiFi card disable pin which is low active - * as disable signal. The output-high states, the signal - * is active, e.g. card is disabled + * Controls the WiFi card's low-active disable pin. + * The output-low states, the signal is inactive, + * resulting in high signal at power-down pin */ wlan-wdisable-hog { gpio-hog; gpios = <5 GPIO_ACTIVE_LOW>; - output-high; + output-low; line-name = "WLAN_W_DISABLE#"; }; /* - * Controls the WiFi card reset pin which is low active - * as reset signal. The output-high states, the signal - * is active, e.g. card in reset + * Controls the WiFi card's reset pin. + * The output-low states, the signal is inactive, + * resulting in high signal at power-down pin */ wlan-perst-hog { gpio-hog; gpios = <6 GPIO_ACTIVE_LOW>; - output-high; + output-low; line-name = "WLAN_PERST#"; }; }; From a3bfd9e8118a86e5ce0746ce2b97923034c9e571 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 7 Jan 2025 15:11:17 +0100 Subject: [PATCH 25/84] arm64: dts: tqma9352-mba93xx[cl]a: swap ethernet aliases In mainboard schematics ENET1 is eqos and ENET2 is fec. This is reversed to standard aliases using base addresses for ordering. Adjust aliases for all mainboards accordingly. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts | 6 +++--- arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts index b8ccc946c62d..ebbac5f8d2b2 100644 --- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) /* - * Copyright (c) 2022-2023 TQ-Systems GmbH , + * Copyright (c) 2022-2024 TQ-Systems GmbH , * D-82229 Seefeld, Germany. * Author: Markus Niebel * Author: Alexander Stein @@ -26,8 +26,8 @@ aliases { eeprom0 = &eeprom0; - ethernet0 = &fec; - ethernet1 = &eqos; + ethernet0 = &eqos; + ethernet1 = &fec; rtc0 = &pcf85063; rtc1 = &bbnsm_rtc; }; diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts index 2e953a05c590..9e88c42c3d17 100644 --- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) /* - * Copyright (c) 2022-2023 TQ-Systems GmbH , + * Copyright (c) 2022-2024 TQ-Systems GmbH , * D-82229 Seefeld, Germany. * Author: Markus Niebel * Author: Alexander Stein @@ -26,8 +26,8 @@ aliases { eeprom0 = &eeprom0; - ethernet0 = &fec; - ethernet1 = &eqos; + ethernet0 = &eqos; + ethernet1 = &fec; rtc0 = &pcf85063; rtc1 = &bbnsm_rtc; }; From 0373fa645cf5db28298a45a3de6a11ceb177f4aa Mon Sep 17 00:00:00 2001 From: Chancel Liu Date: Thu, 9 Jan 2025 10:27:13 +0900 Subject: [PATCH 26/84] arm64: dts: imx8mp-evk: Complete WM8960 power supplies WM8960 has the following power supplies: - AVDD - DBVDD - DCVDD - SPKVDD1 - SPKVDD2 Add new audio regulators to reflect the schematic and complete missed power supplies. Signed-off-by: Chancel Liu Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 22 ++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 68e12a752edd..c26954e5a605 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -74,6 +74,24 @@ clock-frequency = <100000000>; }; + reg_audio_3v3: regulator-audio-3v3 { + compatible = "regulator-fixed"; + regulator-name = "audio-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_audio_1v8: regulator-audio-1v8 { + compatible = "regulator-fixed"; + regulator-name = "audio-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + reg_audio_pwr: regulator-audio-pwr { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -586,7 +604,11 @@ wlf,shared-lrclk; wlf,hp-cfg = <3 2 3>; wlf,gpio-cfg = <1 3>; + AVDD-supply = <®_audio_3v3>; + DBVDD-supply = <®_audio_1v8>; + DCVDD-supply = <®_audio_1v8>; SPKVDD1-supply = <®_audio_pwr>; + SPKVDD2-supply = <®_audio_pwr>; }; pca6416: gpio@20 { From ca0d7229e41cbdec98db016a555b9cdab48ea621 Mon Sep 17 00:00:00 2001 From: Chancel Liu Date: Thu, 9 Jan 2025 10:27:14 +0900 Subject: [PATCH 27/84] arm64: dts: imx8dxl-evk: Complete WM8960 power supplies WM8960 has the following power supplies: - AVDD - DBVDD - DCVDD - SPKVDD1 - SPKVDD2 Add new audio regulators to reflect the schematic and complete missed power supplies. Signed-off-by: Chancel Liu Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts index 6259186cd4d9..5f3b4014e152 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts @@ -191,6 +191,33 @@ enable-active-high; }; + reg_audio_5v: regulator-audio-pwr { + compatible = "regulator-fixed"; + regulator-name = "audio-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_audio_3v3: regulator-audio-3v3 { + compatible = "regulator-fixed"; + regulator-name = "audio-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_audio_1v8: regulator-audio-1v8 { + compatible = "regulator-fixed"; + regulator-name = "audio-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + bt_sco_codec: audio-codec-bt { compatible = "linux,bt-sco"; #sound-dai-cells = <1>; @@ -420,6 +447,11 @@ wlf,shared-lrclk; wlf,hp-cfg = <2 2 3>; wlf,gpio-cfg = <1 3>; + AVDD-supply = <®_audio_3v3>; + DBVDD-supply = <®_audio_1v8>; + DCVDD-supply = <®_audio_1v8>; + SPKVDD1-supply = <®_audio_5v>; + SPKVDD2-supply = <®_audio_5v>; }; }; @@ -444,6 +476,11 @@ wlf,shared-lrclk; wlf,hp-cfg = <2 2 3>; wlf,gpio-cfg = <1 3>; + AVDD-supply = <®_audio_3v3>; + DBVDD-supply = <®_audio_1v8>; + DCVDD-supply = <®_audio_1v8>; + SPKVDD1-supply = <®_audio_5v>; + SPKVDD2-supply = <®_audio_5v>; }; }; @@ -468,6 +505,11 @@ wlf,shared-lrclk; wlf,hp-cfg = <2 2 3>; wlf,gpio-cfg = <1 3>; + AVDD-supply = <®_audio_3v3>; + DBVDD-supply = <®_audio_1v8>; + DCVDD-supply = <®_audio_1v8>; + SPKVDD1-supply = <®_audio_5v>; + SPKVDD2-supply = <®_audio_5v>; }; }; From 9bad194613107e93ad8cee6a970d9d5be6e53880 Mon Sep 17 00:00:00 2001 From: Chancel Liu Date: Thu, 9 Jan 2025 10:27:15 +0900 Subject: [PATCH 28/84] arm64: dts: imx8qm-mek: Complete WM8960 power supplies WM8960 has the following power supplies: - AVDD - DBVDD - DCVDD - SPKVDD1 - SPKVDD2 Add new audio regulators to reflect the schematic and complete missed power supplies. Signed-off-by: Chancel Liu Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 32 ++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts index 5096ca8d7d1c..353f825a8ac5 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -227,6 +227,33 @@ regulator-max-microvolt = <1800000>; }; + reg_audio_5v: regulator-audio-pwr { + compatible = "regulator-fixed"; + regulator-name = "audio-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_audio_3v3: regulator-audio-3v3 { + compatible = "regulator-fixed"; + regulator-name = "audio-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_audio_1v8: regulator-audio-1v8 { + compatible = "regulator-fixed"; + regulator-name = "audio-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + bt_sco_codec: audio-codec-bt { compatible = "linux,bt-sco"; #sound-dai-cells = <1>; @@ -498,6 +525,11 @@ wlf,shared-lrclk; wlf,hp-cfg = <2 2 3>; wlf,gpio-cfg = <1 3>; + AVDD-supply = <®_audio_3v3>; + DBVDD-supply = <®_audio_1v8>; + DCVDD-supply = <®_audio_1v8>; + SPKVDD1-supply = <®_audio_5v>; + SPKVDD2-supply = <®_audio_5v>; }; }; From dc5fb736fb5224a90847c8572c12fe4f3515c63c Mon Sep 17 00:00:00 2001 From: Chancel Liu Date: Thu, 9 Jan 2025 10:27:16 +0900 Subject: [PATCH 29/84] arm64: dts: imx8qxp-mek: Complete WM8960 power supplies WM8960 has the following power supplies: - AVDD - DBVDD - DCVDD - SPKVDD1 - SPKVDD2 Add new audio regulators to reflect the schematic and complete missed power supplies. Signed-off-by: Chancel Liu Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts index be79c793213a..a669a5d500d3 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -98,6 +98,33 @@ regulator-name = "cs42888_supply"; }; + reg_audio_5v: regulator-audio-pwr { + compatible = "regulator-fixed"; + regulator-name = "audio-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_audio_3v3: regulator-audio-3v3 { + compatible = "regulator-fixed"; + regulator-name = "audio-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_audio_1v8: regulator-audio-1v8 { + compatible = "regulator-fixed"; + regulator-name = "audio-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + reg_can_en: regulator-can-en { compatible = "regulator-fixed"; regulator-max-microvolt = <3300000>; @@ -418,6 +445,11 @@ wlf,shared-lrclk; wlf,hp-cfg = <2 2 3>; wlf,gpio-cfg = <1 3>; + AVDD-supply = <®_audio_3v3>; + DBVDD-supply = <®_audio_1v8>; + DCVDD-supply = <®_audio_1v8>; + SPKVDD1-supply = <®_audio_5v>; + SPKVDD2-supply = <®_audio_5v>; }; pca6416: gpio@20 { From b2194a4cf163d205a7c7ea54775b59be69406be1 Mon Sep 17 00:00:00 2001 From: Ciprian Marian Costea Date: Mon, 13 Jan 2025 13:05:10 +0200 Subject: [PATCH 30/84] arm64: dts: s32g: add I2C[0..2] support for s32g2 and s32g3 Add I2C[0..2] for S32G2 and S32G3 SoCs. Signed-off-by: Ciprian Marian Costea Reviewed-by: Frank Li Reviewed-by: Matthias Brugger Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/s32g2.dtsi | 55 ++++++++++++++++++++++ arch/arm64/boot/dts/freescale/s32g3.dtsi | 60 ++++++++++++++++++++++++ 2 files changed, 115 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi index 7be430b78c83..beae4d5cf54e 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -333,6 +333,39 @@ status = "disabled"; }; + i2c0: i2c@401e4000 { + compatible = "nxp,s32g2-i2c"; + reg = <0x401e4000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + + i2c1: i2c@401e8000 { + compatible = "nxp,s32g2-i2c"; + reg = <0x401e8000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + + i2c2: i2c@401ec000 { + compatible = "nxp,s32g2-i2c"; + reg = <0x401ec000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + uart2: serial@402bc000 { compatible = "nxp,s32g2-linflexuart", "fsl,s32v234-linflexuart"; @@ -341,6 +374,28 @@ status = "disabled"; }; + i2c3: i2c@402d8000 { + compatible = "nxp,s32g2-i2c"; + reg = <0x402d8000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + + i2c4: i2c@402dc000 { + compatible = "nxp,s32g2-i2c"; + reg = <0x402dc000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + usdhc0: mmc@402f0000 { compatible = "nxp,s32g2-usdhc"; reg = <0x402f0000 0x1000>; diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi index 6c572ffe37ca..79b38cd8b142 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -390,6 +390,42 @@ status = "disabled"; }; + i2c0: i2c@401e4000 { + compatible = "nxp,s32g3-i2c", + "nxp,s32g2-i2c"; + reg = <0x401e4000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + + i2c1: i2c@401e8000 { + compatible = "nxp,s32g3-i2c", + "nxp,s32g2-i2c"; + reg = <0x401e8000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + + i2c2: i2c@401ec000 { + compatible = "nxp,s32g3-i2c", + "nxp,s32g2-i2c"; + reg = <0x401ec000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + uart2: serial@402bc000 { compatible = "nxp,s32g3-linflexuart", "fsl,s32v234-linflexuart"; @@ -398,6 +434,30 @@ status = "disabled"; }; + i2c3: i2c@402d8000 { + compatible = "nxp,s32g3-i2c", + "nxp,s32g2-i2c"; + reg = <0x402d8000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + + i2c4: i2c@402dc000 { + compatible = "nxp,s32g3-i2c", + "nxp,s32g2-i2c"; + reg = <0x402dc000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + usdhc0: mmc@402f0000 { compatible = "nxp,s32g3-usdhc", "nxp,s32g2-usdhc"; From 81a97afe7ccdc28b072f35f57d3cb9e5a26b962a Mon Sep 17 00:00:00 2001 From: Ciprian Marian Costea Date: Mon, 13 Jan 2025 13:05:11 +0200 Subject: [PATCH 31/84] arm64: dts: s32g: add common 'S32G-EVB' and 'S32G-RDB' board support Create common part, s32gxxa-evb.dtsi and s32gxxa-rdb.dtsi, for S32G2/S32G3 RDB2\3 and EVB G2/G3 boards to avoid copy duplicate part in boards dts file. Prepare to add other modules such as FlexCAN, DSPI easily in the future. Signed-off-by: Ciprian Marian Costea Reviewed-by: Matthias Brugger Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/s32g274a-evb.dts | 1 + .../boot/dts/freescale/s32g274a-rdb2.dts | 1 + .../boot/dts/freescale/s32g399a-rdb3.dts | 1 + .../boot/dts/freescale/s32gxxxa-evb.dtsi | 150 ++++++++++++++++++ .../boot/dts/freescale/s32gxxxa-rdb.dtsi | 122 ++++++++++++++ 5 files changed, 275 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi create mode 100644 arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi diff --git a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts index b9a119eea2b7..c4a195dd67bf 100644 --- a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts +++ b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts @@ -7,6 +7,7 @@ /dts-v1/; #include "s32g2.dtsi" +#include "s32gxxxa-evb.dtsi" / { model = "NXP S32G2 Evaluation Board (S32G-VNP-EVB)"; diff --git a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts index aaa61a8ad0da..b5ba51696f43 100644 --- a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts +++ b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts @@ -7,6 +7,7 @@ /dts-v1/; #include "s32g2.dtsi" +#include "s32gxxxa-rdb.dtsi" / { model = "NXP S32G2 Reference Design Board 2 (S32G-VNP-RDB2)"; diff --git a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts index 828e353455b5..94f531be4017 100644 --- a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts +++ b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts @@ -8,6 +8,7 @@ /dts-v1/; #include "s32g3.dtsi" +#include "s32gxxxa-rdb.dtsi" / { model = "NXP S32G3 Reference Design Board 3 (S32G-VNP-RDB3)"; diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi new file mode 100644 index 000000000000..a44eff28073a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2024 NXP + * + * Authors: Ciprian Marian Costea + * Ghennadi Procopciuc + * Larisa Grigore + */ + +&pinctrl { + i2c0_pins: i2c0-pins { + i2c0-grp0 { + pinmux = <0x101>, <0x111>; + drive-open-drain; + output-enable; + input-enable; + slew-rate = <133>; + }; + + i2c0-grp1 { + pinmux = <0x2352>, <0x2362>; + }; + }; + + i2c0_gpio_pins: i2c0-gpio-pins { + i2c0-gpio-grp0 { + pinmux = <0x100>, <0x110>; + drive-open-drain; + output-enable; + input-enable; + slew-rate = <133>; + }; + + i2c0-gpio-grp1 { + pinmux = <0x2350>, <0x2360>; + }; + }; + + i2c1_pins: i2c1-pins { + i2c1-grp0 { + pinmux = <0x131>, <0x141>; + drive-open-drain; + output-enable; + input-enable; + slew-rate = <133>; + }; + + i2c1-grp1 { + pinmux = <0x2cd2>, <0x2ce2>; + }; + }; + + i2c1_gpio_pins: i2c1-gpio-pins { + i2c1-gpio-grp0 { + pinmux = <0x130>, <0x140>; + drive-open-drain; + output-enable; + input-enable; + slew-rate = <133>; + }; + + i2c1-gpio-grp1 { + pinmux = <0x2cd0>, <0x2ce0>; + }; + }; + + i2c2_pins: i2c2-pins { + i2c2-grp0 { + pinmux = <0x151>, <0x161>; + drive-open-drain; + output-enable; + input-enable; + slew-rate = <133>; + }; + + i2c2-grp1 { + pinmux = <0x2cf2>, <0x2d02>; + }; + }; + + i2c2_gpio_pins: i2c2-gpio-pins { + i2c2-gpio-grp0 { + pinmux = <0x150>, <0x160>; + drive-open-drain; + output-enable; + input-enable; + slew-rate = <133>; + }; + + i2c2-gpio-grp1 { + pinmux = <0x2cf0>, <0x2d00>; + }; + }; + + i2c4_pins: i2c4-pins { + i2c4-grp0 { + pinmux = <0x211>, <0x222>; + drive-open-drain; + output-enable; + input-enable; + slew-rate = <133>; + }; + + i2c4-grp1 { + pinmux = <0x2d43>, <0x2d33>; + }; + }; + + i2c4_gpio_pins: i2c4-gpio-pins { + i2c4-gpio-grp0 { + pinmux = <0x210>, <0x220>; + drive-open-drain; + output-enable; + input-enable; + slew-rate = <133>; + }; + + i2c4-gpio-grp1 { + pinmux = <0x2d40>, <0x2d30>; + }; + }; +}; + +&i2c0 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c0_pins>; + pinctrl-1 = <&i2c0_gpio_pins>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c1_pins>; + pinctrl-1 = <&i2c1_gpio_pins>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c2_pins>; + pinctrl-1 = <&i2c2_gpio_pins>; + status = "okay"; +}; + +&i2c4 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c4_pins>; + pinctrl-1 = <&i2c4_gpio_pins>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi new file mode 100644 index 000000000000..91fd8dbf2224 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2024 NXP + * + * Authors: Ciprian Marian Costea + * Ghennadi Procopciuc + * Larisa Grigore + */ + +&pinctrl { + i2c0_pins: i2c0-pins { + i2c0-grp0 { + pinmux = <0x1f2>, <0x201>; + drive-open-drain; + output-enable; + input-enable; + slew-rate = <133>; + }; + + i2c0-grp1 { + pinmux = <0x2353>, <0x2363>; + }; + }; + + i2c0_gpio_pins: i2c0-gpio-pins { + i2c0-gpio-grp0 { + pinmux = <0x1f0>, <0x200>; + drive-open-drain; + output-enable; + input-enable; + slew-rate = <133>; + }; + + i2c0-gpio-grp1 { + pinmux = <0x2350>, <0x2360>; + }; + }; + + i2c2_pins: i2c2-pins { + i2c2-grp0 { + pinmux = <0x151>, <0x161>; + drive-open-drain; + output-enable; + input-enable; + slew-rate = <133>; + }; + + i2c2-grp1 { + pinmux = <0x2cf2>, <0x2d02>; + }; + }; + + i2c2_gpio_pins: i2c2-gpio-pins { + i2c2-gpio-grp0 { + pinmux = <0x2cf0>, <0x2d00>; + }; + + i2c2-gpio-grp1 { + pinmux = <0x150>, <0x160>; + drive-open-drain; + output-enable; + input-enable; + slew-rate = <133>; + }; + }; + + i2c4_pins: i2c4-pins { + i2c4-grp0 { + pinmux = <0x211>, <0x222>; + drive-open-drain; + output-enable; + input-enable; + slew-rate = <133>; + }; + + i2c4-grp1 { + pinmux = <0x2d43>, <0x2d33>; + }; + }; + + i2c4_gpio_pins: i2c4-gpio-pins { + i2c4-gpio-grp0 { + pinmux = <0x210>, <0x220>; + drive-open-drain; + output-enable; + input-enable; + slew-rate = <133>; + }; + + i2c4-gpio-grp1 { + pinmux = <0x2d40>, <0x2d30>; + }; + }; +}; + +&i2c0 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c0_pins>; + pinctrl-1 = <&i2c0_gpio_pins>; + status = "okay"; + + pcal6524: gpio-expander@22 { + compatible = "nxp,pcal6524"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c2 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c2_pins>; + pinctrl-1 = <&i2c2_gpio_pins>; + status = "okay"; +}; + +&i2c4 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c4_pins>; + pinctrl-1 = <&i2c4_gpio_pins>; + status = "okay"; +}; From 3a3eefecbf6da11a05016e42606a7c96baea7cda Mon Sep 17 00:00:00 2001 From: Ciprian Marian Costea Date: Mon, 13 Jan 2025 13:05:12 +0200 Subject: [PATCH 32/84] arm64: dts: s32g399a-rdb3: Add INA231 sensor entry over I2C4 Add INA231 current sensor for S32G399A-RDB3 boards. Signed-off-by: Ciprian Marian Costea Reviewed-by: Matthias Brugger Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts index 94f531be4017..802f543cae4a 100644 --- a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts +++ b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts @@ -40,6 +40,14 @@ status = "okay"; }; +&i2c4 { + current-sensor@40 { + compatible = "ti,ina231"; + reg = <0x40>; + shunt-resistor = <1000>; + }; +}; + &usdhc0 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc0>; From 2e662a2c3770315d6459be2df7ea39a424ace6fb Mon Sep 17 00:00:00 2001 From: Stefan Eichenberger Date: Mon, 20 Jan 2025 10:45:22 +0100 Subject: [PATCH 33/84] arm64: dts: imx8-apalis: add clock configuration for 44.1 kHz hdmi audio Currently, HDMI audio cannot play sound at a 44.1 kHz sample rate due to a clock frequency mismatch. This update resolves the issue by allowing the sai driver to change the clock parent to AUDIO_PLL_1 when the sample rate is 44.1 kHz. It also ensures that AUDIO_PLL_1 operates at the correct frequency for this configuration. Signed-off-by: Stefan Eichenberger Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8-apalis-v1.1.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi index a3fc945aea16..dbea1eefdeec 100644 --- a/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi @@ -790,6 +790,22 @@ status = "okay"; }; +/* Apalis HDMI Audio */ +&sai5 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>, + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai5_lpcg 0>; + assigned-clock-parents = <&aud_pll_div0_lpcg 0>, <&aud_rec1_lpcg 0>; + assigned-clock-rates = <0>, <0>, <786432000>, <49152000>, <12288000>, + <722534400>, <45158400>, <11289600>, <49152000>; +}; + /* TODO: Apalis SATA1 */ /* Apalis SPDIF1 */ From aabe17aec3e3440ba201657f47304602c5de886e Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 21 Jan 2025 11:30:22 +0100 Subject: [PATCH 34/84] arm64: dts: freescale: tqma8mpql: Add vcc-supply for spi-nor (Q)SPI NOR flash is supplied by 1.8V. Add the corresponding supply. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi index 336785a9fba8..68821dff875f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi @@ -49,6 +49,7 @@ spi-max-frequency = <80000000>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; + vcc-supply = <&buck5_reg>; partitions { compatible = "fixed-partitions"; From fd5186372d4d33c7a336f6ae7c50f867dafc9b35 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 21 Jan 2025 11:30:23 +0100 Subject: [PATCH 35/84] arm64: dts: freescale: tqma8mq: Add vcc-supply for spi-nor (Q)SPI NOR flash is supplied by 1.8V. Add the corresponding supply. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi index 01e5092e4c40..c92001c80f11 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi @@ -254,6 +254,7 @@ spi-max-frequency = <84000000>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; + vcc-supply = <&nvcc_1v8_reg>; partitions { compatible = "fixed-partitions"; From ea6bd2e5ecde75032c39917e294f4d021e125979 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 21 Jan 2025 11:30:24 +0100 Subject: [PATCH 36/84] arm64: dts: freescale: tqma8mqml: Add vcc-supply for spi-nor (Q)SPI NOR flash is supplied by 1.8V. Add the corresponding supply. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi index 8f58c84e14c8..b82e9790ea20 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi @@ -65,6 +65,7 @@ spi-max-frequency = <84000000>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; + vcc-supply = <&buck5_reg>; partitions { compatible = "fixed-partitions"; From b45895954039a09095d916458172a9304472f965 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 21 Jan 2025 11:30:25 +0100 Subject: [PATCH 37/84] arm64: dts: freescale: tqma8mqnl: Add vcc-supply for spi-nor (Q)SPI NOR flash is supplied by 1.8V. Add the corresponding supply. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi index e68a3fd73e17..640c41b51af9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi @@ -63,6 +63,7 @@ spi-max-frequency = <84000000>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; + vcc-supply = <&buck5_reg>; partitions { compatible = "fixed-partitions"; From b09435bc5e8b6cae443cd93d4d9206cf2bcacbe3 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Tue, 28 Jan 2025 16:15:55 -0500 Subject: [PATCH 38/84] arm64: dts: imx8-ss-hsio: fix indentation in pcie node Fix indentation in pcie node. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi index 4bdfc15487cb..577a8b112ca5 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi @@ -69,9 +69,9 @@ hsio_subsys: bus@5f000000 { bus-range = <0x00 0xff>; device_type = "pci"; interrupt-map = <0 0 0 1 &gic 0 105 4>, - <0 0 0 2 &gic 0 106 4>, - <0 0 0 3 &gic 0 107 4>, - <0 0 0 4 &gic 0 108 4>; + <0 0 0 2 &gic 0 106 4>, + <0 0 0 3 &gic 0 107 4>, + <0 0 0 4 &gic 0 108 4>; interrupt-map-mask = <0 0 0 0x7>; num-lanes = <1>; num-viewport = <4>; From d03743c5659a96ba32872ce7bb816e8927408ab3 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Tue, 28 Jan 2025 16:15:56 -0500 Subject: [PATCH 39/84] arm64: dts: imx8q: add PCIe EP for i.MX8QM and i.MX8QXP Add PCIe EP support for i.MX8QM and i.MX8QXP. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8-ss-hsio.dtsi | 19 +++++++++++++++++++ .../boot/dts/freescale/imx8qm-ss-hsio.dtsi | 19 +++++++++++++++++++ 2 files changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi index 577a8b112ca5..9b8b1380c4c2 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi @@ -80,6 +80,25 @@ hsio_subsys: bus@5f000000 { status = "disabled"; }; + pcieb_ep: pcie-ep@5f010000 { + compatible = "fsl,imx8q-pcie-ep"; + reg = <0x5f010000 0x00010000>, + <0x80000000 0x10000000>; + reg-names = "dbi", "addr_space"; + num-lanes = <1>; + interrupts = ; + interrupt-names = "dma"; + clocks = <&pcieb_lpcg IMX_LPCG_CLK_6>, + <&pcieb_lpcg IMX_LPCG_CLK_4>, + <&pcieb_lpcg IMX_LPCG_CLK_5>; + clock-names = "dbi", "mstr", "slv"; + power-domains = <&pd IMX_SC_R_PCIE_B>; + fsl,max-link-speed = <3>; + num-ib-windows = <6>; + num-ob-windows = <6>; + status = "disabled"; + }; + pcieb_lpcg: clock-controller@5f060000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x5f060000 0x10000>; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi index b1d0189a1725..d52609e4fc45 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi @@ -42,6 +42,25 @@ status = "disabled"; }; + pciea_ep: pcie-ep@5f000000 { + compatible = "fsl,imx8q-pcie-ep"; + reg = <0x5f000000 0x00010000>, + <0x40000000 0x10000000>; + reg-names = "dbi", "addr_space"; + num-lanes = <1>; + interrupts = ; + interrupt-names = "dma"; + clocks = <&pciea_lpcg IMX_LPCG_CLK_6>, + <&pciea_lpcg IMX_LPCG_CLK_4>, + <&pciea_lpcg IMX_LPCG_CLK_5>; + clock-names = "dbi", "mstr", "slv"; + power-domains = <&pd IMX_SC_R_PCIE_A>; + fsl,max-link-speed = <3>; + num-ib-windows = <6>; + num-ob-windows = <6>; + status = "disabled"; + }; + pcieb: pcie@5f010000 { compatible = "fsl,imx8q-pcie"; reg = <0x5f010000 0x10000>, From c95fc1e1f618d377ada7387d06db52ac79b7570b Mon Sep 17 00:00:00 2001 From: Frank Li Date: Tue, 28 Jan 2025 16:15:57 -0500 Subject: [PATCH 40/84] arm64: dts: imx8q: add PCIe EP overlay file for i.MX8QXP mek board Add PCIe EP overlay file for i.MX8QXP mek board to let PCI work as endpoint mode. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 4 ++++ .../dts/freescale/imx8qxp-mek-pcie-ep.dtso | 22 +++++++++++++++++++ 2 files changed, 26 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-mek-pcie-ep.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 839432153cc7..9bd32ec898c2 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -267,6 +267,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-iris.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-iris-v2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb + +imx8qxp-mek-pcie-ep-dtbs += imx8qxp-mek.dtb imx8qxp-mek-pcie-ep.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek-pcie-ep.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqp-mba8xx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-pcie-ep.dtso b/arch/arm64/boot/dts/freescale/imx8qxp-mek-pcie-ep.dtso new file mode 100644 index 000000000000..4f562eb5c5b1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-pcie-ep.dtso @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 NXP + */ + +#include + +/dts-v1/; +/plugin/; + +&pcieb { + status = "disabled"; +}; + +&pcieb_ep { + phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; + phy-names = "pcie-phy"; + pinctrl-0 = <&pinctrl_pcieb>; + pinctrl-names = "default"; + vpcie-supply = <®_pcieb>; + status = "okay"; +}; From 1ecc4dbf6acef3c2ec3e930b62f35c5e212bb998 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Tue, 28 Jan 2025 16:15:58 -0500 Subject: [PATCH 41/84] arm64: dts: imx95: add PCIe's msi-map and iommu-map property Add PCIe's msi-map and iommu-map property because i.MX95 support smmu and its. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx95.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index 0b64a1df3c7a..3af13173de4b 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -1615,6 +1615,12 @@ assigned-clock-parents = <0>, <0>, <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; + /* pcie0's Devid(BIT[7:6]) is 0x00, stream id(BIT[5:0]) is 0x10~0x17 */ + msi-map = <0x0 &its 0x10 0x1>, + <0x100 &its 0x11 0x7>; + iommu-map = <0x000 &smmu 0x10 0x1>, + <0x100 &smmu 0x11 0x7>; + iommu-map-mask = <0x1ff>; fsl,max-link-speed = <3>; status = "disabled"; }; @@ -1682,6 +1688,14 @@ assigned-clock-parents = <0>, <0>, <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; + /* pcie1's Devid(BIT[7:6]) is 0x10, stream id(BIT[5:0]) is 0x18~0x1f */ + msi-map = <0x0 &its 0x98 0x1>, + <0x100 &its 0x99 0x7>; + msi-map-mask = <0x1ff>; + /* smmu have not Devid(BIT[7:6]) */ + iommu-map = <0x000 &smmu 0x18 0x1>, + <0x100 &smmu 0x19 0x7>; + iommu-map-mask = <0x1ff>; fsl,max-link-speed = <3>; status = "disabled"; }; From 9bf72db233806a78317da1427ebcbc8c086d5e8d Mon Sep 17 00:00:00 2001 From: Larisa Grigore Date: Mon, 3 Feb 2025 10:09:19 +0200 Subject: [PATCH 42/84] arm64: dts: s32g: add the eDMA nodes Add the two eDMA nodes in the device tree in order to enable the probing of the S32G2/S32G3 eDMA driver. Signed-off-by: Larisa Grigore Reviewed-by: Frank Li Reviewed-by: Matthias Brugger Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/s32g2.dtsi | 34 ++++++++++++++++++++++++ arch/arm64/boot/dts/freescale/s32g3.dtsi | 34 ++++++++++++++++++++++++ 2 files changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi index beae4d5cf54e..e38f1f878790 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -317,6 +317,23 @@ }; }; + edma0: dma-controller@40144000 { + compatible = "nxp,s32g2-edma"; + reg = <0x40144000 0x24000>, + <0x4012c000 0x3000>, + <0x40130000 0x3000>; + #dma-cells = <2>; + dma-channels = <32>; + interrupts = , + , + ; + interrupt-names = "tx-0-15", + "tx-16-31", + "err"; + clocks = <&clks 63>, <&clks 64>; + clock-names = "dmamux0", "dmamux1"; + }; + uart0: serial@401c8000 { compatible = "nxp,s32g2-linflexuart", "fsl,s32v234-linflexuart"; @@ -366,6 +383,23 @@ status = "disabled"; }; + edma1: dma-controller@40244000 { + compatible = "nxp,s32g2-edma"; + reg = <0x40244000 0x24000>, + <0x4022c000 0x3000>, + <0x40230000 0x3000>; + #dma-cells = <2>; + dma-channels = <32>; + interrupts = , + , + ; + interrupt-names = "tx-0-15", + "tx-16-31", + "err"; + clocks = <&clks 63>, <&clks 64>; + clock-names = "dmamux0", "dmamux1"; + }; + uart2: serial@402bc000 { compatible = "nxp,s32g2-linflexuart", "fsl,s32v234-linflexuart"; diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi index 79b38cd8b142..d849edfd26f5 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -374,6 +374,23 @@ }; }; + edma0: dma-controller@40144000 { + compatible = "nxp,s32g3-edma", "nxp,s32g2-edma"; + reg = <0x40144000 0x24000>, + <0x4012c000 0x3000>, + <0x40130000 0x3000>; + #dma-cells = <2>; + dma-channels = <32>; + interrupts = , + , + ; + interrupt-names = "tx-0-15", + "tx-16-31", + "err"; + clocks = <&clks 63>, <&clks 64>; + clock-names = "dmamux0", "dmamux1"; + }; + uart0: serial@401c8000 { compatible = "nxp,s32g3-linflexuart", "fsl,s32v234-linflexuart"; @@ -426,6 +443,23 @@ status = "disabled"; }; + edma1: dma-controller@40244000 { + compatible = "nxp,s32g3-edma", "nxp,s32g2-edma"; + reg = <0x40244000 0x24000>, + <0x4022c000 0x3000>, + <0x40230000 0x3000>; + #dma-cells = <2>; + dma-channels = <32>; + interrupts = , + , + ; + interrupt-names = "tx-0-15", + "tx-16-31", + "err"; + clocks = <&clks 63>, <&clks 64>; + clock-names = "dmamux0", "dmamux1"; + }; + uart2: serial@402bc000 { compatible = "nxp,s32g3-linflexuart", "fsl,s32v234-linflexuart"; From f5b5aec0972b2f29c70957c84e72e2586e4ec2a1 Mon Sep 17 00:00:00 2001 From: Rafael Beims Date: Mon, 10 Feb 2025 09:30:50 -0300 Subject: [PATCH 43/84] arm64: dts: colibri-imx8x: Add missing gpio-line-names Add missing gpio-line-names for SODIMM_79 and SODIMM_97 Signed-off-by: Rafael Beims Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi index d5abfdb8ede2..ecb35c6b67f5 100644 --- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi @@ -295,8 +295,8 @@ "", "SODIMM_61", "SODIMM_103", - "", - "", + "SODIMM_79", + "SODIMM_97", "", "SODIMM_25", "SODIMM_27", From 4b38222c946ce936200e8d6db6a91211d11c4fa5 Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Fri, 14 Feb 2025 10:26:34 +0100 Subject: [PATCH 44/84] arm64: dts: freescale: imx8mm-verdin: Remove LVDS panel and backlight Remove LVDS panel and backlight nodes from the Verdin iMX8M Mini SoM dtsi file, those two hardware components are not part of the SoM, therefore they should not be present in this file. This is solving a dtb checker warning about panel-lvds compatible. Signed-off-by: Francesco Dolcini Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mm-verdin.dtsi | 21 ------------------- 1 file changed, 21 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi index c528594ac442..7251ad3a0017 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -18,20 +18,6 @@ rtc1 = &snvs_rtc; }; - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = <0 45 63 88 119 158 203 255>; - default-brightness-level = <4>; - /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */ - enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>; - power-supply = <®_3p3v>; - /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */ - pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>; - status = "disabled"; - }; - /* Fixed clock dedicated to SPI CAN controller */ clk40m: oscillator { compatible = "fixed-clock"; @@ -66,13 +52,6 @@ status = "disabled"; }; - panel_lvds: panel-lvds { - compatible = "panel-lvds"; - backlight = <&backlight>; - data-mapping = "vesa-24"; - status = "disabled"; - }; - /* Carrier Board Supplies */ reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; From b6af6a5af6265696a4b541c478cb9c5e96bddbba Mon Sep 17 00:00:00 2001 From: Teresa Remmet Date: Tue, 18 Feb 2025 08:41:42 +0100 Subject: [PATCH 45/84] arm64: dts: imx8mm-phycore-som: Keep LDO3 on in suspend LDO3 is also used as switch for enabling VDD_3V3_S and need to be kept on during suspend. Disabling this can lead to an unwanted reset during resume. Set LDO3 to 2,5V as the voltage should be fix. Signed-off-by: Teresa Remmet Signed-off-by: Andrej Picej Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi index 6069678244f3..7761acc5c510 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi @@ -161,11 +161,13 @@ regulator-always-on; regulator-boot-on; regulator-max-microvolt = <2500000>; - regulator-min-microvolt = <1500000>; + regulator-min-microvolt = <2500000>; regulator-name = "VCC_ENET_2V5 (LDO3)"; regulator-state-mem { - regulator-off-in-suspend; + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <2500000>; + regulator-suspend-min-microvolt = <2500000>; }; }; From 81c665eb178b0cdbcfc1985d7318ba183ad5a2a5 Mon Sep 17 00:00:00 2001 From: Andrej Picej Date: Tue, 18 Feb 2025 08:41:43 +0100 Subject: [PATCH 46/84] arm64: dts: imx8mm-phycore-som: Fix bluetooth wakeup source Not using pull-up on the host wake-up line triggers the wake up immediately after device enters suspend. Fix this by enabling internal pull-up and setting interrupt triggering on the falling edge. Signed-off-by: Andrej Picej Reviewed-by: Teresa Remmet Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts index 5eacbd9611ee..31d5c57d3c24 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts @@ -255,7 +255,7 @@ device-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; interrupt-names = "host-wakeup"; interrupt-parent = <&gpio2>; - interrupts = <9 IRQ_TYPE_EDGE_BOTH>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; max-speed = <2000000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_bt>; @@ -332,7 +332,7 @@ fsl,pins = < MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x00 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x00 - MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x00 + MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x140 >; }; From 6b03a7aeea19528230602c5ab89d2c4c73dfc638 Mon Sep 17 00:00:00 2001 From: Teresa Remmet Date: Tue, 18 Feb 2025 08:41:44 +0100 Subject: [PATCH 47/84] arm64: dts: imx8mm-phycore-som: Remove magic-packet property Remove device tree property "fsl,magic-packet" as WoL is not working on the SoM and so not required. This also saves a significant amount of power during suspend as the ethernet phy is not powered down otherwise. Signed-off-by: Teresa Remmet Signed-off-by: Andrej Picej Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi index 7761acc5c510..8de5a46512b0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi @@ -69,7 +69,6 @@ /* Ethernet */ &fec1 { - fsl,magic-packet; phy-mode = "rgmii-id"; phy-handle = <ðphy0>; pinctrl-names = "default"; From 62606c250555f220c94fdda86a530e8623d16629 Mon Sep 17 00:00:00 2001 From: Yashwanth Varakala Date: Tue, 18 Feb 2025 08:41:45 +0100 Subject: [PATCH 48/84] arm64: dts: imx8mm-phycore-som: Assign regulator for dsi to lvds bridge Add a missing voltage regulator of 1.8v to the sn65dsi83 (dsi_lvds bridge) node. Due to the absence of this regulator, a fallback dummy regulator is used and that triggers a warning message from the kernel. Assigning the appropriate regulator avoids the warning. Signed-off-by: Yashwanth Varakala Signed-off-by: Andrej Picej Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi index 8de5a46512b0..7e859c65317a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi @@ -286,6 +286,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sn65dsi83>; reg = <0x2d>; + vcc-supply = <®_vdd_1v8>; status = "disabled"; }; From d1f974697d44548f97f485d1c9d7afde51847595 Mon Sep 17 00:00:00 2001 From: Yannic Moog Date: Tue, 18 Feb 2025 08:41:46 +0100 Subject: [PATCH 49/84] arm64: dts: imx8mm-phycore-som: add descriptions to nodes Add missing EEPROM and RTC descriptions. Also use eMMC with lower-case "e". Signed-off-by: Yannic Moog Signed-off-by: Andrej Picej Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi index 7e859c65317a..cced82226c6d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi @@ -290,6 +290,7 @@ status = "disabled"; }; + /* EEPROM */ eeprom@51 { compatible = "atmel,24c32"; pagesize = <32>; @@ -297,6 +298,7 @@ vcc-supply = <®_vdd_3v3_s>; }; + /* RTC */ rv3028: rtc@52 { compatible = "microcrystal,rv3028"; interrupts = <3 IRQ_TYPE_LEVEL_LOW>; @@ -307,7 +309,7 @@ }; }; -/* EMMC */ +/* eMMC */ &usdhc3 { assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; assigned-clock-rates = <400000000>; From c290eb8afc46fed93777cefe5b1d4c298dd668f5 Mon Sep 17 00:00:00 2001 From: Yannic Moog Date: Tue, 18 Feb 2025 08:41:47 +0100 Subject: [PATCH 50/84] arm64: dts: imx8mm-phyboard-polis: add RTC description Add RTC description. Signed-off-by: Yannic Moog Signed-off-by: Andrej Picej Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts index 31d5c57d3c24..6c95257119d6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts @@ -219,6 +219,7 @@ status = "okay"; }; +/* RTC */ &rv3028 { aux-voltage-chargeable = <1>; trickle-resistor-ohms = <3000>; From ce23d2a8089432a4c3212aaafb24818073a8ceaf Mon Sep 17 00:00:00 2001 From: Andrej Picej Date: Tue, 18 Feb 2025 08:41:48 +0100 Subject: [PATCH 51/84] arm64: dts: imx8mm-phyboard-polis: Set RTC as wakeup-source RV-3028 RTC can be used to wakeup the system on phyBOARD-Polis-i.MX8MM, mark the device as wakeup source. Signed-off-by: Andrej Picej Reviewed-by: Teresa Remmet Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts index 6c95257119d6..7aaf705c7e47 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts @@ -223,6 +223,7 @@ &rv3028 { aux-voltage-chargeable = <1>; trickle-resistor-ohms = <3000>; + wakeup-source; }; &snvs_pwrkey { From 111073fc282e629bdce5b4cac22b89860f03c785 Mon Sep 17 00:00:00 2001 From: Andrej Picej Date: Tue, 18 Feb 2025 08:41:49 +0100 Subject: [PATCH 52/84] arm64: dts: imx8mm-phygate-tauri-l: Set RTC as wakeup-source RV-3028 RTC can be used to wakeup the system on phyGATE-Tauri-L-i.MX8MM, mark the device as wakeup source. Signed-off-by: Andrej Picej Reviewed-by: Teresa Remmet Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts b/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts index c3835b2d860a..c9bf4ac254bb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts @@ -217,6 +217,7 @@ &rv3028 { aux-voltage-chargeable = <1>; trickle-resistor-ohms = <3000>; + wakeup-source; }; &uart1 { From 1fcb3dc13447b944ca3892afb0ddbe4a8863a361 Mon Sep 17 00:00:00 2001 From: Yannic Moog Date: Tue, 18 Feb 2025 08:41:50 +0100 Subject: [PATCH 53/84] arm64: dts: imx8mm: move bulk of rtc properties to carrierboards Move properties from SoM's dtsi to carrierboard's dts as they are actually defined by the carrier board design. Signed-off-by: Yannic Moog Signed-off-by: Andrej Picej Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts | 10 ++++++++++ arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi | 10 ---------- .../boot/dts/freescale/imx8mm-phygate-tauri-l.dts | 10 ++++++++++ 3 files changed, 20 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts index 7aaf705c7e47..17e5dd40b5d7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts @@ -221,6 +221,10 @@ /* RTC */ &rv3028 { + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_rtc>; + pinctrl-names = "default"; aux-voltage-chargeable = <1>; trickle-resistor-ohms = <3000>; wakeup-source; @@ -410,6 +414,12 @@ >; }; + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 + >; + }; + pinctrl_tpm: tpmgrp { fsl,pins = < MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x140 diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi index cced82226c6d..672baba4c8d0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi @@ -301,10 +301,6 @@ /* RTC */ rv3028: rtc@52 { compatible = "microcrystal,rv3028"; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - interrupt-parent = <&gpio1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rtc>; reg = <0x52>; }; }; @@ -377,12 +373,6 @@ >; }; - pinctrl_rtc: rtcgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 - >; - }; - pinctrl_sn65dsi83: sn65dsi83grp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x0 diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts b/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts index c9bf4ac254bb..755cf9cacd22 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts @@ -215,6 +215,10 @@ /* RTC */ &rv3028 { + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_rtc>; + pinctrl-names = "default"; aux-voltage-chargeable = <1>; trickle-resistor-ohms = <3000>; wakeup-source; @@ -395,6 +399,12 @@ >; }; + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 + >; + }; + pinctrl_tempsense: tempsensegrp { fsl,pins = < MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x00 From f8fab2dc4885c5c7fa9d0b2fec8e963015fe87d5 Mon Sep 17 00:00:00 2001 From: Yashwanth Varakala Date: Tue, 18 Feb 2025 08:41:51 +0100 Subject: [PATCH 54/84] arm64: dts: imx8mm-phyboard-polis: Assign missing regulator for bluetooth Assign the missing regulator to the bluetooth node. Absence of this regulator triggers the warning message from kernel as driver uses a fallback dummy regulator when there is no regulator assigned. Signed-off-by: Yashwanth Varakala Signed-off-by: Andrej Picej Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts index 17e5dd40b5d7..be470cfb03d7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts @@ -266,6 +266,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_bt>; shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; + vbat-supply = <®_vcc_3v3>; vddio-supply = <®_vcc_3v3>; }; }; From 1811697151f904d11a40a907a1433160400089f6 Mon Sep 17 00:00:00 2001 From: Teresa Remmet Date: Tue, 18 Feb 2025 08:41:52 +0100 Subject: [PATCH 55/84] arm64: dts: imx8mm-phyboard-polis: Add support for PEB-AV-10 PEB-AV-10 is an Audio/Video extension module which extends phyBOARD-Polis i.MX8MM. With MIPI DSI to LVDS bridge already populated on SoM the PEB-AV-10 adds support for: - connecting 10" display, - audio with TLV320AIC and - EEPROM. Signed-off-by: Teresa Remmet Signed-off-by: Andrej Picej Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 5 + .../imx8mm-phyboard-polis-peb-av-10.dtso | 237 ++++++++++++++++++ 2 files changed, 242 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 9bd32ec898c2..32fdbcc71d08 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -122,6 +122,11 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-mx8menlo.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-nitrogen-r2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-phg.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-phyboard-polis-rdk.dtb + +imx8mm-phyboard-polis-peb-av-10-dtbs += imx8mm-phyboard-polis-rdk.dtb imx8mm-phyboard-polis-peb-av-10.dtbo + +dtb-$(CONFIG_ARCH_MXC) += imx8mm-phyboard-polis-peb-av-10.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8mm-phygate-tauri-l.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-prt8mm.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10.dtso b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10.dtso new file mode 100644 index 000000000000..840f83293452 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10.dtso @@ -0,0 +1,237 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + * Author: Teresa Remmet + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include "imx8mm-pinfunc.h" + +&{/} { + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd>; + default-brightness-level = <6>; + pwms = <&pwm4 0 50000 0>; + power-supply = <®_vdd_3v3_s>; + enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + brightness-levels= <0 4 8 16 32 64 128 255>; + }; + + panel { + compatible = "edt,etml1010g3dra"; + backlight = <&backlight>; + power-supply = <®_vcc_3v3>; + + port { + panel_in: endpoint { + remote-endpoint = <&bridge_out>; + }; + }; + }; + + reg_sound_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "VCC_1V8_Audio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_sound_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3_Analog"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + sound-peb-av-10 { + compatible = "simple-audio-card"; + simple-audio-card,name = "snd-peb-av-10"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,mclk-fs = <32>; + simple-audio-card,widgets = + "Line", "Line In", + "Speaker", "Speaker", + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Speaker", "SPOP", + "Speaker", "SPOM", + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "LINE1L", "Line In", + "LINE1R", "Line In", + "MIC3R", "Microphone Jack", + "Microphone Jack", "Mic Bias"; + + simple-audio-card,cpu { + sound-dai = <&sai5>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai = <&codec>; + clocks = <&clk IMX8MM_CLK_SAI5>; + }; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + codec: codec@18 { + compatible = "ti,tlv320aic3007"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tlv320>; + #sound-dai-cells = <0>; + reg = <0x18>; + reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; + ai3x-gpio-func = <0xd 0x0>; + ai3x-micbias-vg = <2>; + AVDD-supply = <®_sound_3v3>; + IOVDD-supply = <®_sound_3v3>; + DRVDD-supply = <®_sound_3v3>; + DVDD-supply = <®_sound_1v8>; + }; + + eeprom@57 { + compatible = "atmel,24c32"; + pagesize = <32>; + reg = <0x57>; + vcc-supply = <®_vdd_3v3_s>; + }; + + eeprom@5f { + compatible = "atmel,24c32"; + pagesize = <32>; + reg = <0x5f>; + size = <32>; + vcc-supply = <®_vdd_3v3_s>; + }; +}; + +&lcdif { + status = "okay"; +}; + +&mipi_dsi { + samsung,esc-clock-frequency = <10000000>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@1 { + reg = <1>; + dsi_out: endpoint { + remote-endpoint = <&bridge_in>; + }; + }; + }; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&sai5 { + assigned-clocks = <&clk IMX8MM_CLK_SAI5>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL2_OUT>; + assigned-clock-rates = <11289600>; + clocks = <&clk IMX8MM_CLK_SAI5_IPG>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_SAI5_ROOT>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>, + <&clk IMX8MM_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", + "pll11k"; + fsl,sai-mclk-direction-output; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai5>; + #sound-dai-cells = <0>; + status = "okay"; +}; + +&sn65dsi83 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + bridge_in: endpoint { + remote-endpoint = <&dsi_out>; + data-lanes = <1 2 3 4>; + }; + }; + + port@2 { + reg = <2>; + bridge_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&iomuxc { + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c2 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c2 + >; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1e2 + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1e2 + >; + }; + pinctrl_lcd: lcd0grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x12 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_MCLK_PWM4_OUT 0x12 + >; + }; + + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 + MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 + MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6 + >; + }; + + pinctrl_tlv320: tlv320grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x16 + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x16 + >; + }; +}; From 481bc9d5e363d089feb0589f7a5a780fa936a99c Mon Sep 17 00:00:00 2001 From: Janine Hagemann Date: Tue, 18 Feb 2025 08:41:53 +0100 Subject: [PATCH 56/84] arm64: dts: imx8mm-phyboard-polis: Add overlay for PEB-EVAL-01 Add support for the PEB-EVAL-01 expansion board for phyBOARD-Polis-i.MX8MM. Signed-off-by: Janine Hagemann Signed-off-by: Andrej Picej Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 2 + .../imx8mm-phyboard-polis-peb-eval-01.dtso | 72 +++++++++++++++++++ 2 files changed, 74 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-eval-01.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 32fdbcc71d08..b062f76dd8b7 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -124,8 +124,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-phg.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-phyboard-polis-rdk.dtb imx8mm-phyboard-polis-peb-av-10-dtbs += imx8mm-phyboard-polis-rdk.dtb imx8mm-phyboard-polis-peb-av-10.dtbo +imx8mm-phyboard-polis-peb-eval-01-dtbs += imx8mm-phyboard-polis-rdk.dtb imx8mm-phyboard-polis-peb-eval-01.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mm-phyboard-polis-peb-av-10.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-phyboard-polis-peb-eval-01.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-phygate-tauri-l.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-prt8mm.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-eval-01.dtso b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-eval-01.dtso new file mode 100644 index 000000000000..a28f51ece93b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-eval-01.dtso @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + * Author: Janine Hagemann + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include "imx8mm-pinfunc.h" + +&{/} { + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + button-0 { + label = "home"; + linux,code = ; + gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-1 { + label = "menu"; + linux,code = ; + gpios = <&gpio5 29 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + user-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_user_leds>; + + user-led1 { + gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + user-led2 { + gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + user-led3 { + gpios = <&gpio5 28 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; +}; + +&iomuxc { + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x16 + MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x16 + >; + }; + + pinctrl_user_leds: user_ledsgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x16 + MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28 0x16 + MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x16 + >; + }; +}; From 7b77622900aaacedbd354b457924379c0d6e267b Mon Sep 17 00:00:00 2001 From: Dominik Haller Date: Tue, 18 Feb 2025 08:41:54 +0100 Subject: [PATCH 57/84] arm64: dts: imx8mm-phycore-som: Add overlay for rproc Adds a devicetree overlay containing reserved memory regions used for intercore communication between A53 and M4 cores. Signed-off-by: Dominik Haller Signed-off-by: Andrej Picej Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 2 + .../dts/freescale/imx8mm-phycore-rpmsg.dtso | 58 +++++++++++++++++++ 2 files changed, 60 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-phycore-rpmsg.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index b062f76dd8b7..dc62159988b0 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -125,9 +125,11 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-phyboard-polis-rdk.dtb imx8mm-phyboard-polis-peb-av-10-dtbs += imx8mm-phyboard-polis-rdk.dtb imx8mm-phyboard-polis-peb-av-10.dtbo imx8mm-phyboard-polis-peb-eval-01-dtbs += imx8mm-phyboard-polis-rdk.dtb imx8mm-phyboard-polis-peb-eval-01.dtbo +imx8mm-phycore-rpmsg-dtbs += imx8mm-phyboard-polis-rdk.dtb imx8mm-phycore-rpmsg.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mm-phyboard-polis-peb-av-10.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-phyboard-polis-peb-eval-01.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-phycore-rpmsg.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-phygate-tauri-l.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-prt8mm.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phycore-rpmsg.dtso b/arch/arm64/boot/dts/freescale/imx8mm-phycore-rpmsg.dtso new file mode 100644 index 000000000000..43d5905f3d72 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-phycore-rpmsg.dtso @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + * Author: Dominik Haller + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + #address-cells = <2>; + #size-cells = <2>; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + m4_reserved: m4@80000000 { + reg = <0 0x80000000 0 0x1000000>; + no-map; + }; + + vdev0vring0: vdev0vring0@b8000000 { + reg = <0 0xb8000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@b8008000 { + reg = <0 0xb8008000 0 0x8000>; + no-map; + }; + + rsc_table: rsc_table@b80ff000 { + reg = <0 0xb80ff000 0 0x1000>; + no-map; + }; + + vdevbuffer: vdevbuffer@b8400000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8400000 0 0x100000>; + no-map; + }; + }; + + core-m4 { + compatible = "fsl,imx8mm-cm4"; + clocks = <&clk IMX8MM_CLK_M4_DIV>; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + mbox-names = "tx", "rx", "rxdb"; + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, <&rsc_table>; + syscon = <&src>; + }; +}; From f432f54377ae566c1082a1916fe7215469cb3fb3 Mon Sep 17 00:00:00 2001 From: Teresa Remmet Date: Tue, 18 Feb 2025 08:41:55 +0100 Subject: [PATCH 58/84] arm64: dts: imx8mm-phycore-som: Add no-eth phy overlay There are SoM variants with no eth phy populated. Add overlay to be able to support this. Signed-off-by: Teresa Remmet Signed-off-by: Andrej Picej Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 2 ++ .../boot/dts/freescale/imx8mm-phycore-no-eth.dtso | 12 ++++++++++++ 2 files changed, 14 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-phycore-no-eth.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index dc62159988b0..a9e2dc703ae7 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -125,10 +125,12 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-phyboard-polis-rdk.dtb imx8mm-phyboard-polis-peb-av-10-dtbs += imx8mm-phyboard-polis-rdk.dtb imx8mm-phyboard-polis-peb-av-10.dtbo imx8mm-phyboard-polis-peb-eval-01-dtbs += imx8mm-phyboard-polis-rdk.dtb imx8mm-phyboard-polis-peb-eval-01.dtbo +imx8mm-phycore-no-eth-dtbs += imx8mm-phyboard-polis-rdk.dtb imx8mm-phycore-no-eth.dtbo imx8mm-phycore-rpmsg-dtbs += imx8mm-phyboard-polis-rdk.dtb imx8mm-phycore-rpmsg.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mm-phyboard-polis-peb-av-10.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-phyboard-polis-peb-eval-01.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-phycore-no-eth.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-phycore-rpmsg.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-phygate-tauri-l.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phycore-no-eth.dtso b/arch/arm64/boot/dts/freescale/imx8mm-phycore-no-eth.dtso new file mode 100644 index 000000000000..0fb4b6da6c10 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-phycore-no-eth.dtso @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + * Author: Teresa Remmet + */ + +/dts-v1/; +/plugin/; + +ðphy0 { + status = "disabled"; +}; From 9e87325a9c189a40b265cf77e737330a1ba8a79b Mon Sep 17 00:00:00 2001 From: Teresa Remmet Date: Tue, 18 Feb 2025 08:41:56 +0100 Subject: [PATCH 59/84] arm64: dts: imx8mm-phycore-som: Add overlay to disable SPI NOR flash There are SoM variants with no SPI NOR flash populated. Add overlay to be able to support this. Signed-off-by: Teresa Remmet Signed-off-by: Andrej Picej Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 2 ++ .../freescale/imx8mm-phycore-no-spiflash.dtso | 16 ++++++++++++++++ 2 files changed, 18 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-phycore-no-spiflash.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index a9e2dc703ae7..be6ef4c56fbf 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -126,11 +126,13 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-phyboard-polis-rdk.dtb imx8mm-phyboard-polis-peb-av-10-dtbs += imx8mm-phyboard-polis-rdk.dtb imx8mm-phyboard-polis-peb-av-10.dtbo imx8mm-phyboard-polis-peb-eval-01-dtbs += imx8mm-phyboard-polis-rdk.dtb imx8mm-phyboard-polis-peb-eval-01.dtbo imx8mm-phycore-no-eth-dtbs += imx8mm-phyboard-polis-rdk.dtb imx8mm-phycore-no-eth.dtbo +imx8mm-phycore-no-spiflash-dtbs += imx8mm-phyboard-polis-rdk.dtb imx8mm-phycore-no-spiflash.dtbo imx8mm-phycore-rpmsg-dtbs += imx8mm-phyboard-polis-rdk.dtb imx8mm-phycore-rpmsg.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mm-phyboard-polis-peb-av-10.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-phyboard-polis-peb-eval-01.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-phycore-no-eth.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-phycore-no-spiflash.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-phycore-rpmsg.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-phygate-tauri-l.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phycore-no-spiflash.dtso b/arch/arm64/boot/dts/freescale/imx8mm-phycore-no-spiflash.dtso new file mode 100644 index 000000000000..7bfc366c1689 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-phycore-no-spiflash.dtso @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + * Author: Teresa Remmet + */ + +/dts-v1/; +/plugin/; + +&flexspi { + status = "disabled"; +}; + +&som_flash { + status = "disabled"; +}; From 556d6be6f2455ebe802937da8a615f1bd1ae1424 Mon Sep 17 00:00:00 2001 From: Mathew McBride Date: Wed, 5 Mar 2025 11:19:01 +1100 Subject: [PATCH 60/84] arm64: dts: freescale: ten64: add usb hub definition A device tree binding for the Microchip USB5744 hub controller was added in commit 02be19e914b8 ("dt-bindings: usb: Add support for Microchip usb5744 hub controller"). U-Boot will consume this binding in order to perform the necessary actions to enable the USB hub ports over I2C. (We previously used our own out-of-tree driver for this task) The Ten64 board does not have any switchable supplies for the voltage rails utilized by the USB5744, so a pair of dummy supplies have been added to facilitate operation with U-Boot's hub driver. Signed-off-by: Mathew McBride Signed-off-by: Shawn Guo --- .../boot/dts/freescale/fsl-ls1088a-ten64.dts | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts index bc0d89427fbe..3a11068f2212 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts @@ -87,6 +87,22 @@ los-gpios = <&sfpgpio 7 GPIO_ACTIVE_HIGH>; maximum-power-milliwatt = <2000>; }; + + usb1v2_supply: regulator-usbhub-1v2 { + compatible = "regulator-fixed"; + regulator-name = "usbhub_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + system3v3_supply: regulator-system-3v3 { + compatible = "regulator-fixed"; + regulator-name = "system_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; }; /* XG1 - Upper SFP */ @@ -231,6 +247,12 @@ compatible = "atmel,at97sc3204t"; reg = <0x29>; }; + + usbhub: usb-hub@2d { + compatible = "microchip,usb5744"; + reg = <0x2d>; + }; + }; &i2c2 { @@ -378,10 +400,32 @@ }; }; +/* LS1088A USB Port 0 - direct to bottom USB-A port */ &usb0 { status = "okay"; }; +/* LS1088A USB Port 1 - to Microchip USB5744 USB Hub */ &usb1 { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; + + hub_2_0: hub@1 { + compatible = "usb424,2744"; + reg = <1>; + peer-hub = <&hub_3_0>; + i2c-bus = <&usbhub>; + vdd-supply = <&system3v3_supply>; + vdd2-supply = <&usb1v2_supply>; + }; + + hub_3_0: hub@2 { + compatible = "usb424,5744"; + reg = <2>; + peer-hub = <&hub_2_0>; + i2c-bus = <&usbhub>; + vdd-supply = <&system3v3_supply>; + vdd2-supply = <&usb1v2_supply>; + }; }; From 9f7595b3e5ae0ead20a74a5f2a8f0434b3254ac5 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Tue, 4 Feb 2025 19:27:37 +0100 Subject: [PATCH 61/84] arm64: dts: imx8mp: configure GPU and NPU clocks to overdrive rate A lot of other clocks on the i.MX8MP, including the DRAM set up by the bootloader are already running at overdrive clock rates. While this is a deviation from the configuration of other i.MX8M* family SoCs, overdrive is the default for most i.MX8MP boards and only some special purpose boards will choose to run the SoC at nominal drive rates. Up the GPU and NPU clock rates to their overdrive level to be consistent with other clocks set up in the dtsi. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index e0d3b8cba221..aeaa6a5c2f56 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -816,12 +816,12 @@ assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>, <&clk IMX8MP_CLK_ML_AXI>, <&clk IMX8MP_CLK_ML_AHB>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, <&clk IMX8MP_SYS_PLL1_800M>, <&clk IMX8MP_SYS_PLL1_800M>; - assigned-clock-rates = <800000000>, + assigned-clock-rates = <1000000000>, <800000000>, - <300000000>; + <400000000>; }; pgc_audio: power-domain@5 { @@ -2232,9 +2232,9 @@ clock-names = "core", "shader", "bus", "reg"; assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>, <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, - <&clk IMX8MP_SYS_PLL1_800M>; - assigned-clock-rates = <800000000>, <800000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL2_1000M>; + assigned-clock-rates = <1000000000>, <1000000000>; power-domains = <&pgc_gpu3d>; }; @@ -2247,8 +2247,8 @@ <&clk IMX8MP_CLK_GPU_AHB>; clock-names = "core", "bus", "reg"; assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; - assigned-clock-rates = <800000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; + assigned-clock-rates = <1000000000>; power-domains = <&pgc_gpu2d>; }; From 255fbd9eabe715b83db977232b1d6550b22f6613 Mon Sep 17 00:00:00 2001 From: Ahmad Fatoum Date: Tue, 18 Feb 2025 19:26:42 +0100 Subject: [PATCH 62/84] arm64: dts: imx8mp: Add optional nominal drive mode DTSI Unlike the i.MX8MM and i.MX8MN SoCs added earlier, the device tree for the i.MX8MP configures some clocks at frequencies that are only validated for overdrive mode, i.e. when VDD_SOC is 950 mV. Boards may want to run their SoC at the lower voltage of 850 mV though to reduce heat generation and power usage. For this to work, clock rates need to adhere to the limits of the nominal drive mode. Add an optional DTSI file which can be included by various boards to run in this mode. Reviewed-by: Peng Fan Signed-off-by: Ahmad Fatoum Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mp-nominal.dtsi | 63 +++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-nominal.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8mp-nominal.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-nominal.dtsi new file mode 100644 index 000000000000..f9a82a663033 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-nominal.dtsi @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2024 Pengutronix, Ahmad Fatoum + */ + +&clk { + assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>, + <&clk IMX8MP_CLK_A53_CORE>, + <&clk IMX8MP_SYS_PLL3>, + <&clk IMX8MP_CLK_NOC>, + <&clk IMX8MP_CLK_NOC_IO>, + <&clk IMX8MP_CLK_GIC>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_ARM_PLL_OUT>, + <0>, + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL3_OUT>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <0>, <0>, + <600000000>, + <800000000>, + <600000000>, + <400000000>; +}; + +&pgc_hdmimix { + assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>, + <&clk IMX8MP_CLK_HDMI_APB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_133M>; + assigned-clock-rates = <400000000>, <133000000>; +}; + +&pgc_hsiomix { + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <400000000>; +}; + +&pgc_gpumix { + assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>, + <&clk IMX8MP_CLK_GPU_AHB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL3_OUT>, + <&clk IMX8MP_SYS_PLL3_OUT>; + assigned-clock-rates = <600000000>, <300000000>; +}; + +&media_blk_ctrl { + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>, + <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>, + <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>, + <&clk IMX8MP_CLK_MEDIA_ISP>, + <&clk IMX8MP_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_VIDEO_PLL1_OUT>, + <&clk IMX8MP_VIDEO_PLL1_OUT>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <400000000>, <200000000>, + <0>, <0>, <400000000>, + <1039500000>; +}; From c7e78f8aac0e6a22e089b9efe293e721d749eccc Mon Sep 17 00:00:00 2001 From: Ahmad Fatoum Date: Tue, 18 Feb 2025 19:26:43 +0100 Subject: [PATCH 63/84] arm64: dts: imx8mp: add fsl,nominal-mode property into nominal.dtsi The imx8mp-nominal.dtsi is meant to be included into boards that want to override the default overdrive clock settings with settings suitable for running in nominal drive mode at its lower required voltage. Specifying fsl,operating-mode = "nominal" informs drivers of this fact, so they can sanity check runtime clock reconfiguration to observe the limits imposed by nominal mode. Signed-off-by: Ahmad Fatoum Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-nominal.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-nominal.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-nominal.dtsi index f9a82a663033..a1b75c9068b2 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-nominal.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-nominal.dtsi @@ -21,6 +21,7 @@ <800000000>, <600000000>, <400000000>; + fsl,operating-mode = "nominal"; }; &pgc_hdmimix { From 3e09fbc76794b8384e5b46cb8eeefeed5a017203 Mon Sep 17 00:00:00 2001 From: Ahmad Fatoum Date: Tue, 18 Feb 2025 19:26:44 +0100 Subject: [PATCH 64/84] arm64: dts: freescale: imx8mp-skov: configure LDB clock automatically The comment in the DT mentions that "currently it is not possible to let display clocks configure automatically, so we need to set them manually". Since commit ff06ea04e4cf ("clk: imx: clk-imx8mp: Allow media_disp pixel clock reconfigure parent rate"), this is no longer the case. Make use of this new functionality by dropping the now unneeded assigned-clock-rates in &media_blk_ctrl. Signed-off-by: Ahmad Fatoum Acked-by: Peng Fan Signed-off-by: Shawn Guo --- .../imx8mp-skov-revb-mi1010ait-1cp1.dts | 19 +++++-------------- 1 file changed, 5 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts b/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts index 2c75da5f064f..a13f6d76a495 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts @@ -51,8 +51,11 @@ }; &lvds_bridge { - /* IMX8MP_CLK_MEDIA_LDB = IMX8MP_CLK_MEDIA_DISP2_PIX * 7 */ - assigned-clock-rates = <490000000>; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>, + <&clk IMX8MP_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; + /* IMX8MP_VIDEO_PLL1 = IMX8MP_CLK_MEDIA_DISP2_PIX * 2 * 7 */ + assigned-clock-rates = <0>, <980000000>; status = "okay"; ports { @@ -64,18 +67,6 @@ }; }; -&media_blk_ctrl { - /* currently it is not possible to let display clocks confugure - * automatically, so we need to set them manually - */ - assigned-clock-rates = <500000000>, <200000000>, <0>, - /* IMX8MP_CLK_MEDIA_DISP2_PIX = pixelclk of lvds panel */ - <70000000>, - <500000000>, - /* IMX8MP_VIDEO_PLL1 = IMX8MP_CLK_MEDIA_LDB */ - <490000000>; -}; - &pwm4 { status = "okay"; }; From 1cf99ee00d5a1e38401be2ea409305ff3d11778e Mon Sep 17 00:00:00 2001 From: Ahmad Fatoum Date: Tue, 18 Feb 2025 19:26:45 +0100 Subject: [PATCH 65/84] arm64: dts: freescale: imx8mp-skov: operate SoC in nominal mode To reduce heat generation, the Skov i.MX8MP boards should run in nominal drive mode with a VDD_SOC voltage of 850 mV. At this operating point, not all frequencies that are achievable with overdrive mode are possible, so import imx8mp-nominal.dtsi to clock down the clocks. Signed-off-by: Ahmad Fatoum Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi index ec7857db7bf0..b5e34e9d5a90 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: (GPL-2.0 OR MIT) #include "imx8mp.dtsi" +#include "imx8mp-nominal.dtsi" #include @@ -255,8 +256,8 @@ regulators { reg_vdd_soc: BUCK1 { regulator-name = "VDD_SOC"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <2187500>; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; vin-supply = <®_5v_p>; regulator-boot-on; regulator-always-on; From 34662050b023399c5de6ddcb4de121b24297bcc9 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 18 Feb 2025 19:38:14 +0100 Subject: [PATCH 66/84] arm64: dts: imx8mp-skov: add basic board as fallback All Skov i.MX8MP boards share the same baseboard (modulo revisions) and are booted with the same bootloader image, which samples some strapping pins at startup and determines which kernel device tree to use. For use as bootloader device tree and as fallback, when no matching device tree has been found, add a basic variant that doesn't configure any variant-specific peripherals like displays. Signed-off-by: Oleksij Rempel Signed-off-by: Ahmad Fatoum Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + arch/arm64/boot/dts/freescale/imx8mp-skov-basic.dts | 10 ++++++++++ 2 files changed, 11 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-skov-basic.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index be6ef4c56fbf..617408934665 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -206,6 +206,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-nitrogen-smarc-universal-board.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb imx8mp-phyboard-pollux-rdk-no-eth-dtbs += imx8mp-phyboard-pollux-rdk.dtb imx8mp-phycore-no-eth.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk-no-eth.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-basic.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-lt6.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-mi1010ait-1cp1.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-skov-basic.dts b/arch/arm64/boot/dts/freescale/imx8mp-skov-basic.dts new file mode 100644 index 000000000000..5a2629f3567c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-skov-basic.dts @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; + +#include "imx8mp-skov-reva.dtsi" + +/ { + model = "SKOV IMX8MP CPU basic/fallback"; + compatible = "skov,imx8mp-skov-basic", "fsl,imx8mp"; +}; From 505aa4c775d10832094690874039255c0f1036ec Mon Sep 17 00:00:00 2001 From: Ahmad Fatoum Date: Tue, 18 Feb 2025 19:38:15 +0100 Subject: [PATCH 67/84] arm64: dts: imx8mp-skov: move I2C2 pin control group into DTSI I2C2 is exposed on a pin header on the base board, so its pinmux is always the same if it's enabled. Therefore, move the definition to the common DTSI, so board DTs only need to override the status to enable it. Signed-off-by: Ahmad Fatoum Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi | 12 ++++++++++++ .../freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts | 11 ----------- 2 files changed, 12 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi index b5e34e9d5a90..e1a8aed511cd 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi @@ -333,6 +333,11 @@ }; }; +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; +}; + &i2c3 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -564,6 +569,13 @@ >; }; + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 diff --git a/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts b/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts index a13f6d76a495..45c9a6d55bc9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts @@ -27,8 +27,6 @@ &i2c2 { clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; touchscreen@38 { @@ -81,12 +79,3 @@ voltage-table = <3160000 73>; status = "okay"; }; - -&iomuxc { - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 - MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 - >; - }; -}; From 00fad74ebe56d8ad499cc21a5bfb7f8a1654e190 Mon Sep 17 00:00:00 2001 From: Ahmad Fatoum Date: Tue, 18 Feb 2025 19:38:16 +0100 Subject: [PATCH 68/84] arm64: dts: imx8mp-skov: describe I2C bus recovery for all controllers I2C bus recovery can be used to recover when SCL/SDA are stuck low. To be able to use it, add the necessary GPIO and pinctrl entries. Signed-off-by: Ahmad Fatoum Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mp-skov-reva.dtsi | 48 +++++++++++++++++-- 1 file changed, 44 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi index e1a8aed511cd..29951a36e43e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi @@ -241,8 +241,11 @@ &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; pmic@25 { @@ -334,14 +337,20 @@ }; &i2c2 { - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; }; &i2c3 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; i2c_rtc: rtc@51 { @@ -356,8 +365,11 @@ &i2c4 { clock-frequency = <380000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; switch: switch@5f { @@ -569,6 +581,13 @@ >; }; + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c2 + MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c2 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 @@ -576,6 +595,13 @@ >; }; + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c2 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 @@ -583,6 +609,13 @@ >; }; + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c2 + >; + }; + pinctrl_i2c4: i2c4grp { fsl,pins = < MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 @@ -590,6 +623,13 @@ >; }; + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c3 + MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c3 + >; + }; + pinctrl_pmic: pmicirqgrp { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 From f18ec29591e8c72a239664ff42c3e4b516783a5a Mon Sep 17 00:00:00 2001 From: Ahmad Fatoum Date: Tue, 18 Feb 2025 19:38:17 +0100 Subject: [PATCH 69/84] arm64: dts: imx8mp-skov: add revC BD500 board The BD500 replaces the touch display with 3 bicolor LEDs and a push button on top of a Skov i.MX8-CPU revision C. Signed-off-by: Oleksij Rempel Signed-off-by: Ahmad Fatoum Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx8mp-skov-revc-bd500.dts | 91 +++++++++++++++++++ 2 files changed, 92 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-skov-revc-bd500.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 617408934665..dffe9cb8aff9 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -210,6 +210,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-basic.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-lt6.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-mi1010ait-1cp1.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revc-bd500.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-var-som-symphony.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-skov-revc-bd500.dts b/arch/arm64/boot/dts/freescale/imx8mp-skov-revc-bd500.dts new file mode 100644 index 000000000000..b816c6cd3bca --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-skov-revc-bd500.dts @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; + +#include "imx8mp-skov-reva.dtsi" + +/ { + model = "SKOV IMX8MP CPU revC - bd500"; + compatible = "skov,imx8mp-skov-revc-bd500", "fsl,imx8mp"; + + leds { + led_system_red: led-3 { + label = "bd500:system:red"; + color = ; + /* Inverted compared to others due to NMOS inverter */ + gpios = <&gpioexp 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led_system_green: led-4 { + label = "bd500:system:green"; + color = ; + gpios = <&gpioexp 2 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led_lan1_red: led-5 { + label = "bd500:lan1:act"; + color = ; + linux,default-trigger = "netdev"; + gpios = <&gpioexp 1 GPIO_ACTIVE_LOW>; + }; + + led_lan1_green: led-6 { + label = "bd500:lan1:link"; + color = ; + linux,default-trigger = "netdev"; + gpios = <&gpioexp 0 GPIO_ACTIVE_LOW>; + }; + + led_lan2_red: led-7 { + label = "bd500:lan2:act"; + color = ; + linux,default-trigger = "netdev"; + gpios = <&gpioexp 6 GPIO_ACTIVE_LOW>; + }; + + led_lan2_green: led-8 { + label = "bd500:lan2:link"; + color = ; + linux,default-trigger = "netdev"; + gpios = <&gpioexp 7 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-1 { + label = "S1"; + linux,code = ; + gpios = <&gpioexp 5 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + status = "okay"; + + gpioexp: gpio@20 { + compatible = "nxp,pca6408"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_exp>; + interrupts-extended = <&gpio4 28 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>; + vcc-supply = <®_vdd_3v3>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&iomuxc { + pinctrl_gpio_exp: gpioexpgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x0 + MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x0 + >; + }; +}; From d7b2b64b7315df572a2341208c671f21ca86be03 Mon Sep 17 00:00:00 2001 From: Ahmad Fatoum Date: Tue, 18 Feb 2025 19:38:18 +0100 Subject: [PATCH 70/84] arm64: dts: imx8mp-skov: support new 7" panel board This board is very similar to the already upstream imx8mp-skov-revb-mi1010ait-1cp1.dts with the difference that it uses a different 7" LVDS panel. Signed-off-by: Ahmad Fatoum Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../imx8mp-skov-revc-tian-g07017.dts | 81 +++++++++++++++++++ 2 files changed, 82 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-skov-revc-tian-g07017.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index dffe9cb8aff9..a211a56ec2c6 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -211,6 +211,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-lt6.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-mi1010ait-1cp1.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revc-bd500.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revc-tian-g07017.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-var-som-symphony.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-skov-revc-tian-g07017.dts b/arch/arm64/boot/dts/freescale/imx8mp-skov-revc-tian-g07017.dts new file mode 100644 index 000000000000..9a562c011f2c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-skov-revc-tian-g07017.dts @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; + +#include "imx8mp-skov-reva.dtsi" + +/ { + model = "SKOV IMX8MP CPU revC - TIAN G07017"; + compatible = "skov,imx8mp-skov-revc-tian-g07017", "fsl,imx8mp"; + + panel { + compatible = "topland,tian-g07017-01"; + backlight = <&backlight>; + power-supply = <®_tft_vcom>; + + port { + in_lvds0: endpoint { + remote-endpoint = <&ldb_lvds_ch0>; + }; + }; + }; +}; + +&backlight { + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + status = "okay"; + + touchscreen@38 { + compatible = "edt,edt-ft5506"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touchscreen>; + interrupts-extended = <&gpio4 28 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <1024>; + touchscreen-size-y = <600>; + vcc-supply = <®_vdd_3v3>; + iovcc-supply = <®_vdd_3v3>; + wakeup-source; + }; +}; + +&lcdif2 { + status = "okay"; +}; + +&lvds_bridge { + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>, + <&clk IMX8MP_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; + /* IMX8MP_VIDEO_PLL1 = IMX8MP_CLK_MEDIA_DISP2_PIX * 2 * 7 */ + assigned-clock-rates = <0>, <358400000>; + status = "okay"; + + ports { + port@1 { + ldb_lvds_ch0: endpoint { + remote-endpoint = <&in_lvds0>; + }; + }; + }; +}; + +&pwm4 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +®_tft_vcom { + regulator-min-microvolt = <3160000>; + regulator-max-microvolt = <3160000>; + voltage-table = <3160000 73>; + status = "okay"; +}; From c25548f22d0772be057d03a234b0fd6851aa3bce Mon Sep 17 00:00:00 2001 From: Frank Li Date: Fri, 21 Feb 2025 16:15:58 -0500 Subject: [PATCH 71/84] arm64: dts: imx95: Add #io-channel-cells = <1> for adc node Add #io-channel-cells = <1> for adc node. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx95.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index 3af13173de4b..69a4a2db3463 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -1379,6 +1379,7 @@ ; clocks = <&scmi_clk IMX95_CLK_ADC>; clock-names = "ipg"; + #io-channel-cells = <1>; status = "disabled"; }; From 969497ebefcfe69c8d0ee6f6291102418d5589b1 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Fri, 21 Feb 2025 16:15:59 -0500 Subject: [PATCH 72/84] arm64: dts: imx95: Add i3c1 and i3c2 Add i3c1 and i3c2 support. Signed-off-by: Frank Li Reviewed-by: Daniel Baluta Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx95.dtsi | 26 ++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index 69a4a2db3463..51625bc9154e 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -673,6 +673,19 @@ status = "disabled"; }; + i3c2: i3c@42520000 { + compatible = "silvaco,i3c-master-v1"; + reg = <0x42520000 0x10000>; + interrupts = ; + #address-cells = <3>; + #size-cells = <0>; + clocks = <&scmi_clk IMX95_CLK_BUSAON>, + <&scmi_clk IMX95_CLK_I3C2>, + <&scmi_clk IMX95_CLK_I3C2SLOW>; + clock-names = "pclk", "fast_clk", "slow_clk"; + status = "disabled"; + }; + lpi2c3: i2c@42530000 { compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; reg = <0x42530000 0x10000>; @@ -1245,6 +1258,19 @@ status = "disabled"; }; + i3c1: i3c@44330000 { + compatible = "silvaco,i3c-master-v1"; + reg = <0x44330000 0x10000>; + interrupts = ; + #address-cells = <3>; + #size-cells = <0>; + clocks = <&scmi_clk IMX95_CLK_BUSAON>, + <&scmi_clk IMX95_CLK_I3C1>, + <&scmi_clk IMX95_CLK_I3C1SLOW>; + clock-names = "pclk", "fast_clk", "slow_clk"; + status = "disabled"; + }; + lpi2c1: i2c@44340000 { compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; reg = <0x44340000 0x10000>; From e3e8b199aff893549816707321e71cbade63cb06 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Fri, 21 Feb 2025 16:16:00 -0500 Subject: [PATCH 73/84] arm64: dts: imx95: Add imx95-15x15-evk support Add imx95-15x15-evk support. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/imx95-15x15-evk.dts | 1130 +++++++++++++++++ 2 files changed, 1131 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index a211a56ec2c6..b6d3fe26d621 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -301,6 +301,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxca.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb +dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk.dtb imx8mm-kontron-dl-dtbs := imx8mm-kontron-bl.dtb imx8mm-kontron-dl.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts new file mode 100644 index 000000000000..514f2429dcbc --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts @@ -0,0 +1,1130 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 NXP + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "imx95.dtsi" + +#define FALLING_EDGE BIT(0) +#define RISING_EDGE BIT(1) + +#define BRD_SM_CTRL_SD3_WAKE 0x8000 +#define BRD_SM_CTRL_PCIE1_WAKE 0x8001 +#define BRD_SM_CTRL_BT_WAKE 0x8002 +#define BRD_SM_CTRL_PCIE2_WAKE 0x8003 +#define BRD_SM_CTRL_BUTTON 0x8004 + +/ { + compatible = "fsl,imx95-15x15-evk", "fsl,imx95"; + model = "NXP i.MX95 15X15 board"; + + aliases { + ethernet0 = &enetc_port0; + ethernet1 = &enetc_port1; + serial0 = &lpuart1; + }; + + bt_sco_codec: bt-sco-codec { + compatible = "linux,bt-sco"; + #sound-dai-cells = <1>; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + stdout-path = &lpuart1; + }; + + fan0: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + cooling-levels = <64 128 192 255>; + pwms = <&tpm6 0 4000000 PWM_POLARITY_INVERTED>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8_SW"; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_SW"; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vref_1v8"; + }; + + reg_audio_pwr: regulator-audio-pwr { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "audio-pwr"; + gpio = <&pcal6524 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_audio_switch1: regulator-audio-switch1 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "audio-switch1"; + gpio = <&pcal6524 0 GPIO_ACTIVE_LOW>; + }; + + reg_can2_stby: regulator-can2-stby { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "can2-stby"; + gpio = <&pcal6524 14 GPIO_ACTIVE_LOW>; + }; + + reg_m2_pwr: regulator-m2-pwr { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "M.2-power"; + gpio = <&pcal6524 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + off-on-delay-us = <12000>; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VDD_SD2_3V3"; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc3_vmmc: regulator-usdhc3 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "WLAN_EN"; + vin-supply = <®_m2_pwr>; + gpio = <&pcal6524 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* + * IW612 wifi chip needs more delay than other wifi chips to complete + * the host interface initialization after power up, otherwise the + * internal state of IW612 may be unstable, resulting in the failure of + * the SDIO3.0 switch voltage. + */ + startup-delay-us = <20000>; + }; + + reg_vcc_12v: regulator-vcc-12v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <12000000>; + regulator-min-microvolt = <12000000>; + regulator-name = "VCC_12V"; + gpio = <&pcal6524 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reserved-memory { + ranges; + #address-cells = <2>; + #size-cells = <2>; + + linux_cma: linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x80000000 0 0x7F000000>; + reusable; + size = <0 0x3c000000>; + linux,cma-default; + }; + + vdev0vring0: vdev0vring0@88000000 { + reg = <0 0x88000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@88008000 { + reg = <0 0x88008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@88010000 { + reg = <0 0x88010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@88018000 { + reg = <0 0x88018000 0 0x8000>; + no-map; + }; + + vdevbuffer: vdevbuffer@88020000 { + compatible = "shared-dma-pool"; + reg = <0 0x88020000 0 0x100000>; + no-map; + }; + + rsc_table: rsc-table@88220000 { + reg = <0 0x88220000 0 0x1000>; + no-map; + }; + + vpu_boot: vpu_boot@a0000000 { + reg = <0 0xa0000000 0 0x100000>; + no-map; + }; + }; + + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-inversion; + simple-audio-card,bitclock-master = <&btcpu>; + simple-audio-card,format = "dsp_a"; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,name = "bt-sco-audio"; + + simple-audio-card,codec { + sound-dai = <&bt_sco_codec 1>; + }; + + btcpu: simple-audio-card,cpu { + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + sound-dai = <&sai1>; + }; + }; + + sound-micfil { + compatible = "fsl,imx-audio-card"; + model = "micfil-audio"; + + pri-dai-link { + format = "i2s"; + link-name = "micfil hifi"; + + cpu { + sound-dai = <&micfil>; + }; + }; + }; + + sound-wm8962 { + compatible = "fsl,imx-audio-wm8962"; + audio-codec = <&wm8962>; + audio-cpu = <&sai3>; + audio-routing = "Headphone Jack", "HPOUTL", "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", "Ext Spk", "SPKOUTR", "AMIC", "MICBIAS", + "IN3R", "AMIC", "IN1R", "AMIC"; + hp-det-gpio = <&gpio2 21 GPIO_ACTIVE_HIGH>; + model = "wm8962-audio"; + pinctrl-0 = <&pinctrl_hp>; + pinctrl-names = "default"; + }; + + sound-xcvr { + compatible = "fsl,imx-audio-card"; + model = "imx-audio-xcvr"; + + pri-dai-link { + link-name = "XCVR PCM"; + + cpu { + sound-dai = <&xcvr>; + }; + }; + }; + + usdhc3_pwrseq: usdhc3-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-0 = <&pinctrl_usdhc3_pwrseq>; + pinctrl-names = "default"; + reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + }; + + memory@80000000 { + reg = <0x0 0x80000000 0 0x80000000>; + device_type = "memory"; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&enetc_port0 { + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + pinctrl-0 = <&pinctrl_enetc0>; + pinctrl-names = "default"; + status = "okay"; +}; + +&enetc_port1 { + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; + pinctrl-0 = <&pinctrl_enetc1>; + pinctrl-names = "default"; + status = "okay"; +}; + +&flexcan2 { + pinctrl-0 = <&pinctrl_flexcan2>; + pinctrl-names = "default"; + xceiver-supply = <®_can2_stby>; + status = "okay"; +}; + +&i3c2 { + i2c-scl-hz = <400000>; + pinctrl-0 = <&pinctrl_i3c2>; + pinctrl-names = "default"; + status = "okay"; + + pca9570: gpio@24 { + compatible = "nxp,pca9570"; + reg = <0x24 0 (I2C_FILTER)>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = "OUT1", "OUT2", "OUT3", "OUT4"; + }; +}; + +&lpi2c2 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-names = "default"; + status = "okay"; + + wm8962: codec@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&scmi_clk IMX95_CLK_SAI3>; + AVDD-supply = <®_audio_pwr>; + CPVDD-supply = <®_audio_pwr>; + DBVDD-supply = <®_audio_pwr>; + DCVDD-supply = <®_audio_pwr>; + gpio-cfg = < + 0x0000 + 0x0000 + 0x0000 + 0x0000 + 0x0000 + 0x0000 + >; + MICVDD-supply = <®_audio_pwr>; + PLLVDD-supply = <®_audio_pwr>; + SPKVDD1-supply = <®_audio_pwr>; + SPKVDD2-supply = <®_audio_pwr>; + }; + + pcal6524: gpio@22 { + compatible = "nxp,pcal6524"; + reg = <0x22>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio5>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells = <2>; + gpio-controller; + pinctrl-0 = <&pinctrl_pcal6524>; + pinctrl-names = "default"; + }; +}; + +&lpi2c3 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-names = "default"; + status = "okay"; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x50>; + interrupt-parent = <&gpio5>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_ptn5110>; + pinctrl-names = "default"; + + typec_con: connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + op-sink-microwatt = <15000000>; + power-role = "dual"; + self-powered; + sink-pdos = ; + source-pdos = ; + try-power-role = "sink"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec_con_hs: endpoint { + remote-endpoint = <&usb3_data_hs>; + }; + }; + + port@1 { + reg = <1>; + + typec_con_ss: endpoint { + remote-endpoint = <&usb3_data_ss>; + }; + }; + }; + }; + }; + + pca9632: led-controller@62 { + compatible = "nxp,pca9632"; + reg = <0x62>; + #address-cells = <1>; + #size-cells = <0>; + nxp,inverted-out; + + led_backlight0: led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_BACKLIGHT; + function-enumerator = <0>; + }; + + led_backlight1: led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_BACKLIGHT; + function-enumerator = <1>; + }; + }; +}; + +&lpi2c4 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c4>; + pinctrl-names = "default"; + status = "okay"; +}; + +&lpi2c6 { + clock-frequency = <100000>; + pinctrl-0 = <&pinctrl_lpi2c6>; + pinctrl-names = "default"; + status = "okay"; +}; + +&lpuart1 { + pinctrl-0 = <&pinctrl_uart1>; + pinctrl-names = "default"; + status = "okay"; +}; + +&lpuart5 { + pinctrl-0 = <&pinctrl_uart5>; + pinctrl-names = "default"; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +&micfil { + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_PDM>; + assigned-clock-parents = <0>, <0>, <0>, <0>, <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, <3612672000>, <393216000>, <361267200>, <49152000>; + #sound-dai-cells = <0>; + pinctrl-0 = <&pinctrl_pdm>; + pinctrl-names = "default"; + status = "okay"; +}; + +&mu7 { + status = "okay"; +}; + +&netc_blk_ctrl { + status = "okay"; +}; + +&netc_bus0 { + msi-map = <0x00 &its 0x60 0x1>, //ENETC0 PF + <0x10 &its 0x61 0x1>, //ENETC0 VF0 + <0x20 &its 0x62 0x1>, //ENETC0 VF1 + <0x40 &its 0x63 0x1>, //ENETC1 PF + <0x50 &its 0x65 0x1>, //ENETC1 VF0 + <0x60 &its 0x66 0x1>, //ENETC1 VF1 + <0x80 &its 0x64 0x1>, //ENETC2 PF + <0xc0 &its 0x67 0x1>; +}; + +&netc_emdio { + pinctrl-0 = <&pinctrl_emdio>; + pinctrl-names = "default"; + status = "okay"; + + ethphy0: ethernet-phy@1 { + reg = <1>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + reset-gpios = <&pcal6524 4 GPIO_ACTIVE_LOW>; + realtek,clkout-disable; + }; + + ethphy1: ethernet-phy@2 { + reg = <2>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + reset-gpios = <&pcal6524 5 GPIO_ACTIVE_LOW>; + realtek,clkout-disable; + }; +}; + +&netc_timer { + status = "okay"; +}; + +&netcmix_blk_ctrl { + status = "okay"; +}; + +&pcie0 { + pinctrl-0 = <&pinctrl_pcie0>; + pinctrl-names = "default"; + reset-gpio = <&gpio5 13 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_m2_pwr>; + status = "okay"; +}; + +&sai1 { + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_SAI1>; + assigned-clock-parents = <0>, <0>, <0>, <0>, <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, <3612672000>, <393216000>, <361267200>, <12288000>; + #sound-dai-cells = <0>; + pinctrl-0 = <&pinctrl_sai1>; + pinctrl-names = "default"; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&sai3 { + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_SAI3>; + assigned-clock-parents = <0>, <0>, <0>, <0>, <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, <3612672000>, <393216000>, <361267200>, <12288000>; + #sound-dai-cells = <0>; + pinctrl-0 = <&pinctrl_sai3>; + pinctrl-names = "default"; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&scmi_iomuxc { + pinctrl_emdio: emdiogrp { + fsl,pins = < + IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC 0x57e + IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO 0x97e + >; + }; + + pinctrl_enetc0: enetc0grp { + fsl,pins = < + IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x57e + IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x57e + IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x57e + IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x57e + IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e + IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e + IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e + IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e + IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e + IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e + IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e + IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e + >; + }; + + pinctrl_enetc1: enetc1grp { + fsl,pins = < + IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x57e + IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x57e + IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x57e + IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x57e + IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x57e + IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x58e + IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x57e + IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x58e + IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x57e + IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x57e + IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x57e + IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x57e + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + IMX95_PAD_GPIO_IO25__CAN2_TX 0x39e + IMX95_PAD_GPIO_IO27__CAN2_RX 0x39e + >; + }; + + pinctrl_hp: hpgrp { + fsl,pins = < + IMX95_PAD_GPIO_IO21__GPIO2_IO_BIT21 0x31e + >; + }; + + pinctrl_i3c2: i3c2grp { + fsl,pins = < + IMX95_PAD_ENET1_MDC__I3C2_SCL 0x40000186 + IMX95_PAD_ENET1_MDIO__I3C2_SDA 0x40000186 + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + IMX95_PAD_I2C1_SCL__AONMIX_TOP_LPI2C1_SCL 0x40000b9e + IMX95_PAD_I2C1_SDA__AONMIX_TOP_LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40000b9e + IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_lpi2c4: lpi2c4grp { + fsl,pins = < + IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40000b9e + IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40000b9e + >; + }; + + pinctrl_lpi2c6: lpi2c6grp { + fsl,pins = < + IMX95_PAD_GPIO_IO02__LPI2C6_SDA 0x40000b9e + IMX95_PAD_GPIO_IO03__LPI2C6_SCL 0x40000b9e + >; + }; + + pinctrl_mipi_dsi_csi: mipidsigrp { + fsl,pins = < + IMX95_PAD_XSPI1_DATA6__GPIO5_IO_BIT6 0x31e + >; + }; + + pinctrl_pcal6524: pcal6524grp { + fsl,pins = < + IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x31e + >; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins = < + IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x40000b1e + IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13 0x31e + >; + }; + + pinctrl_pdm: pdmgrp { + fsl,pins = < + IMX95_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 0x31e + IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_BIT0 0x31e + >; + }; + + pinctrl_ptn5110: ptn5110grp { + fsl,pins = < + IMX95_PAD_XSPI1_SS1_B__GPIO5_IO_BIT11 0x31e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + IMX95_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_RX_DATA_BIT0 0x31e + IMX95_PAD_SAI1_TXC__AONMIX_TOP_SAI1_TX_BCLK 0x31e + IMX95_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_TX_SYNC 0x31e + IMX95_PAD_SAI1_TXD0__AONMIX_TOP_SAI1_TX_DATA_BIT0 0x31e + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_SAI2_RX_BCLK 0x31e + IMX95_PAD_ENET2_MDC__NETCMIX_TOP_SAI2_RX_SYNC 0x31e + IMX95_PAD_ENET2_TD3__NETCMIX_TOP_SAI2_RX_DATA_BIT0 0x31e + IMX95_PAD_ENET2_TD2__NETCMIX_TOP_SAI2_RX_DATA_BIT1 0x31e + IMX95_PAD_ENET2_TXC__NETCMIX_TOP_SAI2_TX_BCLK 0x31e + IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_SAI2_TX_SYNC 0x31e + IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_SAI2_TX_DATA_BIT0 0x31e + IMX95_PAD_ENET2_RXC__NETCMIX_TOP_SAI2_TX_DATA_BIT1 0x31e + IMX95_PAD_ENET2_RD0__NETCMIX_TOP_SAI2_TX_DATA_BIT2 0x31e + IMX95_PAD_ENET2_RD1__NETCMIX_TOP_SAI2_TX_DATA_BIT3 0x31e + IMX95_PAD_ENET2_RD2__NETCMIX_TOP_SAI2_MCLK 0x31e + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + IMX95_PAD_GPIO_IO17__SAI3_MCLK 0x31e + IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e + IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e + IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 0x31e + IMX95_PAD_GPIO_IO19__SAI3_TX_DATA_BIT0 0x31e + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + IMX95_PAD_GPIO_IO22__SPDIF_IN 0x3fe + IMX95_PAD_GPIO_IO23__SPDIF_OUT 0x3fe + >; + }; + + pinctrl_tpm3: tpm3grp { + fsl,pins = < + IMX95_PAD_CCM_CLKO2__GPIO3_IO_BIT27 0x51e + >; + }; + + pinctrl_tpm6: tpm6grp { + fsl,pins = < + IMX95_PAD_GPIO_IO08__TPM6_CH0 0x51e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e + IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + IMX95_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e + IMX95_PAD_DAP_TDI__LPUART5_RX 0x31e + IMX95_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e + IMX95_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e + IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e + IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e + IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e + IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e + IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e + >; + }; + + pinctrl_usdhc3_pwrseq: usdhc3pwrseqgrp { + fsl,pins = < + IMX95_PAD_XSPI1_SCLK__GPIO5_IO_BIT9 0x31e + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e + IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e + IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e + IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e + IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e + IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + IMX95_PAD_SD3_CLK__USDHC3_CLK 0x15fe + IMX95_PAD_SD3_CMD__USDHC3_CMD 0x13fe + IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe + IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe + IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe + IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe + >; + }; +}; + +&scmi_misc { + nxp,ctrl-ids = , + , + , + , + ; +}; + +&thermal_zones { + a55-thermal { + cooling-maps { + map1 { + cooling-device = <&fan0 0 1>; + trip = <&atrip2>; + }; + + map2 { + cooling-device = <&fan0 1 2>; + trip = <&atrip3>; + }; + + map3 { + cooling-device = <&fan0 2 3>; + trip = <&atrip4>; + }; + }; + + trips { + atrip2: trip2 { + hysteresis = <2000>; + temperature = <55000>; + type = "active"; + }; + + atrip3: trip3 { + hysteresis = <2000>; + temperature = <65000>; + type = "active"; + }; + + atrip4: trip4 { + hysteresis = <2000>; + temperature = <75000>; + type = "active"; + }; + }; + }; + + pf09-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 2>; + + trips { + pf09_alert: trip0 { + hysteresis = <2000>; + temperature = <140000>; + type = "passive"; + }; + + pf09_crit: trip1 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; + + pf53arm-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 4>; + + cooling-maps { + map0 { + cooling-device = <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + trip = <&pf5301_alert>; + }; + }; + + trips { + pf5301_alert: trip0 { + hysteresis = <2000>; + temperature = <140000>; + type = "passive"; + }; + + pf5301_crit: trip1 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; + + pf53soc-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 3>; + + trips { + pf5302_alert: trip0 { + hysteresis = <2000>; + temperature = <140000>; + type = "passive"; + }; + + pf5302_crit: trip1 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; +}; + +&tpm3 { + pinctrl-0 = <&pinctrl_tpm3>; + pinctrl-names = "default"; + status = "okay"; +}; + +&tpm6 { + pinctrl-0 = <&pinctrl_tpm6>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + adp-disable; + dr_mode = "otg"; + hnp-disable; + role-switch-default-mode = "peripheral"; + srp-disable; + usb-role-switch; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + status = "okay"; + + port { + usb3_data_hs: endpoint { + remote-endpoint = <&typec_con_hs>; + }; + }; +}; + +&usb3_phy { + orientation-switch; + fsl,phy-tx-preemp-amp-tune-microamp = <600>; + status = "okay"; + + port { + usb3_data_ss: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; +}; + +&usdhc1 { + bus-width = <8>; + non-removable; + no-sd; + no-sdio; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-3 = <&pinctrl_usdhc1>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + fsl,tuning-step = <1>; + status = "okay"; +}; + +&usdhc2 { + bus-width = <4>; + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + vmmc-supply = <®_usdhc2_vmmc>; + fsl,tuning-step = <1>; + status = "okay"; +}; + +&usdhc3 { + bus-width = <4>; + keep-power-in-suspend; + mmc-pwrseq = <&usdhc3_pwrseq>; + non-removable; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + pinctrl-3 = <&pinctrl_usdhc3>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + vmmc-supply = <®_usdhc3_vmmc>; + wakeup-source; + status = "okay"; +}; + +&wdog3 { + status = "okay"; +}; + +&xcvr { + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, + <&scmi_clk IMX95_CLK_SPDIF>, + <&dummy>, + <&scmi_clk IMX95_CLK_AUDIOXCVR>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>; + clock-names = "ipg", "phy", "spba", "pll_ipg", "pll8k", "pll11k"; + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_SPDIF>, + <&scmi_clk IMX95_CLK_AUDIOXCVR>; + assigned-clock-parents = <0>, <0>, <0>, <0>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; + assigned-clock-rates = <3932160000>, <3612672000>, + <393216000>, <361267200>, + <12288000>, <0>; + #sound-dai-cells = <0>; + pinctrl-0 = <&pinctrl_spdif>; + pinctrl-names = "default"; + status = "okay"; +}; From e82bc7cfea635b208c858c57a1a2483e51c5c704 Mon Sep 17 00:00:00 2001 From: Ciprian Marian Costea Date: Mon, 24 Feb 2025 15:40:16 +0200 Subject: [PATCH 74/84] arm64: dts: s32g: add FlexCAN[0..3] support for s32g2 and s32g3 Add FlexCAN[0..3] for S32G2 and S32G3 SoCs. Signed-off-by: Ciprian Marian Costea Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/s32g2.dtsi | 52 ++++++++++++++ arch/arm64/boot/dts/freescale/s32g3.dtsi | 56 +++++++++++++++ .../boot/dts/freescale/s32gxxxa-evb.dtsi | 72 +++++++++++++++++++ .../boot/dts/freescale/s32gxxxa-rdb.dtsi | 48 +++++++++++++ 4 files changed, 228 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi index e38f1f878790..ea1456d361a3 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -334,6 +334,32 @@ clock-names = "dmamux0", "dmamux1"; }; + can0: can@401b4000 { + compatible = "nxp,s32g2-flexcan"; + reg = <0x401b4000 0xa000>; + interrupts = , + , + , + ; + interrupt-names = "mb-0", "state", "berr", "mb-1"; + clocks = <&clks 9>, <&clks 11>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + can1: can@401be000 { + compatible = "nxp,s32g2-flexcan"; + reg = <0x401be000 0xa000>; + interrupts = , + , + , + ; + interrupt-names = "mb-0", "state", "berr", "mb-1"; + clocks = <&clks 9>, <&clks 11>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + uart0: serial@401c8000 { compatible = "nxp,s32g2-linflexuart", "fsl,s32v234-linflexuart"; @@ -400,6 +426,32 @@ clock-names = "dmamux0", "dmamux1"; }; + can2: can@402a8000 { + compatible = "nxp,s32g2-flexcan"; + reg = <0x402a8000 0xa000>; + interrupts = , + , + , + ; + interrupt-names = "mb-0", "state", "berr", "mb-1"; + clocks = <&clks 9>, <&clks 11>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + can3: can@402b2000 { + compatible = "nxp,s32g2-flexcan"; + reg = <0x402b2000 0xa000>; + interrupts = , + , + , + ; + interrupt-names = "mb-0", "state", "berr", "mb-1"; + clocks = <&clks 9>, <&clks 11>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + uart2: serial@402bc000 { compatible = "nxp,s32g2-linflexuart", "fsl,s32v234-linflexuart"; diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi index d849edfd26f5..991dbfbfa203 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -391,6 +391,34 @@ clock-names = "dmamux0", "dmamux1"; }; + can0: can@401b4000 { + compatible = "nxp,s32g3-flexcan", + "nxp,s32g2-flexcan"; + reg = <0x401b4000 0xa000>; + interrupts = , + , + , + ; + interrupt-names = "mb-0", "state", "berr", "mb-1"; + clocks = <&clks 9>, <&clks 11>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + can1: can@401be000 { + compatible = "nxp,s32g3-flexcan", + "nxp,s32g2-flexcan"; + reg = <0x401be000 0xa000>; + interrupts = , + , + , + ; + interrupt-names = "mb-0", "state", "berr", "mb-1"; + clocks = <&clks 9>, <&clks 11>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + uart0: serial@401c8000 { compatible = "nxp,s32g3-linflexuart", "fsl,s32v234-linflexuart"; @@ -460,6 +488,34 @@ clock-names = "dmamux0", "dmamux1"; }; + can2: can@402a8000 { + compatible = "nxp,s32g3-flexcan", + "nxp,s32g2-flexcan"; + reg = <0x402a8000 0xa000>; + interrupts = , + , + , + ; + interrupt-names = "mb-0", "state", "berr", "mb-1"; + clocks = <&clks 9>, <&clks 11>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + can3: can@402b2000 { + compatible = "nxp,s32g3-flexcan", + "nxp,s32g2-flexcan"; + reg = <0x402b2000 0xa000>; + interrupts = , + , + , + ; + interrupt-names = "mb-0", "state", "berr", "mb-1"; + clocks = <&clks 9>, <&clks 11>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + uart2: serial@402bc000 { compatible = "nxp,s32g3-linflexuart", "fsl,s32v234-linflexuart"; diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi index a44eff28073a..d26af0fb8be7 100644 --- a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi +++ b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi @@ -8,6 +8,60 @@ */ &pinctrl { + can0_pins: can0-pins { + can0-grp0 { + pinmux = <0x2c1>; + output-enable; + slew-rate = <133>; + }; + + can0-grp1 { + pinmux = <0x2b0>; + input-enable; + slew-rate = <133>; + }; + + can0-grp2 { + pinmux = <0x2012>; + }; + }; + + can2_pins: can2-pins { + can2-grp0 { + pinmux = <0x1b2>; + output-enable; + slew-rate = <133>; + }; + + can2-grp1 { + pinmux = <0x1c0>; + input-enable; + slew-rate = <133>; + }; + + can2-grp2 { + pinmux = <0x2782>; + }; + }; + + can3_pins: can3-pins { + can3-grp0 { + pinmux = <0x192>; + output-enable; + slew-rate = <133>; + }; + + can3-grp1 { + pinmux = <0x1a0>; + input-enable; + slew-rate = <133>; + }; + + can3-grp2 { + pinmux = <0x2792>; + }; + }; + i2c0_pins: i2c0-pins { i2c0-grp0 { pinmux = <0x101>, <0x111>; @@ -121,6 +175,24 @@ }; }; +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&can0_pins>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&can2_pins>; + status = "okay"; +}; + +&can3 { + pinctrl-names = "default"; + pinctrl-0 = <&can3_pins>; + status = "okay"; +}; + &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&i2c0_pins>; diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi index 91fd8dbf2224..ba53ec622f0b 100644 --- a/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi +++ b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi @@ -8,6 +8,42 @@ */ &pinctrl { + can0_pins: can0-pins { + can0-grp0 { + pinmux = <0x112>; + output-enable; + slew-rate = <133>; + }; + + can0-grp1 { + pinmux = <0x120>; + input-enable; + slew-rate = <133>; + }; + + can0-grp2 { + pinmux = <0x2013>; + }; + }; + + can1_pins: can1-pins { + can1-grp0 { + pinmux = <0x132>; + output-enable; + slew-rate = <133>; + }; + + can1-grp1 { + pinmux = <0x140>; + input-enable; + slew-rate = <133>; + }; + + can1-grp2 { + pinmux = <0x2772>; + }; + }; + i2c0_pins: i2c0-pins { i2c0-grp0 { pinmux = <0x1f2>, <0x201>; @@ -93,6 +129,18 @@ }; }; +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&can0_pins>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&can1_pins>; + status = "okay"; +}; + &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&i2c0_pins>; From e6303798b6ac4b5241d74e5751346161af37d55d Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Mon, 24 Feb 2025 16:00:14 +0100 Subject: [PATCH 75/84] arm64: dts: imx8mp-tqma8mpql-mba8mpxl: change sound card model name The card name for ALSA is generated from the model name string and is limited to 16 characters. Use a shorter name to prevent cutting the name. Since nearly all starter kit mainboards for i.MX based SoM by TQ-Systems use the same codec with the same routing on board it is a good idea to use the same model name for the sound card. This allows sharing a default asound.conf in BSP over all the kits. Signed-off-by: Markus Niebel Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts index ae64731266f3..23c612e80dd3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts @@ -234,7 +234,7 @@ sound { compatible = "fsl,imx-audio-tlv320aic32x4"; - model = "tq-tlv320aic32x"; + model = "tqm-tlv320aic32"; audio-cpu = <&sai3>; audio-codec = <&tlv320aic3x04>; }; From 15aca1284e1fa469be5cc3fe8baca18108ecf18b Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Mon, 24 Feb 2025 16:00:15 +0100 Subject: [PATCH 76/84] arm64: dts: mba8mx: change sound card model name The card name for ALSA is generated from the model name string and is limited to 16 characters. Use a shorter name to prevent cutting the name. Since nearly all starter kit mainboards for i.MX based SoM by TQ-Systems use the same codec with the same routing on board it is a good idea to use the same model name for the sound card. This allows sharing a default asound.conf in BSP over all the kits. Signed-off-by: Markus Niebel Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/mba8mx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/mba8mx.dtsi b/arch/arm64/boot/dts/freescale/mba8mx.dtsi index 58e3865c2889..7ee1228a50f4 100644 --- a/arch/arm64/boot/dts/freescale/mba8mx.dtsi +++ b/arch/arm64/boot/dts/freescale/mba8mx.dtsi @@ -138,7 +138,7 @@ sound { compatible = "fsl,imx-audio-tlv320aic32x4"; - model = "imx-audio-tlv320aic32x4"; + model = "tqm-tlv320aic32"; ssi-controller = <&sai3>; audio-codec = <&tlv320aic3x04>; }; From 03d6b803e14fd259dbfdf76fd6ceb09399161434 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 24 Feb 2025 14:33:07 -0500 Subject: [PATCH 77/84] arm64: dts: im8mq-librem5: move dwc3 usb port under ports Move port@0 and port@1 under ports to fix below DTB_CHECK warnings. arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dtb: usb@38100000: port@0:reg:0:0: 0 is less than the minimum of 1 from schema $id: http://devicetree.org/schemas/usb/snps,dwc3.yaml# arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dtb: usb@38100000: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'dr_mode', 'phy-names', 'phys', 'port@0', 'port@1', 'snps,parkmode-disable-ss-quirk' were unexpected) from schema $id: http://devicetree.org/schemas/usb/snps,dwc3.yaml# Signed-off-by: Frank Li Acked-by: Rob Herring (Arm) Signed-off-by: Shawn Guo --- .../dts/freescale/imx8mq-librem5-devkit.dts | 25 +++++++++++-------- .../boot/dts/freescale/imx8mq-librem5.dtsi | 25 +++++++++++-------- 2 files changed, 28 insertions(+), 22 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts index 9d8e7231b7c6..d9f203c79519 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts @@ -979,24 +979,27 @@ }; &usb_dwc3_0 { - #address-cells = <1>; - #size-cells = <0>; dr_mode = "otg"; status = "okay"; - port@0 { - reg = <0>; + ports { + #address-cells = <1>; + #size-cells = <0>; - typec_hs: endpoint { - remote-endpoint = <&usb_con_hs>; + port@0 { + reg = <0>; + + typec_hs: endpoint { + remote-endpoint = <&usb_con_hs>; + }; }; - }; - port@1 { - reg = <1>; + port@1 { + reg = <1>; - typec_ss: endpoint { - remote-endpoint = <&usb_con_ss>; + typec_ss: endpoint { + remote-endpoint = <&usb_con_ss>; + }; }; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index c19ffa8e8a79..9e0e2d7271ef 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -1321,25 +1321,28 @@ }; &usb_dwc3_0 { - #address-cells = <1>; - #size-cells = <0>; dr_mode = "otg"; usb-role-switch; status = "okay"; - port@0 { - reg = <0>; + ports { + #address-cells = <1>; + #size-cells = <0>; - typec_hs: endpoint { - remote-endpoint = <&usb_con_hs>; + port@0 { + reg = <0>; + + typec_hs: endpoint { + remote-endpoint = <&usb_con_hs>; + }; }; - }; - port@1 { - reg = <1>; + port@1 { + reg = <1>; - typec_ss: endpoint { - remote-endpoint = <&usb_con_ss>; + typec_ss: endpoint { + remote-endpoint = <&usb_con_ss>; + }; }; }; }; From 0b4c46f9ad79c03f4cebb948f9eee1b2753fdfb6 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 25 Feb 2025 11:27:22 +0100 Subject: [PATCH 78/84] arm64: dts: imx8qm-ss-hsio: Wire up DMA IRQ for PCIe IRQ mapping is already present. Add the missing DMA interrupt. This is similar to commit 9d9c56025e429 ("arm64: dts: imx8-ss-hsio: Wire up DMA IRQ for PCIe") Signed-off-by: Alexander Stein Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi index d52609e4fc45..e80f722dbe65 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi @@ -69,8 +69,9 @@ ranges = <0x81000000 0 0x00000000 0x8ff80000 0 0x00010000>, <0x82000000 0 0x80000000 0x80000000 0 0x0ff00000>; #interrupt-cells = <1>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + ; + interrupt-names = "msi", "dma"; #address-cells = <3>; #size-cells = <2>; clocks = <&pcieb_lpcg IMX_LPCG_CLK_6>, From bcd240b231650c49ad500ce7887ab8657b0dd7b0 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 25 Feb 2025 11:27:23 +0100 Subject: [PATCH 79/84] arm64: dts: mba8xx: Remove invalid property disable-gpio disable-gpio is an (old) downstream kernel property, which slipped into DT. Remove it. Fixes: c01a26b8897a ("arm64: dts: mba8xx: Add PCIe support") Signed-off-by: Alexander Stein Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/mba8xx.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/mba8xx.dtsi b/arch/arm64/boot/dts/freescale/mba8xx.dtsi index 117f65728319..c4b5663949ad 100644 --- a/arch/arm64/boot/dts/freescale/mba8xx.dtsi +++ b/arch/arm64/boot/dts/freescale/mba8xx.dtsi @@ -328,7 +328,6 @@ pinctrl-0 = <&pinctrl_pcieb>; pinctrl-names = "default"; reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; - disable-gpio = <&expander 7 GPIO_ACTIVE_LOW>; vpcie-supply = <®_pcie_1v5>; status = "okay"; }; From 3c8d7b5d2bed442b5e85f88d9338b8afcb83dab8 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Tue, 25 Feb 2025 12:08:02 -0500 Subject: [PATCH 80/84] arm64: dts: imx95: add ref clock for pcie nodes Add "ref" clock for i.MX95's pcie and fix below CHECK_DTBS warnings: arch/arm64/boot/dts/freescale/imx95-19x19-evk.dtb: pcie@4c300000: clock-names: ['pcie', 'pcie_bus', 'pcie_phy', 'pcie_aux'] is too short from schema $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx95.dtsi | 25 ++++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index 51625bc9154e..9bb26b466a06 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -291,6 +291,13 @@ clock-output-names = "sai5_mclk"; }; + clk_sys100m: clock-sys100m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "clk_sys100m"; + }; + osc_24m: clock-24m { compatible = "fixed-clock"; #clock-cells = <0>; @@ -1595,6 +1602,14 @@ }; }; + hsio_blk_ctl: syscon@4c0100c0 { + compatible = "nxp,imx95-hsio-blk-ctl", "syscon"; + reg = <0x0 0x4c0100c0 0x0 0x1>; + #clock-cells = <1>; + clocks = <&clk_sys100m>; + power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; + }; + usb3_phy: phy@4c1f0040 { compatible = "fsl,imx95-usb-phy", "fsl,imx8mp-usb-phy"; reg = <0x0 0x4c1f0040 0x0 0x40>, @@ -1633,8 +1648,9 @@ clocks = <&scmi_clk IMX95_CLK_HSIO>, <&scmi_clk IMX95_CLK_HSIOPLL>, <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, - <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; - clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>, + <&hsio_blk_ctl 0>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref"; assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, <&scmi_clk IMX95_CLK_HSIOPLL>, <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; @@ -1706,8 +1722,9 @@ clocks = <&scmi_clk IMX95_CLK_HSIO>, <&scmi_clk IMX95_CLK_HSIOPLL>, <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, - <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; - clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>, + <&hsio_blk_ctl 0>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref"; assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, <&scmi_clk IMX95_CLK_HSIOPLL>, <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; From 8255de389dbc2f67ce068ecc423b17c3adb122fe Mon Sep 17 00:00:00 2001 From: Frank Li Date: Tue, 25 Feb 2025 14:21:58 -0500 Subject: [PATCH 81/84] arm64: dts: imx93: add ddr edac support Add ddr edac support for imx93. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index 56766fdb0b1e..64cd0776b43d 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -1334,6 +1334,14 @@ #index-cells = <1>; }; + memory-controller@4e300000 { + compatible = "nxp,imx9-memory-controller"; + reg = <0x4e300000 0x800>, <0x4e301000 0x1000>; + reg-names = "ctrl", "inject"; + interrupts = ; + little-endian; + }; + ddr-pmu@4e300dc0 { compatible = "fsl,imx93-ddr-pmu"; reg = <0x4e300dc0 0x200>; From cfe47a3d3f7440cd1bdf2a169b325257eba01534 Mon Sep 17 00:00:00 2001 From: Laurentiu Mihalcea Date: Wed, 26 Feb 2025 11:45:12 -0500 Subject: [PATCH 82/84] arm64: dts: imx8mp: add AUDIO_AXI_CLK_ROOT to AUDIOMIX block Needed because the DSP and OCRAM_A components from AUDIOMIX are clocked by AUDIO_AXI_CLK_ROOT instead of AUDIO_AHB_CLK_ROOT. Fixes: b86c3afabb4f ("arm64: dts: imx8mp: Add SAI, SDMA, AudioMIX") Signed-off-by: Laurentiu Mihalcea Reviewed-by: Iuliana Prodan Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index aeaa6a5c2f56..abb272682deb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1619,10 +1619,11 @@ <&clk IMX8MP_CLK_SAI3>, <&clk IMX8MP_CLK_SAI5>, <&clk IMX8MP_CLK_SAI6>, - <&clk IMX8MP_CLK_SAI7>; + <&clk IMX8MP_CLK_SAI7>, + <&clk IMX8MP_CLK_AUDIO_AXI_ROOT>; clock-names = "ahb", "sai1", "sai2", "sai3", - "sai5", "sai6", "sai7"; + "sai5", "sai6", "sai7", "axi"; power-domains = <&pgc_audio>; assigned-clocks = <&clk IMX8MP_AUDIO_PLL1>, <&clk IMX8MP_AUDIO_PLL2>; From c54e2f908da30a6c66195a6d0aba6412c673ec2c Mon Sep 17 00:00:00 2001 From: Laurentiu Mihalcea Date: Wed, 26 Feb 2025 11:45:13 -0500 Subject: [PATCH 83/84] arm64: dts: imx8mp: change AUDIO_AXI_CLK_ROOT freq. to 800MHz AUDIO_AXI_CLK_ROOT can't run at currently requested 600MHz w/ its parent SYS_PLL1 configured at 800MHz. Configure it to run at 800MHz as some applications running on the DSP expect the core to run at this frequency anyways. This change also affects the AUDIOMIX NoC. Fixes: b739681b3f8b ("arm64: dts: imx8mp: Fix SDMA2/3 clocks") Signed-off-by: Laurentiu Mihalcea Reviewed-by: Iuliana Prodan Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index abb272682deb..ce6793b2d57e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -834,7 +834,7 @@ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, <&clk IMX8MP_SYS_PLL1_800M>; assigned-clock-rates = <400000000>, - <600000000>; + <800000000>; }; pgc_gpu2d: power-domain@6 { From 5a690619426fc4b09c7fd3f40d3a69264ef3db0f Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Fri, 28 Feb 2025 16:13:51 +0100 Subject: [PATCH 84/84] arm64: dts: imx8qm-apalis: Remove compatible from SoM dtsi The SoM cannot be used standalone, this compatible is invalid and it is always overwritten when this .dtsi file is included, remove it therefore. Signed-off-by: Francesco Dolcini Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1.dtsi | 2 -- arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi | 2 -- 2 files changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1.dtsi index 81ba8b2831ac..b1c3f331c4ed 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1.dtsi @@ -9,8 +9,6 @@ / { model = "Toradex Apalis iMX8QM V1.1"; - compatible = "toradex,apalis-imx8-v1.1", - "fsl,imx8qm"; }; /* TODO: Cooling Maps */ diff --git a/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi index 4d6427fbe875..c18f57039f6e 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi @@ -7,8 +7,6 @@ / { model = "Toradex Apalis iMX8QM"; - compatible = "toradex,apalis-imx8", - "fsl,imx8qm"; }; ðphy0 {