From c837228adb0335580de55c1b6d6023b5ee47bb80 Mon Sep 17 00:00:00 2001 From: Heinrich Toews Date: Tue, 17 Feb 2026 14:33:03 +0100 Subject: [PATCH] spi: spi-cadence-quadspi: mram: update to VCR0 reg Signed-off-by: Heinrich Toews --- drivers/mtd/spi-nor/everspin.c | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/mtd/spi-nor/everspin.c b/drivers/mtd/spi-nor/everspin.c index 796844272325..284c88183c63 100644 --- a/drivers/mtd/spi-nor/everspin.c +++ b/drivers/mtd/spi-nor/everspin.c @@ -11,8 +11,8 @@ /* Opcodes and Register Definitions */ #define SPINOR_OP_EVERSPIN_WRAR 0x71 /* Write Any Register */ #define SPINOR_OP_EVERSPIN_RDAR 0x65 /* Read Any Register */ -#define SPINOR_REG_EVERSPIN_CFR1V 0x00800002 /* Volatile CFR1 Address */ -#define EVERSPIN_OCTAL_STR_ENABLE 0x01 /* Value for Octal STR Mode */ +#define SPINOR_REG_EVERSPIN_VCR0 0x000000 /* Volatile Config Register 0 */ +#define EVERSPIN_OCTAL_STR_B7 0xB7 /* Octal STR with Data Strobe */ /** * everspin_mram_write_reg - Helper to write to volatile/non-volatile registers @@ -26,6 +26,10 @@ static int everspin_mram_write_reg(struct spi_nor *nor, u32 addr, u8 val) SPI_MEM_OP_DATA_OUT(1, nor->bouncebuf, 1)); nor->bouncebuf[0] = val; + + /* Send WREN before EVERY register write */ + spi_nor_write_enable(nor); + return spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); } @@ -98,24 +102,22 @@ static void everspin_mram_default_init(struct spi_nor *nor) } } - /* 2. Switch to Octal Mode via CFR1V */ - dev_info(nor->dev, "Setting CFR1V to Octal STR...\n"); + /* 2. Switch to Octal Mode using the correct VCR0 address and value */ + dev_info(nor->dev, "Setting VCR0 to Octal STR (0xB7) at address 0x000000...\n"); - /* IMPORTANT: Every write access to registers needs WREN first */ - spi_nor_write_enable(nor); + /* IMPORTANT: Use 0xB7 for Octal with Data Strobe */ + ret = everspin_mram_write_reg(nor, SPINOR_REG_EVERSPIN_VCR0, EVERSPIN_OCTAL_STR_B7); - ret = everspin_mram_write_reg(nor, SPINOR_REG_EVERSPIN_CFR1V, EVERSPIN_OCTAL_STR_ENABLE); if (ret) { - dev_err(nor->dev, "Error writing CFR1V register (%d)\n", ret); + dev_err(nor->dev, "Error writing VCR0 register (%d)\n", ret); } else { - dev_info(nor->dev, "CFR1V successfully set to Octal STR.\n"); - + dev_info(nor->dev, "VCR0 successfully set to Octal STR.\n"); /* Give the chip a few microseconds to settle the new mode */ udelay(100); /* Read SR1 again to see if WEL is cleared after CFR1V write */ spi_nor_read_any_reg(nor, &op, nor->reg_proto); - dev_info(nor->dev, "SR1 after CFR1V write: 0x%02x\n", nor->bouncebuf[0]); + dev_info(nor->dev, "SR1 after VCR0 write: 0x%02x\n", nor->bouncebuf[0]); } /* 3. Synchronize kernel parameters */