From c79cf2c1a8aedb4faec6d8924d854edfaaa64e67 Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Wed, 11 May 2022 15:25:38 +0800 Subject: [PATCH] phy: rockchip: naneng-combphy: Set gate_tx_pck_sel length select work for L1SS This configuration is required for Gen1 l1ss support. Change-Id: I921d1551dbbb4e85f823ce9ce0abbb96198d2ccf Signed-off-by: Jon Lin --- drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index c9e45cce9886..0351ed80aafe 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -775,6 +775,10 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv) case 100000000: param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); if (priv->mode == PHY_TYPE_PCIE) { + /* gate_tx_pck_sel length select work for L1SS */ + val = 0xc0; + writel(val, priv->mmio + 0x74); + /* PLL KVCO tuning fine */ val = readl(priv->mmio + (0x20 << 2)); val &= ~GENMASK(4, 2);