From b8ab89d4ca8cf693af4f1925af15a7419901a45a Mon Sep 17 00:00:00 2001 From: Heinrich Toews Date: Thu, 19 Feb 2026 17:02:32 +0100 Subject: [PATCH] successful write enable test with 8s-8s-8s Signed-off-by: Heinrich Toews --- drivers/mtd/spi-nor/everspin.c | 63 +++++++++++++++++++++------------- 1 file changed, 40 insertions(+), 23 deletions(-) diff --git a/drivers/mtd/spi-nor/everspin.c b/drivers/mtd/spi-nor/everspin.c index ea91e804d4ee..64170928f25b 100644 --- a/drivers/mtd/spi-nor/everspin.c +++ b/drivers/mtd/spi-nor/everspin.c @@ -173,47 +173,64 @@ static void everspin_mram_default_init(struct spi_nor *nor) } /** - * everspin_mram_late_init - Bypassing Kernel 6.6 restrictions on 8-8-8 modes + * everspin_mram_late_init - Bypassing 6.6 core and debugging Octal WREN */ static int everspin_mram_late_init(struct spi_nor *nor) { struct spi_nor_flash_parameter *params = nor->params; + struct spi_mem_op op; + int ret; + u8 status; - dev_info(nor->dev, "Finalizing Everspin MRAM: Forcing 8s-8s-8s STR mode via bypass...\n"); + dev_info(nor->dev, "Finalizing Everspin MRAM: Starting Octal WREN Debug...\n"); - /* - * 1. Enable standard caps that are NOT blocked by SNOR_HWCAPS_X_X_X. - * We use READ (1-1-1) and PP_1_1_8 (1-1-8) as safe carriers. - */ - params->hwcaps.mask |= SNOR_HWCAPS_READ | SNOR_HWCAPS_PP_1_1_8; - - /* - * 2. Directly assign Octal STR settings to the 'nor' structure. - * This ensures the MTD layer uses 8-8-8 for every access. - */ + /* 1. Preliminary Setup (as discussed) */ + params->hwcaps.mask |= SNOR_HWCAPS_READ | SNOR_HWCAPS_PP; nor->read_opcode = 0xCB; nor->read_proto = SNOR_PROTO_8_8_8; nor->read_dummy = 8; - nor->program_opcode = 0x82; nor->write_proto = SNOR_PROTO_8_8_8; - nor->reg_proto = SNOR_PROTO_8_8_8; nor->addr_nbytes = 3; + params->rdsr_dummy = 8; /* Required for RDSR in Octal mode */ /* - * 3. Map our 8-8-8 configuration to the allowed slots. - * Even if the core re-runs the selection, it will pick these settings. + * 2. DEBUG: Manual Write Enable (WREN) in Octal-STR (8-8-8) */ - spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ], - 0, 8, 0xCB, SNOR_PROTO_8_8_8); + op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WREN, 8), + SPI_MEM_OP_NO_ADDR, + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_NO_DATA); - /* We use the PP_1_1_8 slot because it is not in the X_X_X mask */ - spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_1_1_8], - 0x82, SNOR_PROTO_8_8_8); + ret = spi_nor_write_any_volatile_reg(nor, &op, SNOR_PROTO_8_8_8); + if (ret) { + dev_err(nor->dev, "Octal WREN (06h) command failed to execute!\n"); + return ret; + } - /* Ensure we prefer our fake 1-1-8 (which is actually 8-8-8) over standard 1-1-1 */ - params->hwcaps.mask &= ~SNOR_HWCAPS_PP; + /* + * 3. DEBUG: Check Status Register 1 (RDSR 05h) for WEL bit + * WEL is Bit 1 (0x02). + */ + op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR, 8), + SPI_MEM_OP_NO_ADDR, + SPI_MEM_OP_DUMMY(8, 8), /* 8 dummy cycles for 8-8-8 */ + SPI_MEM_OP_DATA_IN(1, nor->bouncebuf, 8)); + + ret = spi_nor_read_any_reg(nor, &op, SNOR_PROTO_8_8_8); + status = nor->bouncebuf[0]; + + if (ret || !(status & 0x02)) { + dev_err(nor->dev, "Octal WEL check FAILED! SR1: 0x%02x (WEL bit 1 should be SET)\n", status); + /* If this fails, the Page Program (0x82) will always time out! */ + } else { + dev_info(nor->dev, "Octal WEL check SUCCESS! SR1: 0x%02x (Write Enabled)\n", status); + } + + /* 4. Map settings to standard slots for MTD operation */ + spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ], 0, 8, 0xCB, SNOR_PROTO_8_8_8); + spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP], 0x82, SNOR_PROTO_8_8_8); return 0; }