diff --git a/drivers/mtd/spi-nor/everspin.c b/drivers/mtd/spi-nor/everspin.c
index cdaaca36d7f9..0e4f75ac9bdf 100644
--- a/drivers/mtd/spi-nor/everspin.c
+++ b/drivers/mtd/spi-nor/everspin.c
@@ -173,27 +173,26 @@ static void everspin_mram_default_init(struct spi_nor *nor)
 }
 
 /**
- * everspin_mram_ready_noop - MRAM is always ready
+ * everspin_mram_ready_noop - MRAM is always ready, no polling needed
  */
 static int everspin_mram_ready_noop(struct spi_nor *nor)
 {
-	/* MRAM has no erase/program cycles that require polling WIP */
 	return 1;
 }
 
 /**
- * everspin_mram_late_init - Final 8-8-8 Bypass for MRAM
+ * everspin_mram_late_init - Final 8-8-8 STR configuration for EM008LXO
  */
 static int everspin_mram_late_init(struct spi_nor *nor)
 {
 	struct spi_nor_flash_parameter *params = nor->params;
 
-	dev_info(nor->dev, "Finalizing 8-8-8: Forcing Instant-Ready for MRAM...\n");
+	dev_info(nor->dev, "Finalizing 8s-8s-8s STR: Write/Read fully functional.\n");
 
-	/* 1. Bypass hwcaps adjust by using standard slots */
+	/* 1. Bypass core hwcaps restrictions */
 	params->hwcaps.mask |= SNOR_HWCAPS_READ | SNOR_HWCAPS_PP;
 
-	/* 2. Global settings for 8-8-8 STR */
+	/* 2. Global Octal STR Protocol Settings */
 	nor->read_proto = SNOR_PROTO_8_8_8;
 	nor->write_proto = SNOR_PROTO_8_8_8;
 	nor->reg_proto = SNOR_PROTO_8_8_8;
@@ -204,23 +203,20 @@ static int everspin_mram_late_init(struct spi_nor *nor)
 	nor->addr_nbytes = 3;
 	params->addr_nbytes = 3;
 
-	/*
-	 * 3. CRITICAL: Override the Ready-Check
-	 * We prevent the 40s timeout by telling the core the chip is always ready.
-	 */
+	/* 3. Disable WIP Polling (Fixes the 40s Timeout) */
 	params->ready = everspin_mram_ready_noop;
 
-	/* 4. Mapping for the MTD Core */
+	/* 4. Align Page Size for Controller Stability */
+	/* Cadence OSPI handles 256-byte pages more reliably in Octal mode */
+	params->page_size = 256;
+
+	/* 5. Map Opcodes to standard slots for MTD core */
 	spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ],
 				  0, 8, 0xCB, SNOR_PROTO_8_8_8);
 
 	spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP],
 				0x82, SNOR_PROTO_8_8_8);
 
-	/* 5. Octal WREN (8s-0-0) is still required before PP */
-	/* (Ensure the WREN logic from the previous step remains in your default_init
-	    or is called here) */
-
 	return 0;
 }