diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-maxim-max96756-dphy0.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-maxim-max96756-dphy0.dtsi
new file mode 100644
index 000000000000..888e42607177
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-maxim-max96756-dphy0.dtsi
@@ -0,0 +1,199 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+/ {
+	max96756_dphy0_osc: max96712-dphy0-oscillator@0 {
+		compatible = "fixed-clock";
+		#clock-cells = <1>;
+		clock-frequency  = <25000000>;
+		clock-output-names = "max96756-dphy0-osc";
+	};
+
+	max96756_dphy0_vcc1v2: max96756-dphy0-vcc1v2 {
+		compatible = "regulator-fixed";
+		regulator-name = "max96756_dphy0_vcc1v2";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1200000>;
+		startup-delay-us = <850>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	max96756_dphy0_vcc1v8: max96756-dphy0-vcc1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "max96756_dphy0_vcc1v8";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		startup-delay-us = <200>;
+		vin-supply = <&vcc_3v3_s3>;
+	};
+};
+
+/**
+ * ============================================================================
+ * Info DPHY0
+ * ============================================================================
+ */
+&csi2_dphy0_hw {
+	status = "okay";
+};
+
+&csi2_dphy0 {
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		port@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mipi_dphy0_in_max96756: endpoint@1 {
+				reg = <1>;
+				remote-endpoint = <&max96756_dphy0_out>;
+				data-lanes = <1 2 3 4>;
+			};
+		};
+		port@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			csidphy0_out: endpoint@0 {
+				reg = <0>;
+				remote-endpoint = <&mipi2_csi2_input>;
+			};
+		};
+	};
+};
+
+&i2c7 {
+	status = "okay";
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c7m3_xfer>;
+
+	max96756: max96756@48 {
+		compatible = "maxim,max96756";
+		status = "okay";
+		reg = <0x48>;
+
+		clock-names = "xvclk";
+		clocks = <&max96756_dphy0_osc 0>;
+		power-domains = <&power RK3588_PD_VI>;
+		rockchip,grf = <&sys_grf>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&max96756_dphy0_pwdn>, <&max96756_dphy0_errb>, <&max96756_dphy0_lock>;
+
+		pwdn-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
+		lock-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>;
+
+		vcc1v2-supply = <&max96756_dphy0_vcc1v2>;
+		vcc1v8-supply = <&max96756_dphy0_vcc1v8>;
+
+		rockchip,camera-module-index = <0>;
+		rockchip,camera-module-facing = "back";
+		rockchip,camera-module-name = "max96756";
+		rockchip,camera-module-lens-name = "max96756";
+
+		port {
+			max96756_dphy0_out: endpoint {
+				remote-endpoint = <&mipi_dphy0_in_max96756>;
+				data-lanes = <1 2 3 4>;
+			};
+		};
+	};
+};
+
+&mipi2_csi2 {
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mipi2_csi2_input: endpoint@1 {
+				reg = <1>;
+				remote-endpoint = <&csidphy0_out>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mipi2_csi2_output: endpoint@0 {
+				reg = <0>;
+				remote-endpoint = <&cif_mipi2_in>;
+			};
+		};
+	};
+};
+
+&rkcif_mipi_lvds2 {
+	status = "okay";
+	/* parameters for do cif reset detecting:
+	 * index0: monitor mode,
+		   0 for idle,
+		   1 for continue,
+		   2 for trigger,
+		   3 for hotplug (for nextchip)
+	 * index1: the frame id to start timer,
+		   min is 2
+	 * index2: frame num of monitoring cycle
+	 * index3: err time for keep monitoring
+		   after finding out err (ms)
+	 * index4: csi2 err reference val for resetting
+	 */
+	rockchip,cif-monitor = <3 2 1 1000 5>;
+
+	port {
+		cif_mipi2_in: endpoint {
+			remote-endpoint = <&mipi2_csi2_output>;
+		};
+	};
+};
+
+/**
+ * =============================================================================
+ * Common
+ * =============================================================================
+ */
+&rkcif {
+	status = "okay";
+	rockchip,android-usb-camerahal-enable;
+};
+
+&rkcif_mmu {
+	status = "okay";
+};
+
+&pinctrl {
+	max96756-dphy0 {
+		max96756_dphy0_pwdn: max96756-dphy0-pwdn {
+			rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_output_low>;
+		};
+
+		max96756_dphy0_errb: max96756-dphy0-errb {
+			rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none_smt>;
+		};
+
+		max96756_dphy0_lock: max96756-dphy0-lock {
+			rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none_smt>;
+		};
+	};
+};