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clk: samsung: exynos5433: Add clocks for CMU_G2D domain

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This patch adds ths mux/divider/gate clocks of CMU_G2D domain which
includes G2D/MDMA IPs. The CMU_G2D requires its parent defined in
the CMU_TOP domain. Hence this patch adds G2D related clocks to the
CMU_TOP domain.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This commit is contained in:
Chanwoo Choi
2015-02-02 23:24:00 +09:00
committed by Sylwester Nawrocki
parent 56bcf3f3ea
commit a29308dad5
2 changed files with 187 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files
include/dt-bindings/clock/exynos5433.h
+41 -1
View File
@@ -100,6 +100,12 @@
#define CLK_DIV_SCLK_PCM1 128
#define CLK_DIV_SCLK_AUDIO1 129
#define CLK_DIV_SCLK_AUDIO0 130
#define CLK_DIV_ACLK_GSCL_111 131
#define CLK_DIV_ACLK_GSCL_333 132
#define CLK_DIV_ACLK_HEVC_400 133
#define CLK_DIV_ACLK_MFC_400 134
#define CLK_DIV_ACLK_G2D_266 135
#define CLK_DIV_ACLK_G2D_400 136
#define CLK_ACLK_PERIC_66 200
#define CLK_ACLK_PERIS_66 201
@@ -121,8 +127,10 @@
#define CLK_SCLK_SLIMBUS 217
#define CLK_SCLK_AUDIO1 218
#define CLK_SCLK_AUDIO0 219
#define CLK_ACLK_G2D_266 220
#define CLK_ACLK_G2D_400 221
#define TOP_NR_CLK 220
#define TOP_NR_CLK 222
/* CMU_CPIF */
#define CLK_FOUT_MPHY_PLL 1
@@ -286,4 +294,36 @@
#define FSYS_NR_CLK 66
/* CMU_G2D */
#define CLK_MUX_ACLK_G2D_266_USER 1
#define CLK_MUX_ACLK_G2D_400_USER 2
#define CLK_DIV_PCLK_G2D 3
#define CLK_ACLK_SMMU_MDMA1 4
#define CLK_ACLK_BTS_MDMA1 5
#define CLK_ACLK_BTS_G2D 6
#define CLK_ACLK_ALB_G2D 7
#define CLK_ACLK_AXIUS_G2DX 8
#define CLK_ACLK_ASYNCAXI_SYSX 9
#define CLK_ACLK_AHB2APB_G2D1P 10
#define CLK_ACLK_AHB2APB_G2D0P 11
#define CLK_ACLK_XIU_G2DX 12
#define CLK_ACLK_G2DNP_133 13
#define CLK_ACLK_G2DND_400 14
#define CLK_ACLK_MDMA1 15
#define CLK_ACLK_G2D 16
#define CLK_ACLK_SMMU_G2D 17
#define CLK_PCLK_SMMU_MDMA1 18
#define CLK_PCLK_BTS_MDMA1 19
#define CLK_PCLK_BTS_G2D 20
#define CLK_PCLK_ALB_G2D 21
#define CLK_PCLK_ASYNCAXI_SYSX 22
#define CLK_PCLK_PMU_G2D 23
#define CLK_PCLK_SYSREG_G2D 24
#define CLK_PCLK_G2D 25
#define CLK_PCLK_SMMU_G2D 26
#define G2D_NR_CLK 27
#endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */