Revert "Revert "8250: add support for ASIX devices with a FIFO bug""
This reverts commit5f4a1111adwhich is commita82d62f708upstream. It changes the serial port ABI, which Android cares about. As the issue isn't really a problem at all for any Android devices, just revert it keeping the fix present for now, to preserve the abi. Bug: 161946584 Change-Id: Ie9b3f9aa8e705c63680fb9556e579e6241589d74 Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
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@@ -87,6 +87,7 @@ struct serial8250_config {
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#define UART_BUG_TXEN (1 << 1) /* UART has buggy TX IIR status */
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#define UART_BUG_TXEN (1 << 1) /* UART has buggy TX IIR status */
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#define UART_BUG_NOMSR (1 << 2) /* UART has buggy MSR status bits (Au1x00) */
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#define UART_BUG_NOMSR (1 << 2) /* UART has buggy MSR status bits (Au1x00) */
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#define UART_BUG_THRE (1 << 3) /* UART has buggy THRE reassertion */
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#define UART_BUG_THRE (1 << 3) /* UART has buggy THRE reassertion */
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#define UART_BUG_PARITY (1 << 4) /* UART mishandles parity if FIFO enabled */
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#define UART_BUG_TXRACE (1 << 5) /* UART Tx fails to set remote DR */
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#define UART_BUG_TXRACE (1 << 5) /* UART Tx fails to set remote DR */
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@@ -1044,6 +1044,14 @@ static int pci_oxsemi_tornado_init(struct pci_dev *dev)
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return number_uarts;
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return number_uarts;
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}
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}
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static int pci_asix_setup(struct serial_private *priv,
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const struct pciserial_board *board,
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struct uart_8250_port *port, int idx)
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{
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port->bugs |= UART_BUG_PARITY;
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return pci_default_setup(priv, board, port, idx);
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}
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/* Quatech devices have their own extra interface features */
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/* Quatech devices have their own extra interface features */
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struct quatech_feature {
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struct quatech_feature {
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@@ -1866,6 +1874,7 @@ pci_moxa_setup(struct serial_private *priv,
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#define PCI_DEVICE_ID_WCH_CH355_4S 0x7173
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#define PCI_DEVICE_ID_WCH_CH355_4S 0x7173
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#define PCI_VENDOR_ID_AGESTAR 0x5372
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#define PCI_VENDOR_ID_AGESTAR 0x5372
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#define PCI_DEVICE_ID_AGESTAR_9375 0x6872
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#define PCI_DEVICE_ID_AGESTAR_9375 0x6872
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#define PCI_VENDOR_ID_ASIX 0x9710
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#define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
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#define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
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#define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
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#define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
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@@ -2675,6 +2684,16 @@ static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
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.exit = pci_wch_ch38x_exit,
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.exit = pci_wch_ch38x_exit,
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.setup = pci_wch_ch38x_setup,
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.setup = pci_wch_ch38x_setup,
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},
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},
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/*
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* ASIX devices with FIFO bug
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*/
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{
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.vendor = PCI_VENDOR_ID_ASIX,
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.device = PCI_ANY_ID,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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.setup = pci_asix_setup,
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},
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/*
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/*
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* Broadcom TruManage (NetXtreme)
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* Broadcom TruManage (NetXtreme)
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*/
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*/
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@@ -2574,8 +2574,11 @@ static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
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if (c_cflag & CSTOPB)
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if (c_cflag & CSTOPB)
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cval |= UART_LCR_STOP;
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cval |= UART_LCR_STOP;
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if (c_cflag & PARENB)
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if (c_cflag & PARENB) {
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cval |= UART_LCR_PARITY;
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cval |= UART_LCR_PARITY;
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if (up->bugs & UART_BUG_PARITY)
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up->fifo_bug = true;
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}
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if (!(c_cflag & PARODD))
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if (!(c_cflag & PARODD))
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cval |= UART_LCR_EPAR;
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cval |= UART_LCR_EPAR;
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#ifdef CMSPAR
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#ifdef CMSPAR
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@@ -2738,7 +2741,8 @@ serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
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up->lcr = cval; /* Save computed LCR */
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up->lcr = cval; /* Save computed LCR */
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if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
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if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
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if (baud < 2400 && !up->dma) {
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/* NOTE: If fifo_bug is not set, a user can set RX_trigger. */
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if ((baud < 2400 && !up->dma) || up->fifo_bug) {
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up->fcr &= ~UART_FCR_TRIGGER_MASK;
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up->fcr &= ~UART_FCR_TRIGGER_MASK;
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up->fcr |= UART_FCR_TRIGGER_1;
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up->fcr |= UART_FCR_TRIGGER_1;
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}
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}
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@@ -3074,7 +3078,8 @@ static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
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struct uart_8250_port *up = up_to_u8250p(uport);
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struct uart_8250_port *up = up_to_u8250p(uport);
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int rxtrig;
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int rxtrig;
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if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
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if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 ||
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up->fifo_bug)
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return -EINVAL;
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return -EINVAL;
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rxtrig = bytes_to_fcr_rxtrig(up, bytes);
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rxtrig = bytes_to_fcr_rxtrig(up, bytes);
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@@ -97,6 +97,7 @@ struct uart_8250_port {
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struct list_head list; /* ports on this IRQ */
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struct list_head list; /* ports on this IRQ */
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u32 capabilities; /* port capabilities */
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u32 capabilities; /* port capabilities */
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unsigned short bugs; /* port bugs */
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unsigned short bugs; /* port bugs */
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bool fifo_bug; /* min RX trigger if enabled */
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unsigned int tx_loadsz; /* transmit fifo load size */
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unsigned int tx_loadsz; /* transmit fifo load size */
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unsigned char acr;
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unsigned char acr;
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unsigned char fcr;
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unsigned char fcr;
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