Merge tag 'riscv-for-linus-6.13-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-v updates from Palmer Dabbelt: - Support for pointer masking in userspace - Support for probing vector misaligned access performance - Support for qspinlock on systems with Zacas and Zabha * tag 'riscv-for-linus-6.13-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (38 commits) RISC-V: Remove unnecessary include from compat.h riscv: Fix default misaligned access trap riscv: Add qspinlock support dt-bindings: riscv: Add Ziccrse ISA extension description riscv: Add ISA extension parsing for Ziccrse asm-generic: ticket-lock: Add separate ticket-lock.h asm-generic: ticket-lock: Reuse arch_spinlock_t of qspinlock riscv: Implement xchg8/16() using Zabha riscv: Implement arch_cmpxchg128() using Zacas riscv: Improve zacas fully-ordered cmpxchg() riscv: Implement cmpxchg8/16() using Zabha dt-bindings: riscv: Add Zabha ISA extension description riscv: Implement cmpxchg32/64() using Zacas riscv: Do not fail to build on byte/halfword operations with Zawrs riscv: Move cpufeature.h macros into their own header KVM: riscv: selftests: Add Smnpm and Ssnpm to get-reg-list test RISC-V: KVM: Allow Smnpm and Ssnpm extensions for guests riscv: hwprobe: Export the Supm ISA extension riscv: selftests: Add a pointer masking test riscv: Allow ptrace control of the tagged address ABI ...
This commit is contained in:
Linus Torvalds
@@ -136,6 +136,7 @@ static __always_inline bool virt_spin_lock(struct qspinlock *lock)
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}
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#endif
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#ifndef __no_arch_spinlock_redefine
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/*
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* Remapping spinlock architecture specific functions to the corresponding
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* queued spinlock functions.
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@@ -146,5 +147,6 @@ static __always_inline bool virt_spin_lock(struct qspinlock *lock)
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#define arch_spin_lock(l) queued_spin_lock(l)
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#define arch_spin_trylock(l) queued_spin_trylock(l)
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#define arch_spin_unlock(l) queued_spin_unlock(l)
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#endif
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#endif /* __ASM_GENERIC_QSPINLOCK_H */
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@@ -1,94 +1,9 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* 'Generic' ticket-lock implementation.
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*
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* It relies on atomic_fetch_add() having well defined forward progress
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* guarantees under contention. If your architecture cannot provide this, stick
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* to a test-and-set lock.
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*
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* It also relies on atomic_fetch_add() being safe vs smp_store_release() on a
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* sub-word of the value. This is generally true for anything LL/SC although
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* you'd be hard pressed to find anything useful in architecture specifications
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* about this. If your architecture cannot do this you might be better off with
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* a test-and-set.
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*
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* It further assumes atomic_*_release() + atomic_*_acquire() is RCpc and hence
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* uses atomic_fetch_add() which is RCsc to create an RCsc hot path, along with
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* a full fence after the spin to upgrade the otherwise-RCpc
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* atomic_cond_read_acquire().
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*
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* The implementation uses smp_cond_load_acquire() to spin, so if the
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* architecture has WFE like instructions to sleep instead of poll for word
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* modifications be sure to implement that (see ARM64 for example).
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*
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*/
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#ifndef __ASM_GENERIC_SPINLOCK_H
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#define __ASM_GENERIC_SPINLOCK_H
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#include <linux/atomic.h>
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#include <asm-generic/spinlock_types.h>
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static __always_inline void arch_spin_lock(arch_spinlock_t *lock)
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{
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u32 val = atomic_fetch_add(1<<16, lock);
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u16 ticket = val >> 16;
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if (ticket == (u16)val)
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return;
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/*
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* atomic_cond_read_acquire() is RCpc, but rather than defining a
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* custom cond_read_rcsc() here we just emit a full fence. We only
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* need the prior reads before subsequent writes ordering from
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* smb_mb(), but as atomic_cond_read_acquire() just emits reads and we
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* have no outstanding writes due to the atomic_fetch_add() the extra
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* orderings are free.
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*/
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atomic_cond_read_acquire(lock, ticket == (u16)VAL);
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smp_mb();
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}
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static __always_inline bool arch_spin_trylock(arch_spinlock_t *lock)
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{
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u32 old = atomic_read(lock);
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if ((old >> 16) != (old & 0xffff))
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return false;
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return atomic_try_cmpxchg(lock, &old, old + (1<<16)); /* SC, for RCsc */
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}
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static __always_inline void arch_spin_unlock(arch_spinlock_t *lock)
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{
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u16 *ptr = (u16 *)lock + IS_ENABLED(CONFIG_CPU_BIG_ENDIAN);
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u32 val = atomic_read(lock);
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smp_store_release(ptr, (u16)val + 1);
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}
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static __always_inline int arch_spin_value_unlocked(arch_spinlock_t lock)
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{
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u32 val = lock.counter;
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return ((val >> 16) == (val & 0xffff));
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}
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static __always_inline int arch_spin_is_locked(arch_spinlock_t *lock)
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{
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arch_spinlock_t val = READ_ONCE(*lock);
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return !arch_spin_value_unlocked(val);
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}
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static __always_inline int arch_spin_is_contended(arch_spinlock_t *lock)
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{
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u32 val = atomic_read(lock);
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return (s16)((val >> 16) - (val & 0xffff)) > 1;
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}
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#include <asm-generic/ticket_spinlock.h>
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#include <asm/qrwlock.h>
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#endif /* __ASM_GENERIC_SPINLOCK_H */
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@@ -3,15 +3,7 @@
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#ifndef __ASM_GENERIC_SPINLOCK_TYPES_H
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#define __ASM_GENERIC_SPINLOCK_TYPES_H
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#include <linux/types.h>
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typedef atomic_t arch_spinlock_t;
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/*
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* qrwlock_types depends on arch_spinlock_t, so we must typedef that before the
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* include.
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*/
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#include <asm/qrwlock_types.h>
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#define __ARCH_SPIN_LOCK_UNLOCKED ATOMIC_INIT(0)
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#include <asm-generic/qspinlock_types.h>
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#include <asm-generic/qrwlock_types.h>
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#endif /* __ASM_GENERIC_SPINLOCK_TYPES_H */
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@@ -0,0 +1,105 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* 'Generic' ticket-lock implementation.
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*
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* It relies on atomic_fetch_add() having well defined forward progress
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* guarantees under contention. If your architecture cannot provide this, stick
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* to a test-and-set lock.
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*
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* It also relies on atomic_fetch_add() being safe vs smp_store_release() on a
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* sub-word of the value. This is generally true for anything LL/SC although
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* you'd be hard pressed to find anything useful in architecture specifications
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* about this. If your architecture cannot do this you might be better off with
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* a test-and-set.
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*
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* It further assumes atomic_*_release() + atomic_*_acquire() is RCpc and hence
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* uses atomic_fetch_add() which is RCsc to create an RCsc hot path, along with
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* a full fence after the spin to upgrade the otherwise-RCpc
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* atomic_cond_read_acquire().
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*
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* The implementation uses smp_cond_load_acquire() to spin, so if the
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* architecture has WFE like instructions to sleep instead of poll for word
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* modifications be sure to implement that (see ARM64 for example).
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*
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*/
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#ifndef __ASM_GENERIC_TICKET_SPINLOCK_H
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#define __ASM_GENERIC_TICKET_SPINLOCK_H
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#include <linux/atomic.h>
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#include <asm-generic/spinlock_types.h>
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static __always_inline void ticket_spin_lock(arch_spinlock_t *lock)
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{
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u32 val = atomic_fetch_add(1<<16, &lock->val);
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u16 ticket = val >> 16;
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if (ticket == (u16)val)
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return;
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/*
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* atomic_cond_read_acquire() is RCpc, but rather than defining a
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* custom cond_read_rcsc() here we just emit a full fence. We only
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* need the prior reads before subsequent writes ordering from
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* smb_mb(), but as atomic_cond_read_acquire() just emits reads and we
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* have no outstanding writes due to the atomic_fetch_add() the extra
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* orderings are free.
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*/
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atomic_cond_read_acquire(&lock->val, ticket == (u16)VAL);
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smp_mb();
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}
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static __always_inline bool ticket_spin_trylock(arch_spinlock_t *lock)
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{
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u32 old = atomic_read(&lock->val);
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if ((old >> 16) != (old & 0xffff))
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return false;
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return atomic_try_cmpxchg(&lock->val, &old, old + (1<<16)); /* SC, for RCsc */
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}
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static __always_inline void ticket_spin_unlock(arch_spinlock_t *lock)
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{
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u16 *ptr = (u16 *)lock + IS_ENABLED(CONFIG_CPU_BIG_ENDIAN);
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u32 val = atomic_read(&lock->val);
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smp_store_release(ptr, (u16)val + 1);
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}
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static __always_inline int ticket_spin_value_unlocked(arch_spinlock_t lock)
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{
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u32 val = lock.val.counter;
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return ((val >> 16) == (val & 0xffff));
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}
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static __always_inline int ticket_spin_is_locked(arch_spinlock_t *lock)
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{
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arch_spinlock_t val = READ_ONCE(*lock);
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return !ticket_spin_value_unlocked(val);
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}
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static __always_inline int ticket_spin_is_contended(arch_spinlock_t *lock)
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{
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u32 val = atomic_read(&lock->val);
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return (s16)((val >> 16) - (val & 0xffff)) > 1;
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}
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#ifndef __no_arch_spinlock_redefine
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/*
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* Remapping spinlock architecture specific functions to the corresponding
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* ticket spinlock functions.
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*/
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#define arch_spin_is_locked(l) ticket_spin_is_locked(l)
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#define arch_spin_is_contended(l) ticket_spin_is_contended(l)
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#define arch_spin_value_unlocked(l) ticket_spin_value_unlocked(l)
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#define arch_spin_lock(l) ticket_spin_lock(l)
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#define arch_spin_trylock(l) ticket_spin_trylock(l)
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#define arch_spin_unlock(l) ticket_spin_unlock(l)
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#endif
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#endif /* __ASM_GENERIC_TICKET_SPINLOCK_H */
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