Merge branch 'mips-next-3.9' of git://git.linux-mips.org/pub/scm/john/linux-john into mips-for-linux-next
This commit is contained in:
Ralf Baechle
@@ -41,11 +41,37 @@
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#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
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#define AR71XX_RESET_SIZE 0x100
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#define AR71XX_PCI_MEM_BASE 0x10000000
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#define AR71XX_PCI_MEM_SIZE 0x07000000
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#define AR71XX_PCI_WIN0_OFFS 0x10000000
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#define AR71XX_PCI_WIN1_OFFS 0x11000000
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#define AR71XX_PCI_WIN2_OFFS 0x12000000
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#define AR71XX_PCI_WIN3_OFFS 0x13000000
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#define AR71XX_PCI_WIN4_OFFS 0x14000000
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#define AR71XX_PCI_WIN5_OFFS 0x15000000
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#define AR71XX_PCI_WIN6_OFFS 0x16000000
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#define AR71XX_PCI_WIN7_OFFS 0x07000000
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#define AR71XX_PCI_CFG_BASE \
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(AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000)
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#define AR71XX_PCI_CFG_SIZE 0x100
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#define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
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#define AR7240_USB_CTRL_SIZE 0x100
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#define AR7240_OHCI_BASE 0x1b000000
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#define AR7240_OHCI_SIZE 0x1000
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#define AR724X_PCI_MEM_BASE 0x10000000
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#define AR724X_PCI_MEM_SIZE 0x04000000
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#define AR724X_PCI_CFG_BASE 0x14000000
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#define AR724X_PCI_CFG_SIZE 0x1000
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#define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000c0000)
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#define AR724X_PCI_CRP_SIZE 0x1000
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#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000)
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#define AR724X_PCI_CTRL_SIZE 0x100
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#define AR724X_EHCI_BASE 0x1b000000
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#define AR724X_EHCI_SIZE 0x1000
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@@ -68,6 +94,25 @@
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#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
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#define AR934X_SRIF_SIZE 0x1000
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#define QCA955X_PCI_MEM_BASE0 0x10000000
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#define QCA955X_PCI_MEM_BASE1 0x12000000
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#define QCA955X_PCI_MEM_SIZE 0x02000000
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#define QCA955X_PCI_CFG_BASE0 0x14000000
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#define QCA955X_PCI_CFG_BASE1 0x16000000
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#define QCA955X_PCI_CFG_SIZE 0x1000
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#define QCA955X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000)
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#define QCA955X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000)
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#define QCA955X_PCI_CRP_SIZE 0x1000
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#define QCA955X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000)
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#define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000)
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#define QCA955X_PCI_CTRL_SIZE 0x100
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#define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
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#define QCA955X_WMAC_SIZE 0x20000
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#define QCA955X_EHCI0_BASE 0x1b000000
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#define QCA955X_EHCI1_BASE 0x1b400000
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#define QCA955X_EHCI_SIZE 0x1000
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/*
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* DDR_CTRL block
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*/
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@@ -199,6 +244,41 @@
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#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
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#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
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#define QCA955X_PLL_CPU_CONFIG_REG 0x00
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#define QCA955X_PLL_DDR_CONFIG_REG 0x04
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#define QCA955X_PLL_CLK_CTRL_REG 0x08
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#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
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#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
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#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT 6
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#define QCA955X_PLL_CPU_CONFIG_NINT_MASK 0x3f
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#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
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#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
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#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
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#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3
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#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
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#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
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#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT 10
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#define QCA955X_PLL_DDR_CONFIG_NINT_MASK 0x3f
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#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
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#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
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#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
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#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
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#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
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#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
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#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
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#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
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#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
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#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
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#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
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#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
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#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
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#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
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#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
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#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
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/*
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* USB_CONFIG block
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*/
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@@ -238,6 +318,10 @@
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#define AR934X_RESET_REG_BOOTSTRAP 0xb0
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#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
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#define QCA955X_RESET_REG_RESET_MODULE 0x1c
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#define QCA955X_RESET_REG_BOOTSTRAP 0xb0
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#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac
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#define MISC_INT_ETHSW BIT(12)
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#define MISC_INT_TIMER4 BIT(10)
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#define MISC_INT_TIMER3 BIT(9)
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@@ -315,6 +399,8 @@
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#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
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#define AR934X_BOOTSTRAP_DDR1 BIT(0)
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#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4)
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#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
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#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1)
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#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
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@@ -333,6 +419,37 @@
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AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
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AR934X_PCIE_WMAC_INT_PCIE_RC3)
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#define QCA955X_EXT_INT_WMAC_MISC BIT(0)
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#define QCA955X_EXT_INT_WMAC_TX BIT(1)
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#define QCA955X_EXT_INT_WMAC_RXLP BIT(2)
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#define QCA955X_EXT_INT_WMAC_RXHP BIT(3)
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#define QCA955X_EXT_INT_PCIE_RC1 BIT(4)
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#define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5)
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#define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6)
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#define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7)
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#define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8)
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#define QCA955X_EXT_INT_PCIE_RC2 BIT(12)
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#define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13)
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#define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14)
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#define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15)
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#define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16)
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#define QCA955X_EXT_INT_USB1 BIT(24)
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#define QCA955X_EXT_INT_USB2 BIT(28)
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#define QCA955X_EXT_INT_WMAC_ALL \
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(QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \
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QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP)
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#define QCA955X_EXT_INT_PCIE_RC1_ALL \
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(QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \
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QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \
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QCA955X_EXT_INT_PCIE_RC1_INT3)
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#define QCA955X_EXT_INT_PCIE_RC2_ALL \
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(QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \
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QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
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QCA955X_EXT_INT_PCIE_RC2_INT3)
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#define REV_ID_MAJOR_MASK 0xfff0
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#define REV_ID_MAJOR_AR71XX 0x00a0
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#define REV_ID_MAJOR_AR913X 0x00b0
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@@ -344,6 +461,8 @@
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#define REV_ID_MAJOR_AR9341 0x0120
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#define REV_ID_MAJOR_AR9342 0x1120
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#define REV_ID_MAJOR_AR9344 0x2120
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#define REV_ID_MAJOR_QCA9556 0x0130
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#define REV_ID_MAJOR_QCA9558 0x1130
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#define AR71XX_REV_ID_MINOR_MASK 0x3
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#define AR71XX_REV_ID_MINOR_AR7130 0x0
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@@ -364,6 +483,8 @@
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#define AR934X_REV_ID_REVISION_MASK 0xf
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#define QCA955X_REV_ID_REVISION_MASK 0xf
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/*
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* SPI block
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*/
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@@ -401,12 +522,15 @@
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#define AR71XX_GPIO_REG_INT_ENABLE 0x24
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#define AR71XX_GPIO_REG_FUNC 0x28
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#define AR934X_GPIO_REG_FUNC 0x6c
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#define AR71XX_GPIO_COUNT 16
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#define AR7240_GPIO_COUNT 18
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#define AR7241_GPIO_COUNT 20
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#define AR913X_GPIO_COUNT 22
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#define AR933X_GPIO_COUNT 30
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#define AR934X_GPIO_COUNT 23
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#define QCA955X_GPIO_COUNT 24
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/*
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* SRIF block
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@@ -32,6 +32,8 @@ enum ath79_soc_type {
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ATH79_SOC_AR9341,
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ATH79_SOC_AR9342,
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ATH79_SOC_AR9344,
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ATH79_SOC_QCA9556,
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ATH79_SOC_QCA9558,
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};
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extern enum ath79_soc_type ath79_soc;
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@@ -98,6 +100,21 @@ static inline int soc_is_ar934x(void)
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return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
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}
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static inline int soc_is_qca9556(void)
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{
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return ath79_soc == ATH79_SOC_QCA9556;
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}
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static inline int soc_is_qca9558(void)
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{
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return ath79_soc == ATH79_SOC_QCA9558;
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}
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static inline int soc_is_qca955x(void)
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{
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return soc_is_qca9556() || soc_is_qca9558();
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}
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extern void __iomem *ath79_ddr_base;
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extern void __iomem *ath79_pll_base;
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extern void __iomem *ath79_reset_base;
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@@ -10,10 +10,13 @@
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#define __ASM_MACH_ATH79_IRQ_H
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#define MIPS_CPU_IRQ_BASE 0
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#define NR_IRQS 48
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#define NR_IRQS 51
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#define ATH79_CPU_IRQ(_x) (MIPS_CPU_IRQ_BASE + (_x))
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#define ATH79_MISC_IRQ_BASE 8
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#define ATH79_MISC_IRQ_COUNT 32
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#define ATH79_MISC_IRQ(_x) (ATH79_MISC_IRQ_BASE + (_x))
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#define ATH79_PCI_IRQ_BASE (ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT)
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#define ATH79_PCI_IRQ_COUNT 6
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@@ -23,25 +26,9 @@
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#define ATH79_IP2_IRQ_COUNT 2
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#define ATH79_IP2_IRQ(_x) (ATH79_IP2_IRQ_BASE + (_x))
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#define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2)
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#define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3)
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#define ATH79_CPU_IRQ_GE0 (MIPS_CPU_IRQ_BASE + 4)
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#define ATH79_CPU_IRQ_GE1 (MIPS_CPU_IRQ_BASE + 5)
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#define ATH79_CPU_IRQ_MISC (MIPS_CPU_IRQ_BASE + 6)
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#define ATH79_CPU_IRQ_TIMER (MIPS_CPU_IRQ_BASE + 7)
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#define ATH79_MISC_IRQ_TIMER (ATH79_MISC_IRQ_BASE + 0)
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#define ATH79_MISC_IRQ_ERROR (ATH79_MISC_IRQ_BASE + 1)
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#define ATH79_MISC_IRQ_GPIO (ATH79_MISC_IRQ_BASE + 2)
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#define ATH79_MISC_IRQ_UART (ATH79_MISC_IRQ_BASE + 3)
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#define ATH79_MISC_IRQ_WDOG (ATH79_MISC_IRQ_BASE + 4)
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#define ATH79_MISC_IRQ_PERFC (ATH79_MISC_IRQ_BASE + 5)
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#define ATH79_MISC_IRQ_OHCI (ATH79_MISC_IRQ_BASE + 6)
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#define ATH79_MISC_IRQ_DMA (ATH79_MISC_IRQ_BASE + 7)
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#define ATH79_MISC_IRQ_TIMER2 (ATH79_MISC_IRQ_BASE + 8)
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#define ATH79_MISC_IRQ_TIMER3 (ATH79_MISC_IRQ_BASE + 9)
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#define ATH79_MISC_IRQ_TIMER4 (ATH79_MISC_IRQ_BASE + 10)
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#define ATH79_MISC_IRQ_ETHSW (ATH79_MISC_IRQ_BASE + 12)
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#define ATH79_IP3_IRQ_BASE (ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT)
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#define ATH79_IP3_IRQ_COUNT 3
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#define ATH79_IP3_IRQ(_x) (ATH79_IP3_IRQ_BASE + (_x))
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#include_next <irq.h>
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@@ -1,28 +0,0 @@
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/*
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* Atheros AR71XX/AR724X PCI support
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*
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* Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
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* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#ifndef __ASM_MACH_ATH79_PCI_H
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#define __ASM_MACH_ATH79_PCI_H
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#if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR71XX)
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int ar71xx_pcibios_init(void);
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#else
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static inline int ar71xx_pcibios_init(void) { return 0; }
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#endif
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#if defined(CONFIG_PCI_AR724X)
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int ar724x_pcibios_init(int irq);
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#else
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static inline int ar724x_pcibios_init(int irq) { return 0; }
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#endif
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#endif /* __ASM_MACH_ATH79_PCI_H */
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