tools headers: Update the x86 headers with the kernel sources
To pick up the changes in:
841326332bcb13ae x86/cpufeatures: Generate the <asm/cpufeaturemasks.h> header based on build config
440a65b7d25fb06f x86/mm: Enable AMD translation cache extensions
767ae437a32d6447 x86/mm: Add INVLPGB feature and Kconfig entry
b4cc466b97359011 cpufreq/amd-pstate: Replace all AMD_CPPC_* macros with masks
98c7a713db91c5a9 x86/bugs: Add X86_BUG_SPECTRE_V2_USER
8f64eee70cdd3bb8 x86/bugs: Remove X86_FEATURE_USE_IBPB
8442df2b49ed9bcd x86/bugs: KVM: Add support for SRSO_MSR_FIX
70792aed14551e31 x86/cpufeatures: Add CPUID feature bit for Idle HLT intercept
968e9bc4cef87054 x86: move ZMM exclusion list into CPU feature flag
c631a2de7ae48d50 perf/x86/intel: Ensure LBRs are disabled when a CPU is starting
38cc6495cdec18a4 x86/sev: Prevent GUEST_TSC_FREQ MSR interception for Secure TSC enabled guests
288bba2f4c8be1e1 x86/cpufeatures: Remove "AMD" from the comments to the AMD-specific leaf
877818802c3e970f x86/bugs: Add SRSO_USER_KERNEL_NO support
8ae3291f773befee x86/sev: Add full support for a segmented RMP table
0cbc0258415814c8 x86/sev: Add support for the RMPREAD instruction
7a470e826d7521be x86/cpufeatures: Free up unused feature bits
Addressing this perf tools build warning:
Warning: Kernel ABI header differences:
diff -u tools/arch/x86/include/asm/cpufeatures.h arch/x86/include/asm/cpufeatures.h
diff -u tools/arch/x86/include/asm/msr-index.h arch/x86/include/asm/msr-index.h
Please see tools/include/uapi/README for further details.
Acked-by: Ingo Molnar <mingo@kernel.org>
Tested-by: Venkat Rao Bagalkote <venkat88@linux.ibm.com>
Cc: x86@kernel.org
Link: https://lore.kernel.org/r/20250410001125.391820-10-namhyung@kernel.org
Signed-off-by: Namhyung Kim <namhyung@kernel.org>
This commit is contained in:
Namhyung Kim
parent
7470998187
commit
847f1403d3
@ -75,8 +75,8 @@
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#define X86_FEATURE_CENTAUR_MCR ( 3*32+ 3) /* "centaur_mcr" Centaur MCRs (= MTRRs) */
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#define X86_FEATURE_K8 ( 3*32+ 4) /* Opteron, Athlon64 */
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#define X86_FEATURE_ZEN5 ( 3*32+ 5) /* CPU based on Zen5 microarchitecture */
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#define X86_FEATURE_P3 ( 3*32+ 6) /* P3 */
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#define X86_FEATURE_P4 ( 3*32+ 7) /* P4 */
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/* Free ( 3*32+ 6) */
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/* Free ( 3*32+ 7) */
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#define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* "constant_tsc" TSC ticks at a constant rate */
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#define X86_FEATURE_UP ( 3*32+ 9) /* "up" SMP kernel running on UP */
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#define X86_FEATURE_ART ( 3*32+10) /* "art" Always running timer (ART) */
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@ -329,6 +329,7 @@
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#define X86_FEATURE_CLZERO (13*32+ 0) /* "clzero" CLZERO instruction */
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#define X86_FEATURE_IRPERF (13*32+ 1) /* "irperf" Instructions Retired Count */
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#define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* "xsaveerptr" Always save/restore FP error pointers */
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#define X86_FEATURE_INVLPGB (13*32+ 3) /* INVLPGB and TLBSYNC instructions supported */
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#define X86_FEATURE_RDPRU (13*32+ 4) /* "rdpru" Read processor register at user level */
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#define X86_FEATURE_WBNOINVD (13*32+ 9) /* "wbnoinvd" WBNOINVD instruction */
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#define X86_FEATURE_AMD_IBPB (13*32+12) /* Indirect Branch Prediction Barrier */
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@ -377,6 +378,7 @@
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#define X86_FEATURE_V_SPEC_CTRL (15*32+20) /* "v_spec_ctrl" Virtual SPEC_CTRL */
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#define X86_FEATURE_VNMI (15*32+25) /* "vnmi" Virtual NMI */
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#define X86_FEATURE_SVME_ADDR_CHK (15*32+28) /* SVME addr check */
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#define X86_FEATURE_IDLE_HLT (15*32+30) /* IDLE HLT intercept */
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/* Intel-defined CPU features, CPUID level 0x00000007:0 (ECX), word 16 */
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#define X86_FEATURE_AVX512VBMI (16*32+ 1) /* "avx512vbmi" AVX512 Vector Bit Manipulation instructions*/
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@ -434,15 +436,18 @@
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#define X86_FEATURE_SPEC_CTRL_SSBD (18*32+31) /* Speculative Store Bypass Disable */
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/* AMD-defined memory encryption features, CPUID level 0x8000001f (EAX), word 19 */
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#define X86_FEATURE_SME (19*32+ 0) /* "sme" AMD Secure Memory Encryption */
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#define X86_FEATURE_SEV (19*32+ 1) /* "sev" AMD Secure Encrypted Virtualization */
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#define X86_FEATURE_SME (19*32+ 0) /* "sme" Secure Memory Encryption */
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#define X86_FEATURE_SEV (19*32+ 1) /* "sev" Secure Encrypted Virtualization */
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#define X86_FEATURE_VM_PAGE_FLUSH (19*32+ 2) /* VM Page Flush MSR is supported */
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#define X86_FEATURE_SEV_ES (19*32+ 3) /* "sev_es" AMD Secure Encrypted Virtualization - Encrypted State */
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#define X86_FEATURE_SEV_SNP (19*32+ 4) /* "sev_snp" AMD Secure Encrypted Virtualization - Secure Nested Paging */
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#define X86_FEATURE_SEV_ES (19*32+ 3) /* "sev_es" Secure Encrypted Virtualization - Encrypted State */
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#define X86_FEATURE_SEV_SNP (19*32+ 4) /* "sev_snp" Secure Encrypted Virtualization - Secure Nested Paging */
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#define X86_FEATURE_V_TSC_AUX (19*32+ 9) /* Virtual TSC_AUX */
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#define X86_FEATURE_SME_COHERENT (19*32+10) /* AMD hardware-enforced cache coherency */
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#define X86_FEATURE_DEBUG_SWAP (19*32+14) /* "debug_swap" AMD SEV-ES full debug state swap support */
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#define X86_FEATURE_SME_COHERENT (19*32+10) /* hardware-enforced cache coherency */
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#define X86_FEATURE_DEBUG_SWAP (19*32+14) /* "debug_swap" SEV-ES full debug state swap support */
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#define X86_FEATURE_RMPREAD (19*32+21) /* RMPREAD instruction */
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#define X86_FEATURE_SEGMENTED_RMP (19*32+23) /* Segmented RMP support */
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#define X86_FEATURE_SVSM (19*32+28) /* "svsm" SVSM present */
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#define X86_FEATURE_HV_INUSE_WR_ALLOWED (19*32+30) /* Allow Write to in-use hypervisor-owned pages */
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/* AMD-defined Extended Feature 2 EAX, CPUID level 0x80000021 (EAX), word 20 */
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#define X86_FEATURE_NO_NESTED_DATA_BP (20*32+ 0) /* No Nested Data Breakpoints */
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@ -455,6 +460,11 @@
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#define X86_FEATURE_SBPB (20*32+27) /* Selective Branch Prediction Barrier */
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#define X86_FEATURE_IBPB_BRTYPE (20*32+28) /* MSR_PRED_CMD[IBPB] flushes all branch type predictions */
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#define X86_FEATURE_SRSO_NO (20*32+29) /* CPU is not affected by SRSO */
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#define X86_FEATURE_SRSO_USER_KERNEL_NO (20*32+30) /* CPU is not affected by SRSO across user/kernel boundaries */
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#define X86_FEATURE_SRSO_BP_SPEC_REDUCE (20*32+31) /*
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* BP_CFG[BpSpecReduce] can be used to mitigate SRSO for VMs.
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* (SRSO_MSR_FIX in the official doc).
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*/
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/*
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* Extended auxiliary flags: Linux defined - for features scattered in various
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@ -470,6 +480,7 @@
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#define X86_FEATURE_AMD_FAST_CPPC (21*32 + 5) /* Fast CPPC */
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#define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32 + 6) /* Heterogeneous Core Topology */
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#define X86_FEATURE_AMD_WORKLOAD_CLASS (21*32 + 7) /* Workload Classification */
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#define X86_FEATURE_PREFER_YMM (21*32 + 8) /* Avoid ZMM registers due to downclocking */
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/*
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* BUG word(s)
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@ -521,4 +532,5 @@
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#define X86_BUG_RFDS X86_BUG(1*32 + 2) /* "rfds" CPU is vulnerable to Register File Data Sampling */
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#define X86_BUG_BHI X86_BUG(1*32 + 3) /* "bhi" CPU is affected by Branch History Injection */
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#define X86_BUG_IBPB_NO_RET X86_BUG(1*32 + 4) /* "ibpb_no_ret" IBPB omits return target predictions */
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#define X86_BUG_SPECTRE_V2_USER X86_BUG(1*32 + 5) /* "spectre_v2_user" CPU is affected by Spectre variant 2 attack between user processes */
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#endif /* _ASM_X86_CPUFEATURES_H */
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@ -397,7 +397,8 @@
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#define MSR_IA32_PASID_VALID BIT_ULL(31)
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/* DEBUGCTLMSR bits (others vary by model): */
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#define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */
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#define DEBUGCTLMSR_LBR_BIT 0 /* last branch recording */
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#define DEBUGCTLMSR_LBR (1UL << DEBUGCTLMSR_LBR_BIT)
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#define DEBUGCTLMSR_BTF_SHIFT 1
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#define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */
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#define DEBUGCTLMSR_BUS_LOCK_DETECT (1UL << 2)
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@ -610,6 +611,7 @@
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#define MSR_AMD_PERF_CTL 0xc0010062
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#define MSR_AMD_PERF_STATUS 0xc0010063
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#define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
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#define MSR_AMD64_GUEST_TSC_FREQ 0xc0010134
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#define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
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#define MSR_AMD64_OSVW_STATUS 0xc0010141
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#define MSR_AMD_PPIN_CTL 0xc00102f0
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@ -646,6 +648,7 @@
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#define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */
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#define MSR_AMD64_SVM_AVIC_DOORBELL 0xc001011b
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#define MSR_AMD64_VM_PAGE_FLUSH 0xc001011e
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#define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f
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#define MSR_AMD64_SEV_ES_GHCB 0xc0010130
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#define MSR_AMD64_SEV 0xc0010131
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#define MSR_AMD64_SEV_ENABLED_BIT 0
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@ -684,11 +687,12 @@
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#define MSR_AMD64_SNP_SMT_PROT BIT_ULL(MSR_AMD64_SNP_SMT_PROT_BIT)
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#define MSR_AMD64_SNP_RESV_BIT 18
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#define MSR_AMD64_SNP_RESERVED_MASK GENMASK_ULL(63, MSR_AMD64_SNP_RESV_BIT)
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#define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f
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#define MSR_AMD64_RMP_BASE 0xc0010132
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#define MSR_AMD64_RMP_END 0xc0010133
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#define MSR_AMD64_RMP_CFG 0xc0010136
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#define MSR_AMD64_SEG_RMP_ENABLED_BIT 0
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#define MSR_AMD64_SEG_RMP_ENABLED BIT_ULL(MSR_AMD64_SEG_RMP_ENABLED_BIT)
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#define MSR_AMD64_RMP_SEGMENT_SHIFT(x) (((x) & GENMASK_ULL(13, 8)) >> 8)
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#define MSR_SVSM_CAA 0xc001f000
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@ -699,15 +703,17 @@
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#define MSR_AMD_CPPC_REQ 0xc00102b3
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#define MSR_AMD_CPPC_STATUS 0xc00102b4
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#define AMD_CPPC_LOWEST_PERF(x) (((x) >> 0) & 0xff)
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#define AMD_CPPC_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff)
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#define AMD_CPPC_NOMINAL_PERF(x) (((x) >> 16) & 0xff)
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#define AMD_CPPC_HIGHEST_PERF(x) (((x) >> 24) & 0xff)
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/* Masks for use with MSR_AMD_CPPC_CAP1 */
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#define AMD_CPPC_LOWEST_PERF_MASK GENMASK(7, 0)
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#define AMD_CPPC_LOWNONLIN_PERF_MASK GENMASK(15, 8)
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#define AMD_CPPC_NOMINAL_PERF_MASK GENMASK(23, 16)
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#define AMD_CPPC_HIGHEST_PERF_MASK GENMASK(31, 24)
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#define AMD_CPPC_MAX_PERF(x) (((x) & 0xff) << 0)
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#define AMD_CPPC_MIN_PERF(x) (((x) & 0xff) << 8)
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#define AMD_CPPC_DES_PERF(x) (((x) & 0xff) << 16)
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#define AMD_CPPC_ENERGY_PERF_PREF(x) (((x) & 0xff) << 24)
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/* Masks for use with MSR_AMD_CPPC_REQ */
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#define AMD_CPPC_MAX_PERF_MASK GENMASK(7, 0)
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#define AMD_CPPC_MIN_PERF_MASK GENMASK(15, 8)
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#define AMD_CPPC_DES_PERF_MASK GENMASK(23, 16)
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#define AMD_CPPC_EPP_PERF_MASK GENMASK(31, 24)
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/* AMD Performance Counter Global Status and Control MSRs */
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#define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS 0xc0000300
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@ -719,6 +725,7 @@
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/* Zen4 */
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#define MSR_ZEN4_BP_CFG 0xc001102e
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#define MSR_ZEN4_BP_CFG_BP_SPEC_REDUCE_BIT 4
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#define MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT 5
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/* Fam 19h MSRs */
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