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Merge branches 'clk-marvell', 'clk-xilinx', 'clk-mediatek' and 'clk-loongson' into clk-next

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- Add Mediatek MT8196 clk drivers

* clk-marvell:
  clk: mmp: pxa1908: Instantiate power driver through auxiliary bus

* clk-xilinx:
  clk: clocking-wizard: Fix output clock register offset for Versal platforms
  clk: xilinx: Optimize divisor search in clk_wzrd_get_divisors_ver()

* clk-mediatek: (31 commits)
  clk: mediatek: Add MT8196 vencsys clock support
  clk: mediatek: Add MT8196 vdecsys clock support
  clk: mediatek: Add MT8196 ovl1 clock support
  clk: mediatek: Add MT8196 ovl0 clock support
  clk: mediatek: Add MT8196 disp-ao clock support
  clk: mediatek: Add MT8196 disp1 clock support
  clk: mediatek: Add MT8196 disp0 clock support
  clk: mediatek: Add MT8196 mfg clock support
  clk: mediatek: Add MT8196 mdpsys clock support
  clk: mediatek: Add MT8196 mcu clock support
  clk: mediatek: Add MT8196 I2C clock support
  clk: mediatek: Add MT8196 pextpsys clock support
  clk: mediatek: Add MT8196 ufssys clock support
  clk: mediatek: Add MT8196 peripheral clock support
  clk: mediatek: Add MT8196 vlpckgen clock support
  clk: mediatek: Add MT8196 topckgen2 clock support
  clk: mediatek: Add MT8196 topckgen clock support
  clk: mediatek: Add MT8196 apmixedsys clock support
  dt-bindings: clock: mediatek: Describe MT8196 clock controllers
  clk: mediatek: clk-mtk: Add MUX_DIV_GATE macro
  ...

* clk-loongson:
  clk: loongson2: Add clock definitions for Loongson-2K0300 SoC
  clk: loongson2: Avoid hardcoding firmware name of the reference clock
  clk: loongson2: Allow zero divisors for dividers
  clk: loongson2: Support scale clocks with an alternative mode
  clk: loongson2: Allow specifying clock flags for gate clock
  dt-bindings: clock: loongson2: Add Loongson-2K0300 compatible
This commit is contained in:
Stephen Boyd 2025-10-06 13:00:22 -05:00
commit 8397c58ea7
No known key found for this signature in database
GPG Key ID: AD028897C6E49525
44 changed files with 6414 additions and 77 deletions
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18
Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml
View File

@ -16,6 +16,7 @@ description: |
properties:
compatible:
enum:
- loongson,ls2k0300-clk
- loongson,ls2k0500-clk
- loongson,ls2k-clk # This is for Loongson-2K1000
- loongson,ls2k2000-clk
@ -24,8 +25,7 @@ properties:
maxItems: 1
clocks:
items:
- description: 100m ref
maxItems: 1
clock-names:
items:
@ -38,11 +38,23 @@ properties:
ID in its "clocks" phandle cell. See include/dt-bindings/clock/loongson,ls2k-clk.h
for the full list of Loongson-2 SoC clock IDs.
allOf:
- if:
properties:
compatible:
contains:
const: loongson,ls2k0300-clk
then:
properties:
clock-names: false
else:
required:
- clock-names
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
additionalProperties: false

112
Documentation/devicetree/bindings/clock/mediatek,mt8196-clock.yaml Normal file
View File

@ -0,0 +1,112 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,mt8196-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek Functional Clock Controller for MT8196
maintainers:
- Guangjie Song <guangjie.song@mediatek.com>
- Laura Nao <laura.nao@collabora.com>
description: |
The clock architecture in MediaTek SoCs is structured like below:
PLLs -->
dividers -->
muxes
-->
clock gate
The device nodes provide clock gate control in different IP blocks.
properties:
compatible:
items:
- enum:
- mediatek,mt8196-imp-iic-wrap-c
- mediatek,mt8196-imp-iic-wrap-e
- mediatek,mt8196-imp-iic-wrap-n
- mediatek,mt8196-imp-iic-wrap-w
- mediatek,mt8196-mdpsys0
- mediatek,mt8196-mdpsys1
- mediatek,mt8196-pericfg-ao
- mediatek,mt8196-pextp0cfg-ao
- mediatek,mt8196-pextp1cfg-ao
- mediatek,mt8196-ufscfg-ao
- mediatek,mt8196-vencsys
- mediatek,mt8196-vencsys-c1
- mediatek,mt8196-vencsys-c2
- mediatek,mt8196-vdecsys
- mediatek,mt8196-vdecsys-soc
- mediatek,mt8196-vdisp-ao
- const: syscon
reg:
maxItems: 1
'#clock-cells':
const: 1
'#reset-cells':
const: 1
description:
Reset lines for PEXTP0/1 and UFS blocks.
mediatek,hardware-voter:
$ref: /schemas/types.yaml#/definitions/phandle
description: |
Phandle to the "Hardware Voter" (HWV), as named in the vendor
documentation for MT8196/MT6991.
The HWV is a SoC-internal fixed-function MCU used to collect votes from
both the Application Processor and other remote processors within the SoC.
It is intended to transparently enable or disable hardware resources (such
as power domains or clocks) based on internal vote aggregation handled by
the MCU's internal state machine.
However, in practice, this design is incomplete. While the HWV performs
some internal vote aggregation,software is still required to
- Manually enable power supplies externally, if present and if required
- Manually enable parent clocks via direct MMIO writes to clock controllers
- Enable the FENC after the clock has been ungated via direct MMIO
writes to clock controllers
As such, the HWV behaves more like a hardware-managed clock reference
counter than a true voter. Furthermore, it is not a separate
controller. It merely serves as an alternative interface to the same
underlying clock or power controller. Actual control still requires
direct access to the controller's own MMIO register space, in
addition to writing to the HWV's MMIO region.
For this reason, a custom phandle is used here - drivers need to directly
access the HWV MMIO region in a syscon-like fashion, due to how the
hardware is wired. This differs from true hardware voting systems, which
typically do not require custom phandles and rely instead on generic APIs
(clocks, power domains, interconnects).
The name "hardware-voter" is retained to match vendor documentation, but
this should not be reused or misunderstood as a proper voting mechanism.
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
pericfg_ao: clock-controller@16640000 {
compatible = "mediatek,mt8196-pericfg-ao", "syscon";
reg = <0x16640000 0x1000>;
mediatek,hardware-voter = <&scp_hwv>;
#clock-cells = <1>;
};
- |
pextp0cfg_ao: clock-controller@169b0000 {
compatible = "mediatek,mt8196-pextp0cfg-ao", "syscon";
reg = <0x169b0000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};

107
Documentation/devicetree/bindings/clock/mediatek,mt8196-sys-clock.yaml Normal file
View File

@ -0,0 +1,107 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,mt8196-sys-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek System Clock Controller for MT8196
maintainers:
- Guangjie Song <guangjie.song@mediatek.com>
- Laura Nao <laura.nao@collabora.com>
description: |
The clock architecture in MediaTek SoCs is structured like below:
PLLs -->
dividers -->
muxes
-->
clock gate
The apmixedsys, apmixedsys_gp2, vlpckgen, armpll, ccipll, mfgpll and ptppll
provide most of the PLLs which are generated from the SoC's 26MHZ crystal oscillator.
The topckgen, topckgen_gp2 and vlpckgen provide dividers and muxes which
provide the clock source to other IP blocks.
properties:
compatible:
items:
- enum:
- mediatek,mt8196-apmixedsys
- mediatek,mt8196-armpll-b-pll-ctrl
- mediatek,mt8196-armpll-bl-pll-ctrl
- mediatek,mt8196-armpll-ll-pll-ctrl
- mediatek,mt8196-apmixedsys-gp2
- mediatek,mt8196-ccipll-pll-ctrl
- mediatek,mt8196-mfgpll-pll-ctrl
- mediatek,mt8196-mfgpll-sc0-pll-ctrl
- mediatek,mt8196-mfgpll-sc1-pll-ctrl
- mediatek,mt8196-ptppll-pll-ctrl
- mediatek,mt8196-topckgen
- mediatek,mt8196-topckgen-gp2
- mediatek,mt8196-vlpckgen
- const: syscon
reg:
maxItems: 1
'#clock-cells':
const: 1
mediatek,hardware-voter:
$ref: /schemas/types.yaml#/definitions/phandle
description: |
Phandle to the "Hardware Voter" (HWV), as named in the vendor
documentation for MT8196/MT6991.
The HWV is a SoC-internal fixed-function MCU used to collect votes from
both the Application Processor and other remote processors within the SoC.
It is intended to transparently enable or disable hardware resources (such
as power domains or clocks) based on internal vote aggregation handled by
the MCU's internal state machine.
However, in practice, this design is incomplete. While the HWV performs
some internal vote aggregation,software is still required to
- Manually enable power supplies externally, if present and if required
- Manually enable parent clocks via direct MMIO writes to clock controllers
- Enable the FENC after the clock has been ungated via direct MMIO
writes to clock controllers
As such, the HWV behaves more like a hardware-managed clock reference
counter than a true voter. Furthermore, it is not a separate
controller. It merely serves as an alternative interface to the same
underlying clock or power controller. Actual control still requires
direct access to the controller's own MMIO register space, in
addition to writing to the HWV's MMIO region.
For this reason, a custom phandle is used here - drivers need to directly
access the HWV MMIO region in a syscon-like fashion, due to how the
hardware is wired. This differs from true hardware voting systems, which
typically do not require custom phandles and rely instead on generic APIs
(clocks, power domains, interconnects).
The name "hardware-voter" is retained to match vendor documentation, but
this should not be reused or misunderstood as a proper voting mechanism.
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
apmixedsys_clk: syscon@10000800 {
compatible = "mediatek,mt8196-apmixedsys", "syscon";
reg = <0x10000800 0x1000>;
#clock-cells = <1>;
};
- |
topckgen: syscon@10000000 {
compatible = "mediatek,mt8196-topckgen", "syscon";
reg = <0x10000000 0x800>;
mediatek,hardware-voter = <&scp_hwv>;
#clock-cells = <1>;
};

2
MAINTAINERS
View File

@ -2869,7 +2869,9 @@ ARM/Marvell PXA1908 SOC support
M: Duje Mihanović <duje@dujemihanovic.xyz>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml
F: arch/arm64/boot/dts/marvell/mmp/
F: drivers/clk/mmp/Kconfig
F: drivers/clk/mmp/clk-pxa1908*.c
F: include/dt-bindings/clock/marvell,pxa1908.h

1
drivers/clk/Kconfig
View File

@ -512,6 +512,7 @@ source "drivers/clk/imx/Kconfig"
source "drivers/clk/ingenic/Kconfig"
source "drivers/clk/keystone/Kconfig"
source "drivers/clk/mediatek/Kconfig"
source "drivers/clk/mmp/Kconfig"
source "drivers/clk/meson/Kconfig"
source "drivers/clk/mstar/Kconfig"
source "drivers/clk/microchip/Kconfig"

122
drivers/clk/clk-loongson2.c
View File

@ -13,10 +13,6 @@
#include <linux/io-64-nonatomic-lo-hi.h>
#include <dt-bindings/clock/loongson,ls2k-clk.h>
static const struct clk_parent_data pdata[] = {
{ .fw_name = "ref_100m", },
};
enum loongson2_clk_type {
CLK_TYPE_PLL,
CLK_TYPE_SCALE,
@ -42,6 +38,7 @@ struct loongson2_clk_data {
u8 div_width;
u8 mult_shift;
u8 mult_width;
u8 bit_idx;
};
struct loongson2_clk_board_info {
@ -50,6 +47,7 @@ struct loongson2_clk_board_info {
const char *name;
const char *parent_name;
unsigned long fixed_rate;
unsigned long flags;
u8 reg_offset;
u8 div_shift;
u8 div_width;
@ -95,6 +93,19 @@ struct loongson2_clk_board_info {
.div_width = _dwidth, \
}
#define CLK_SCALE_MODE(_id, _name, _pname, _offset, \
_dshift, _dwidth, _midx) \
{ \
.id = _id, \
.type = CLK_TYPE_SCALE, \
.name = _name, \
.parent_name = _pname, \
.reg_offset = _offset, \
.div_shift = _dshift, \
.div_width = _dwidth, \
.bit_idx = _midx + 1, \
}
#define CLK_GATE(_id, _name, _pname, _offset, _bidx) \
{ \
.id = _id, \
@ -105,6 +116,18 @@ struct loongson2_clk_board_info {
.bit_idx = _bidx, \
}
#define CLK_GATE_FLAGS(_id, _name, _pname, _offset, _bidx, \
_flags) \
{ \
.id = _id, \
.type = CLK_TYPE_GATE, \
.name = _name, \
.parent_name = _pname, \
.reg_offset = _offset, \
.bit_idx = _bidx, \
.flags = _flags \
}
#define CLK_FIXED(_id, _name, _pname, _rate) \
{ \
.id = _id, \
@ -114,6 +137,51 @@ struct loongson2_clk_board_info {
.fixed_rate = _rate, \
}
static const struct loongson2_clk_board_info ls2k0300_clks[] = {
/* Reference Clock */
CLK_PLL(LS2K0300_NODE_PLL, "pll_node", 0x00, 15, 9, 8, 7),
CLK_PLL(LS2K0300_DDR_PLL, "pll_ddr", 0x08, 15, 9, 8, 7),
CLK_PLL(LS2K0300_PIX_PLL, "pll_pix", 0x10, 15, 9, 8, 7),
CLK_FIXED(LS2K0300_CLK_STABLE, "clk_stable", NULL, 100000000),
CLK_FIXED(LS2K0300_CLK_THSENS, "clk_thsens", NULL, 10000000),
/* Node PLL */
CLK_DIV(LS2K0300_CLK_NODE_DIV, "clk_node_div", "pll_node", 0x00, 24, 7),
CLK_DIV(LS2K0300_CLK_GMAC_DIV, "clk_gmac_div", "pll_node", 0x04, 0, 7),
CLK_DIV(LS2K0300_CLK_I2S_DIV, "clk_i2s_div", "pll_node", 0x04, 8, 7),
CLK_GATE(LS2K0300_CLK_NODE_PLL_GATE, "clk_node_pll_gate", "clk_node_div", 0x00, 0),
CLK_GATE(LS2K0300_CLK_GMAC_GATE, "clk_gmac_gate", "clk_gmac_div", 0x00, 1),
CLK_GATE(LS2K0300_CLK_I2S_GATE, "clk_i2s_gate", "clk_i2s_div", 0x00, 2),
CLK_GATE_FLAGS(LS2K0300_CLK_NODE_GATE, "clk_node_gate", "clk_node_scale", 0x24, 0,
CLK_IS_CRITICAL),
CLK_SCALE_MODE(LS2K0300_CLK_NODE_SCALE, "clk_node_scale", "clk_node_pll_gate", 0x20, 0, 3,
3),
/* DDR PLL */
CLK_DIV(LS2K0300_CLK_DDR_DIV, "clk_ddr_div", "pll_ddr", 0x08, 24, 7),
CLK_DIV(LS2K0300_CLK_NET_DIV, "clk_net_div", "pll_ddr", 0x0c, 0, 7),
CLK_DIV(LS2K0300_CLK_DEV_DIV, "clk_dev_div", "pll_ddr", 0x0c, 8, 7),
CLK_GATE(LS2K0300_CLK_NET_GATE, "clk_net_gate", "clk_net_div", 0x08, 1),
CLK_GATE(LS2K0300_CLK_DEV_GATE, "clk_dev_gate", "clk_dev_div", 0x08, 2),
CLK_GATE_FLAGS(LS2K0300_CLK_DDR_GATE, "clk_ddr_gate", "clk_ddr_div", 0x08, 0,
CLK_IS_CRITICAL),
/* PIX PLL */
CLK_DIV(LS2K0300_CLK_PIX_DIV, "clk_pix_div", "pll_pix", 0x10, 24, 7),
CLK_DIV(LS2K0300_CLK_GMACBP_DIV, "clk_gmacbp_div", "pll_pix", 0x14, 0, 7),
CLK_GATE(LS2K0300_CLK_PIX_PLL_GATE, "clk_pix_pll_gate", "clk_pix_div", 0x10, 0),
CLK_GATE(LS2K0300_CLK_PIX_GATE, "clk_pix_gate", "clk_pix_scale", 0x24, 6),
CLK_GATE(LS2K0300_CLK_GMACBP_GATE, "clk_gmacbp_gate", "clk_gmacbp_div", 0x10, 1),
CLK_SCALE_MODE(LS2K0300_CLK_PIX_SCALE, "clk_pix_scale", "clk_pix_pll_gate", 0x20, 4, 3, 7),
/* clk_dev_gate */
CLK_DIV(LS2K0300_CLK_SDIO_SCALE, "clk_sdio_scale", "clk_dev_gate", 0x20, 24, 4),
CLK_GATE(LS2K0300_CLK_USB_GATE, "clk_usb_gate", "clk_usb_scale", 0x24, 2),
CLK_GATE(LS2K0300_CLK_SDIO_GATE, "clk_sdio_gate", "clk_sdio_scale", 0x24, 4),
CLK_GATE(LS2K0300_CLK_APB_GATE, "clk_apb_gate", "clk_apb_scale", 0x24, 3),
CLK_GATE_FLAGS(LS2K0300_CLK_BOOT_GATE, "clk_boot_gate", "clk_boot_scale", 0x24, 1,
CLK_IS_CRITICAL),
CLK_SCALE_MODE(LS2K0300_CLK_USB_SCALE, "clk_usb_scale", "clk_dev_gate", 0x20, 12, 3, 15),
CLK_SCALE_MODE(LS2K0300_CLK_APB_SCALE, "clk_apb_scale", "clk_dev_gate", 0x20, 16, 3, 19),
CLK_SCALE_MODE(LS2K0300_CLK_BOOT_SCALE, "clk_boot_scale", "clk_dev_gate", 0x20, 8, 3, 11),
};
static const struct loongson2_clk_board_info ls2k0500_clks[] = {
CLK_PLL(LOONGSON2_NODE_PLL, "pll_node", 0, 16, 8, 8, 6),
CLK_PLL(LOONGSON2_DDR_PLL, "pll_ddr", 0x8, 16, 8, 8, 6),
@ -230,20 +298,26 @@ static const struct clk_ops loongson2_pll_recalc_ops = {
static unsigned long loongson2_freqscale_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
u64 val, mult;
u64 val, scale;
u32 mode = 0;
struct loongson2_clk_data *clk = to_loongson2_clk(hw);
val = readq(clk->reg);
mult = loongson2_rate_part(val, clk->div_shift, clk->div_width) + 1;
scale = loongson2_rate_part(val, clk->div_shift, clk->div_width) + 1;
return div_u64((u64)parent_rate * mult, 8);
if (clk->bit_idx)
mode = val & BIT(clk->bit_idx - 1);
return mode == 0 ? div_u64((u64)parent_rate * scale, 8) :
div_u64((u64)parent_rate, scale);
}
static const struct clk_ops loongson2_freqscale_recalc_ops = {
.recalc_rate = loongson2_freqscale_recalc_rate,
};
static struct clk_hw *loongson2_clk_register(struct loongson2_clk_provider *clp,
static struct clk_hw *loongson2_clk_register(const char *parent,
struct loongson2_clk_provider *clp,
const struct loongson2_clk_board_info *cld,
const struct clk_ops *ops)
{
@ -260,17 +334,14 @@ static struct clk_hw *loongson2_clk_register(struct loongson2_clk_provider *clp,
init.ops = ops;
init.flags = 0;
init.num_parents = 1;
if (!cld->parent_name)
init.parent_data = pdata;
else
init.parent_names = &cld->parent_name;
init.parent_names = &parent;
clk->reg = clp->base + cld->reg_offset;
clk->div_shift = cld->div_shift;
clk->div_width = cld->div_width;
clk->mult_shift = cld->mult_shift;
clk->mult_width = cld->mult_width;
clk->bit_idx = cld->bit_idx;
clk->hw.init = &init;
hw = &clk->hw;
@ -288,11 +359,17 @@ static int loongson2_clk_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct loongson2_clk_provider *clp;
const struct loongson2_clk_board_info *p, *data;
const char *refclk_name, *parent_name;
data = device_get_match_data(dev);
if (!data)
return -EINVAL;
refclk_name = of_clk_get_parent_name(dev->of_node, 0);
if (IS_ERR(refclk_name))
return dev_err_probe(dev, PTR_ERR(refclk_name),
"failed to get refclk name\n");
for (p = data; p->name; p++)
clks_num = max(clks_num, p->id + 1);
@ -314,32 +391,36 @@ static int loongson2_clk_probe(struct platform_device *pdev)
for (i = 0; i < clks_num; i++) {
p = &data[i];
parent_name = p->parent_name ? p->parent_name : refclk_name;
switch (p->type) {
case CLK_TYPE_PLL:
hw = loongson2_clk_register(clp, p,
hw = loongson2_clk_register(parent_name, clp, p,
&loongson2_pll_recalc_ops);
break;
case CLK_TYPE_SCALE:
hw = loongson2_clk_register(clp, p,
hw = loongson2_clk_register(parent_name, clp, p,
&loongson2_freqscale_recalc_ops);
break;
case CLK_TYPE_DIVIDER:
hw = devm_clk_hw_register_divider(dev, p->name,
p->parent_name, 0,
parent_name, 0,
clp->base + p->reg_offset,
p->div_shift, p->div_width,
CLK_DIVIDER_ONE_BASED,
CLK_DIVIDER_ONE_BASED |
CLK_DIVIDER_ALLOW_ZERO,
&clp->clk_lock);
break;
case CLK_TYPE_GATE:
hw = devm_clk_hw_register_gate(dev, p->name, p->parent_name, 0,
hw = devm_clk_hw_register_gate(dev, p->name, parent_name,
p->flags,
clp->base + p->reg_offset,
p->bit_idx, 0,
&clp->clk_lock);
break;
case CLK_TYPE_FIXED:
hw = devm_clk_hw_register_fixed_rate_parent_data(dev, p->name, pdata,
0, p->fixed_rate);
hw = devm_clk_hw_register_fixed_rate(dev, p->name, parent_name,
0, p->fixed_rate);
break;
default:
return dev_err_probe(dev, -EINVAL, "Invalid clk type\n");
@ -357,6 +438,7 @@ static int loongson2_clk_probe(struct platform_device *pdev)
}
static const struct of_device_id loongson2_clk_match_table[] = {
{ .compatible = "loongson,ls2k0300-clk", .data = &ls2k0300_clks },
{ .compatible = "loongson,ls2k0500-clk", .data = &ls2k0500_clks },
{ .compatible = "loongson,ls2k-clk", .data = &ls2k1000_clks },
{ .compatible = "loongson,ls2k2000-clk", .data = &ls2k2000_clks },

71
drivers/clk/mediatek/Kconfig
View File

@ -1002,6 +1002,77 @@ config COMMON_CLK_MT8195_VENCSYS
help
This driver supports MediaTek MT8195 vencsys clocks.
config COMMON_CLK_MT8196
tristate "Clock driver for MediaTek MT8196"
depends on ARM64 || COMPILE_TEST
select COMMON_CLK_MEDIATEK
default ARCH_MEDIATEK
help
This driver supports MediaTek MT8196 basic clocks.
config COMMON_CLK_MT8196_IMP_IIC_WRAP
tristate "Clock driver for MediaTek MT8196 imp_iic_wrap"
depends on COMMON_CLK_MT8196
default COMMON_CLK_MT8196
help
This driver supports MediaTek MT8196 i2c clocks.
config COMMON_CLK_MT8196_MCUSYS
tristate "Clock driver for MediaTek MT8196 mcusys"
depends on COMMON_CLK_MT8196
default COMMON_CLK_MT8196
help
This driver supports MediaTek MT8196 mcusys clocks.
config COMMON_CLK_MT8196_MDPSYS
tristate "Clock driver for MediaTek MT8196 mdpsys"
depends on COMMON_CLK_MT8196
default COMMON_CLK_MT8196
help
This driver supports MediaTek MT8196 mdpsys clocks.
config COMMON_CLK_MT8196_MFGCFG
tristate "Clock driver for MediaTek MT8196 mfgcfg"
depends on COMMON_CLK_MT8196
default m
help
This driver supports MediaTek MT8196 mfgcfg clocks.
config COMMON_CLK_MT8196_MMSYS
tristate "Clock driver for MediaTek MT8196 mmsys"
depends on COMMON_CLK_MT8196
default m
help
This driver supports MediaTek MT8196 mmsys clocks.
config COMMON_CLK_MT8196_PEXTPSYS
tristate "Clock driver for MediaTek MT8196 pextpsys"
depends on COMMON_CLK_MT8196
default COMMON_CLK_MT8196
help
This driver supports MediaTek MT8196 pextpsys clocks.
config COMMON_CLK_MT8196_UFSSYS
tristate "Clock driver for MediaTek MT8196 ufssys"
depends on COMMON_CLK_MT8196
default COMMON_CLK_MT8196
help
This driver supports MediaTek MT8196 ufssys clocks.
config COMMON_CLK_MT8196_VDECSYS
tristate "Clock driver for MediaTek MT8196 vdecsys"
depends on COMMON_CLK_MT8196
default m
help
This driver supports MediaTek MT8196 vdecsys clocks.
config COMMON_CLK_MT8196_VENCSYS
tristate "Clock driver for MediaTek MT8196 vencsys"
depends on COMMON_CLK_MT8196
default m
help
This driver supports MediaTek MT8196 vencsys clocks.
config COMMON_CLK_MT8365
tristate "Clock driver for MediaTek MT8365"
depends on ARCH_MEDIATEK || COMPILE_TEST

13
drivers/clk/mediatek/Makefile
View File

@ -150,6 +150,19 @@ obj-$(CONFIG_COMMON_CLK_MT8195_VDOSYS) += clk-mt8195-vdo0.o clk-mt8195-vdo1.o
obj-$(CONFIG_COMMON_CLK_MT8195_VENCSYS) += clk-mt8195-venc.o
obj-$(CONFIG_COMMON_CLK_MT8195_VPPSYS) += clk-mt8195-vpp0.o clk-mt8195-vpp1.o
obj-$(CONFIG_COMMON_CLK_MT8195_WPESYS) += clk-mt8195-wpe.o
obj-$(CONFIG_COMMON_CLK_MT8196) += clk-mt8196-apmixedsys.o clk-mt8196-topckgen.o \
clk-mt8196-topckgen2.o clk-mt8196-vlpckgen.o \
clk-mt8196-peri_ao.o
obj-$(CONFIG_COMMON_CLK_MT8196_IMP_IIC_WRAP) += clk-mt8196-imp_iic_wrap.o
obj-$(CONFIG_COMMON_CLK_MT8196_MCUSYS) += clk-mt8196-mcu.o
obj-$(CONFIG_COMMON_CLK_MT8196_MDPSYS) += clk-mt8196-mdpsys.o
obj-$(CONFIG_COMMON_CLK_MT8196_MFGCFG) += clk-mt8196-mfg.o
obj-$(CONFIG_COMMON_CLK_MT8196_MMSYS) += clk-mt8196-disp0.o clk-mt8196-disp1.o clk-mt8196-vdisp_ao.o \
clk-mt8196-ovl0.o clk-mt8196-ovl1.o
obj-$(CONFIG_COMMON_CLK_MT8196_PEXTPSYS) += clk-mt8196-pextp.o
obj-$(CONFIG_COMMON_CLK_MT8196_UFSSYS) += clk-mt8196-ufs_ao.o
obj-$(CONFIG_COMMON_CLK_MT8196_VDECSYS) += clk-mt8196-vdec.o
obj-$(CONFIG_COMMON_CLK_MT8196_VENCSYS) += clk-mt8196-venc.o
obj-$(CONFIG_COMMON_CLK_MT8365) += clk-mt8365-apmixedsys.o clk-mt8365.o
obj-$(CONFIG_COMMON_CLK_MT8365_APU) += clk-mt8365-apu.o
obj-$(CONFIG_COMMON_CLK_MT8365_CAM) += clk-mt8365-cam.o

117
drivers/clk/mediatek/clk-gate.c
View File

@ -5,6 +5,7 @@
*/
#include <linux/clk-provider.h>
#include <linux/dev_printk.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/printk.h>
@ -12,15 +13,14 @@
#include <linux/slab.h>
#include <linux/types.h>
#include "clk-mtk.h"
#include "clk-gate.h"
struct mtk_clk_gate {
struct clk_hw hw;
struct regmap *regmap;
int set_ofs;
int clr_ofs;
int sta_ofs;
u8 bit;
struct regmap *regmap_hwv;
const struct mtk_gate *gate;
};
static inline struct mtk_clk_gate *to_mtk_clk_gate(struct clk_hw *hw)
@ -33,9 +33,9 @@ static u32 mtk_get_clockgating(struct clk_hw *hw)
struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
u32 val;
regmap_read(cg->regmap, cg->sta_ofs, &val);
regmap_read(cg->regmap, cg->gate->regs->sta_ofs, &val);
return val & BIT(cg->bit);
return val & BIT(cg->gate->shift);
}
static int mtk_cg_bit_is_cleared(struct clk_hw *hw)
@ -52,28 +52,30 @@ static void mtk_cg_set_bit(struct clk_hw *hw)
{
struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
regmap_write(cg->regmap, cg->set_ofs, BIT(cg->bit));
regmap_write(cg->regmap, cg->gate->regs->set_ofs, BIT(cg->gate->shift));
}
static void mtk_cg_clr_bit(struct clk_hw *hw)
{
struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit));
regmap_write(cg->regmap, cg->gate->regs->clr_ofs, BIT(cg->gate->shift));
}
static void mtk_cg_set_bit_no_setclr(struct clk_hw *hw)
{
struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
regmap_set_bits(cg->regmap, cg->sta_ofs, BIT(cg->bit));
regmap_set_bits(cg->regmap, cg->gate->regs->sta_ofs,
BIT(cg->gate->shift));
}
static void mtk_cg_clr_bit_no_setclr(struct clk_hw *hw)
{
struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
regmap_clear_bits(cg->regmap, cg->sta_ofs, BIT(cg->bit));
regmap_clear_bits(cg->regmap, cg->gate->regs->sta_ofs,
BIT(cg->gate->shift));
}
static int mtk_cg_enable(struct clk_hw *hw)
@ -100,6 +102,32 @@ static void mtk_cg_disable_inv(struct clk_hw *hw)
mtk_cg_clr_bit(hw);
}
static int mtk_cg_hwv_set_en(struct clk_hw *hw, bool enable)
{
struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
u32 val;
regmap_write(cg->regmap_hwv,
enable ? cg->gate->hwv_regs->set_ofs :
cg->gate->hwv_regs->clr_ofs,
BIT(cg->gate->shift));
return regmap_read_poll_timeout_atomic(cg->regmap_hwv,
cg->gate->hwv_regs->sta_ofs, val,
val & BIT(cg->gate->shift), 0,
MTK_WAIT_HWV_DONE_US);
}
static int mtk_cg_hwv_enable(struct clk_hw *hw)
{
return mtk_cg_hwv_set_en(hw, true);
}
static void mtk_cg_hwv_disable(struct clk_hw *hw)
{
mtk_cg_hwv_set_en(hw, false);
}
static int mtk_cg_enable_no_setclr(struct clk_hw *hw)
{
mtk_cg_clr_bit_no_setclr(hw);
@ -124,6 +152,15 @@ static void mtk_cg_disable_inv_no_setclr(struct clk_hw *hw)
mtk_cg_clr_bit_no_setclr(hw);
}
static bool mtk_cg_uses_hwv(const struct clk_ops *ops)
{
if (ops == &mtk_clk_gate_hwv_ops_setclr ||
ops == &mtk_clk_gate_hwv_ops_setclr_inv)
return true;
return false;
}
const struct clk_ops mtk_clk_gate_ops_setclr = {
.is_enabled = mtk_cg_bit_is_cleared,
.enable = mtk_cg_enable,
@ -138,6 +175,20 @@ const struct clk_ops mtk_clk_gate_ops_setclr_inv = {
};
EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_setclr_inv);
const struct clk_ops mtk_clk_gate_hwv_ops_setclr = {
.is_enabled = mtk_cg_bit_is_cleared,
.enable = mtk_cg_hwv_enable,
.disable = mtk_cg_hwv_disable,
};
EXPORT_SYMBOL_GPL(mtk_clk_gate_hwv_ops_setclr);
const struct clk_ops mtk_clk_gate_hwv_ops_setclr_inv = {
.is_enabled = mtk_cg_bit_is_set,
.enable = mtk_cg_hwv_enable,
.disable = mtk_cg_hwv_disable,
};
EXPORT_SYMBOL_GPL(mtk_clk_gate_hwv_ops_setclr_inv);
const struct clk_ops mtk_clk_gate_ops_no_setclr = {
.is_enabled = mtk_cg_bit_is_cleared,
.enable = mtk_cg_enable_no_setclr,
@ -152,12 +203,10 @@ const struct clk_ops mtk_clk_gate_ops_no_setclr_inv = {
};
EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_no_setclr_inv);
static struct clk_hw *mtk_clk_register_gate(struct device *dev, const char *name,
const char *parent_name,
struct regmap *regmap, int set_ofs,
int clr_ofs, int sta_ofs, u8 bit,
const struct clk_ops *ops,
unsigned long flags)
static struct clk_hw *mtk_clk_register_gate(struct device *dev,
const struct mtk_gate *gate,
struct regmap *regmap,
struct regmap *regmap_hwv)
{
struct mtk_clk_gate *cg;
int ret;
@ -167,18 +216,19 @@ static struct clk_hw *mtk_clk_register_gate(struct device *dev, const char *name
if (!cg)
return ERR_PTR(-ENOMEM);
init.name = name;
init.flags = flags | CLK_SET_RATE_PARENT;
init.parent_names = parent_name ? &parent_name : NULL;
init.num_parents = parent_name ? 1 : 0;
init.ops = ops;
init.name = gate->name;
init.flags = gate->flags | CLK_SET_RATE_PARENT;
init.parent_names = gate->parent_name ? &gate->parent_name : NULL;
init.num_parents = gate->parent_name ? 1 : 0;
init.ops = gate->ops;
if (mtk_cg_uses_hwv(init.ops) && !regmap_hwv)
return dev_err_ptr_probe(
dev, -ENXIO,
"regmap not found for hardware voter clocks\n");
cg->regmap = regmap;
cg->set_ofs = set_ofs;
cg->clr_ofs = clr_ofs;
cg->sta_ofs = sta_ofs;
cg->bit = bit;
cg->regmap_hwv = regmap_hwv;
cg->gate = gate;
cg->hw.init = &init;
ret = clk_hw_register(dev, &cg->hw);
@ -209,6 +259,7 @@ int mtk_clk_register_gates(struct device *dev, struct device_node *node,
int i;
struct clk_hw *hw;
struct regmap *regmap;
struct regmap *regmap_hwv;
if (!clk_data)
return -ENOMEM;
@ -219,6 +270,12 @@ int mtk_clk_register_gates(struct device *dev, struct device_node *node,
return PTR_ERR(regmap);
}
regmap_hwv = mtk_clk_get_hwv_regmap(node);
if (IS_ERR(regmap_hwv))
return dev_err_probe(
dev, PTR_ERR(regmap_hwv),
"Cannot find hardware voter regmap for %pOF\n", node);
for (i = 0; i < num; i++) {
const struct mtk_gate *gate = &clks[i];
@ -228,13 +285,7 @@ int mtk_clk_register_gates(struct device *dev, struct device_node *node,
continue;
}
hw = mtk_clk_register_gate(dev, gate->name, gate->parent_name,
regmap,
gate->regs->set_ofs,
gate->regs->clr_ofs,
gate->regs->sta_ofs,
gate->shift, gate->ops,
gate->flags);
hw = mtk_clk_register_gate(dev, gate, regmap, regmap_hwv);
if (IS_ERR(hw)) {
pr_err("Failed to register clk %s: %pe\n", gate->name,

3
drivers/clk/mediatek/clk-gate.h
View File

@ -19,6 +19,8 @@ extern const struct clk_ops mtk_clk_gate_ops_setclr;
extern const struct clk_ops mtk_clk_gate_ops_setclr_inv;
extern const struct clk_ops mtk_clk_gate_ops_no_setclr;
extern const struct clk_ops mtk_clk_gate_ops_no_setclr_inv;
extern const struct clk_ops mtk_clk_gate_hwv_ops_setclr;
extern const struct clk_ops mtk_clk_gate_hwv_ops_setclr_inv;
struct mtk_gate_regs {
u32 sta_ofs;
@ -31,6 +33,7 @@ struct mtk_gate {
const char *name;
const char *parent_name;
const struct mtk_gate_regs *regs;
const struct mtk_gate_regs *hwv_regs;
int shift;
const struct clk_ops *ops;
unsigned long flags;

1
drivers/clk/mediatek/clk-mt7622-aud.c
View File

@ -75,6 +75,7 @@ static const struct mtk_gate audio_clks[] = {
GATE_AUDIO1(CLK_AUDIO_A1SYS, "audio_a1sys", "a1sys_hp_sel", 21),
GATE_AUDIO1(CLK_AUDIO_A2SYS, "audio_a2sys", "a2sys_hp_sel", 22),
GATE_AUDIO1(CLK_AUDIO_AFE_CONN, "audio_afe_conn", "a1sys_hp_sel", 23),
GATE_AUDIO1(CLK_AUDIO_AFE_MRGIF, "audio_afe_mrgif", "aud_mux1_sel", 25),
/* AUDIO2 */
GATE_AUDIO2(CLK_AUDIO_UL1, "audio_ul1", "a1sys_hp_sel", 0),
GATE_AUDIO2(CLK_AUDIO_UL2, "audio_ul2", "a1sys_hp_sel", 1),

2
drivers/clk/mediatek/clk-mt8195-infra_ao.c
View File

@ -103,7 +103,7 @@ static const struct mtk_gate infra_ao_clks[] = {
GATE_INFRA_AO0(CLK_INFRA_AO_CQ_DMA_FPC, "infra_ao_cq_dma_fpc", "fpc", 28),
GATE_INFRA_AO0(CLK_INFRA_AO_UART5, "infra_ao_uart5", "top_uart", 29),
/* INFRA_AO1 */
GATE_INFRA_AO1(CLK_INFRA_AO_HDMI_26M, "infra_ao_hdmi_26m", "clk26m", 0),
GATE_INFRA_AO1(CLK_INFRA_AO_HDMI_26M, "infra_ao_hdmi_26m", "top_hdmi_xtal", 0),
GATE_INFRA_AO1(CLK_INFRA_AO_SPI0, "infra_ao_spi0", "top_spi", 1),
GATE_INFRA_AO1(CLK_INFRA_AO_MSDC0, "infra_ao_msdc0", "top_msdc50_0_hclk", 2),
GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1, "infra_ao_msdc1", "top_axi", 4),

204
drivers/clk/mediatek/clk-mt8196-apmixedsys.c Normal file
View File

@ -0,0 +1,204 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2025 MediaTek Inc.
* Guangjie Song <guangjie.song@mediatek.com>
* Copyright (c) 2025 Collabora Ltd.
* Laura Nao <laura.nao@collabora.com>
*/
#include <dt-bindings/clock/mediatek,mt8196-clock.h>
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-pll.h"
/* APMIXEDSYS PLL control register offsets */
#define MAINPLL_CON0 0x250
#define MAINPLL_CON1 0x254
#define UNIVPLL_CON0 0x264
#define UNIVPLL_CON1 0x268
#define MSDCPLL_CON0 0x278
#define MSDCPLL_CON1 0x27c
#define ADSPPLL_CON0 0x28c
#define ADSPPLL_CON1 0x290
#define EMIPLL_CON0 0x2a0
#define EMIPLL_CON1 0x2a4
#define EMIPLL2_CON0 0x2b4
#define EMIPLL2_CON1 0x2b8
#define NET1PLL_CON0 0x2c8
#define NET1PLL_CON1 0x2cc
#define SGMIIPLL_CON0 0x2dc
#define SGMIIPLL_CON1 0x2e0
/* APMIXEDSYS_GP2 PLL control register offsets*/
#define MAINPLL2_CON0 0x250
#define MAINPLL2_CON1 0x254
#define UNIVPLL2_CON0 0x264
#define UNIVPLL2_CON1 0x268
#define MMPLL2_CON0 0x278
#define MMPLL2_CON1 0x27c
#define IMGPLL_CON0 0x28c
#define IMGPLL_CON1 0x290
#define TVDPLL1_CON0 0x2a0
#define TVDPLL1_CON1 0x2a4
#define TVDPLL2_CON0 0x2b4
#define TVDPLL2_CON1 0x2b8
#define TVDPLL3_CON0 0x2c8
#define TVDPLL3_CON1 0x2cc
#define PLLEN_ALL 0x080
#define PLLEN_ALL_SET 0x084
#define PLLEN_ALL_CLR 0x088
#define FENC_STATUS_CON0 0x03c
#define MT8196_PLL_FMAX (3800UL * MHZ)
#define MT8196_PLL_FMIN (1500UL * MHZ)
#define MT8196_INTEGER_BITS 8
#define PLL_FENC(_id, _name, _reg, _fenc_sta_ofs, _fenc_sta_bit,\
_flags, _pd_reg, _pd_shift, \
_pcw_reg, _pcw_shift, _pcwbits, \
_pll_en_bit) { \
.id = _id, \
.name = _name, \
.reg = _reg, \
.fenc_sta_ofs = _fenc_sta_ofs, \
.fenc_sta_bit = _fenc_sta_bit, \
.flags = _flags, \
.fmax = MT8196_PLL_FMAX, \
.fmin = MT8196_PLL_FMIN, \
.pd_reg = _pd_reg, \
.pd_shift = _pd_shift, \
.pcw_reg = _pcw_reg, \
.pcw_shift = _pcw_shift, \
.pcwbits = _pcwbits, \
.pcwibits = MT8196_INTEGER_BITS, \
.en_reg = PLLEN_ALL, \
.en_set_reg = PLLEN_ALL_SET, \
.en_clr_reg = PLLEN_ALL_CLR, \
.pll_en_bit = _pll_en_bit, \
.ops = &mtk_pll_fenc_clr_set_ops, \
}
struct mtk_pll_desc {
const struct mtk_pll_data *clks;
size_t num_clks;
};
static const struct mtk_pll_data apmixed_plls[] = {
PLL_FENC(CLK_APMIXED_MAINPLL, "mainpll", MAINPLL_CON0, FENC_STATUS_CON0,
7, PLL_AO, MAINPLL_CON1, 24, MAINPLL_CON1, 0, 22, 0),
PLL_FENC(CLK_APMIXED_UNIVPLL, "univpll", UNIVPLL_CON0, FENC_STATUS_CON0,
6, 0, UNIVPLL_CON1, 24, UNIVPLL_CON1, 0, 22, 1),
PLL_FENC(CLK_APMIXED_MSDCPLL, "msdcpll", MSDCPLL_CON0, FENC_STATUS_CON0,
5, 0, MSDCPLL_CON1, 24, MSDCPLL_CON1, 0, 22, 2),
PLL_FENC(CLK_APMIXED_ADSPPLL, "adsppll", ADSPPLL_CON0, FENC_STATUS_CON0,
4, 0, ADSPPLL_CON1, 24, ADSPPLL_CON1, 0, 22, 3),
PLL_FENC(CLK_APMIXED_EMIPLL, "emipll", EMIPLL_CON0, FENC_STATUS_CON0, 3,
PLL_AO, EMIPLL_CON1, 24, EMIPLL_CON1, 0, 22, 4),
PLL_FENC(CLK_APMIXED_EMIPLL2, "emipll2", EMIPLL2_CON0, FENC_STATUS_CON0,
2, PLL_AO, EMIPLL2_CON1, 24, EMIPLL2_CON1, 0, 22, 5),
PLL_FENC(CLK_APMIXED_NET1PLL, "net1pll", NET1PLL_CON0, FENC_STATUS_CON0,
1, 0, NET1PLL_CON1, 24, NET1PLL_CON1, 0, 22, 6),
PLL_FENC(CLK_APMIXED_SGMIIPLL, "sgmiipll", SGMIIPLL_CON0, FENC_STATUS_CON0,
0, 0, SGMIIPLL_CON1, 24, SGMIIPLL_CON1, 0, 22, 7),
};
static const struct mtk_pll_desc apmixed_desc = {
.clks = apmixed_plls,
.num_clks = ARRAY_SIZE(apmixed_plls),
};
static const struct mtk_pll_data apmixed2_plls[] = {
PLL_FENC(CLK_APMIXED2_MAINPLL2, "mainpll2", MAINPLL2_CON0, FENC_STATUS_CON0,
6, 0, MAINPLL2_CON1, 24, MAINPLL2_CON1, 0, 22, 0),
PLL_FENC(CLK_APMIXED2_UNIVPLL2, "univpll2", UNIVPLL2_CON0, FENC_STATUS_CON0,
5, 0, UNIVPLL2_CON1, 24, UNIVPLL2_CON1, 0, 22, 1),
PLL_FENC(CLK_APMIXED2_MMPLL2, "mmpll2", MMPLL2_CON0, FENC_STATUS_CON0,
4, 0, MMPLL2_CON1, 24, MMPLL2_CON1, 0, 22, 2),
PLL_FENC(CLK_APMIXED2_IMGPLL, "imgpll", IMGPLL_CON0, FENC_STATUS_CON0,
3, 0, IMGPLL_CON1, 24, IMGPLL_CON1, 0, 22, 3),
PLL_FENC(CLK_APMIXED2_TVDPLL1, "tvdpll1", TVDPLL1_CON0, FENC_STATUS_CON0,
2, 0, TVDPLL1_CON1, 24, TVDPLL1_CON1, 0, 22, 4),
PLL_FENC(CLK_APMIXED2_TVDPLL2, "tvdpll2", TVDPLL2_CON0, FENC_STATUS_CON0,
1, 0, TVDPLL2_CON1, 24, TVDPLL2_CON1, 0, 22, 5),
PLL_FENC(CLK_APMIXED2_TVDPLL3, "tvdpll3", TVDPLL3_CON0, FENC_STATUS_CON0,
0, 0, TVDPLL3_CON1, 24, TVDPLL3_CON1, 0, 22, 6),
};
static const struct mtk_pll_desc apmixed2_desc = {
.clks = apmixed2_plls,
.num_clks = ARRAY_SIZE(apmixed2_plls),
};
static int clk_mt8196_apmixed_probe(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
const struct mtk_pll_desc *mcd;
int r;
mcd = device_get_match_data(&pdev->dev);
if (!mcd)
return -EINVAL;
clk_data = mtk_alloc_clk_data(mcd->num_clks);
if (!clk_data)
return -ENOMEM;
r = mtk_clk_register_plls(node, mcd->clks, mcd->num_clks, clk_data);
if (r)
goto free_apmixed_data;
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
goto unregister_plls;
platform_set_drvdata(pdev, clk_data);
return r;
unregister_plls:
mtk_clk_unregister_plls(mcd->clks, mcd->num_clks, clk_data);
free_apmixed_data:
mtk_free_clk_data(clk_data);
return r;
}
static void clk_mt8196_apmixed_remove(struct platform_device *pdev)
{
const struct mtk_pll_desc *mcd = device_get_match_data(&pdev->dev);
struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
struct device_node *node = pdev->dev.of_node;
of_clk_del_provider(node);
mtk_clk_unregister_plls(mcd->clks, mcd->num_clks, clk_data);
mtk_free_clk_data(clk_data);
}
static const struct of_device_id of_match_clk_mt8196_apmixed[] = {
{ .compatible = "mediatek,mt8196-apmixedsys", .data = &apmixed_desc },
{ .compatible = "mediatek,mt8196-apmixedsys-gp2",
.data = &apmixed2_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_apmixed);
static struct platform_driver clk_mt8196_apmixed_drv = {
.probe = clk_mt8196_apmixed_probe,
.remove = clk_mt8196_apmixed_remove,
.driver = {
.name = "clk-mt8196-apmixed",
.of_match_table = of_match_clk_mt8196_apmixed,
},
};
module_platform_driver(clk_mt8196_apmixed_drv);
MODULE_DESCRIPTION("MediaTek MT8196 apmixedsys clocks driver");
MODULE_LICENSE("GPL");

170
drivers/clk/mediatek/clk-mt8196-disp0.c Normal file
View File

@ -0,0 +1,170 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2025 MediaTek Inc.
* Guangjie Song <guangjie.song@mediatek.com>
* Copyright (c) 2025 Collabora Ltd.
* Laura Nao <laura.nao@collabora.com>
*/
#include <dt-bindings/clock/mediatek,mt8196-clock.h>
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
static const struct mtk_gate_regs mm0_cg_regs = {
.set_ofs = 0x104,
.clr_ofs = 0x108,
.sta_ofs = 0x100,
};
static const struct mtk_gate_regs mm0_hwv_regs = {
.set_ofs = 0x0020,
.clr_ofs = 0x0024,
.sta_ofs = 0x2c10,
};
static const struct mtk_gate_regs mm1_cg_regs = {
.set_ofs = 0x114,
.clr_ofs = 0x118,
.sta_ofs = 0x110,
};
static const struct mtk_gate_regs mm1_hwv_regs = {
.set_ofs = 0x0028,
.clr_ofs = 0x002c,
.sta_ofs = 0x2c14,
};
#define GATE_MM0(_id, _name, _parent, _shift) { \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &mm0_cg_regs, \
.shift = _shift, \
.flags = CLK_OPS_PARENT_ENABLE, \
.ops = &mtk_clk_gate_ops_setclr,\
}
#define GATE_HWV_MM0(_id, _name, _parent, _shift) { \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &mm0_cg_regs, \
.hwv_regs = &mm0_hwv_regs, \
.shift = _shift, \
.ops = &mtk_clk_gate_hwv_ops_setclr, \
.flags = CLK_OPS_PARENT_ENABLE \
}
#define GATE_MM1(_id, _name, _parent, _shift) { \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &mm1_cg_regs, \
.shift = _shift, \
.flags = CLK_OPS_PARENT_ENABLE, \
.ops = &mtk_clk_gate_ops_setclr,\
}
#define GATE_HWV_MM1(_id, _name, _parent, _shift) { \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &mm1_cg_regs, \
.hwv_regs = &mm1_hwv_regs, \
.shift = _shift, \
.ops = &mtk_clk_gate_hwv_ops_setclr, \
.flags = CLK_OPS_PARENT_ENABLE, \
}
static const struct mtk_gate mm_clks[] = {
/* MM0 */
GATE_HWV_MM0(CLK_MM_CONFIG, "mm_config", "disp", 0),
GATE_HWV_MM0(CLK_MM_DISP_MUTEX0, "mm_disp_mutex0", "disp", 1),
GATE_HWV_MM0(CLK_MM_DISP_AAL0, "mm_disp_aal0", "disp", 2),
GATE_HWV_MM0(CLK_MM_DISP_AAL1, "mm_disp_aal1", "disp", 3),
GATE_MM0(CLK_MM_DISP_C3D0, "mm_disp_c3d0", "disp", 4),
GATE_MM0(CLK_MM_DISP_C3D1, "mm_disp_c3d1", "disp", 5),
GATE_MM0(CLK_MM_DISP_C3D2, "mm_disp_c3d2", "disp", 6),
GATE_MM0(CLK_MM_DISP_C3D3, "mm_disp_c3d3", "disp", 7),
GATE_MM0(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0", "disp", 8),
GATE_MM0(CLK_MM_DISP_CCORR1, "mm_disp_ccorr1", "disp", 9),
GATE_MM0(CLK_MM_DISP_CCORR2, "mm_disp_ccorr2", "disp", 10),
GATE_MM0(CLK_MM_DISP_CCORR3, "mm_disp_ccorr3", "disp", 11),
GATE_MM0(CLK_MM_DISP_CHIST0, "mm_disp_chist0", "disp", 12),
GATE_MM0(CLK_MM_DISP_CHIST1, "mm_disp_chist1", "disp", 13),
GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "disp", 14),
GATE_MM0(CLK_MM_DISP_COLOR1, "mm_disp_color1", "disp", 15),
GATE_MM0(CLK_MM_DISP_DITHER0, "mm_disp_dither0", "disp", 16),
GATE_MM0(CLK_MM_DISP_DITHER1, "mm_disp_dither1", "disp", 17),
GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC0, "mm_disp_dli_async0", "disp", 18),
GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC1, "mm_disp_dli_async1", "disp", 19),
GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC2, "mm_disp_dli_async2", "disp", 20),
GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC3, "mm_disp_dli_async3", "disp", 21),
GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC4, "mm_disp_dli_async4", "disp", 22),
GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC5, "mm_disp_dli_async5", "disp", 23),
GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC6, "mm_disp_dli_async6", "disp", 24),
GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC7, "mm_disp_dli_async7", "disp", 25),
GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC8, "mm_disp_dli_async8", "disp", 26),
GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC9, "mm_disp_dli_async9", "disp", 27),
GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC10, "mm_disp_dli_async10", "disp", 28),
GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC11, "mm_disp_dli_async11", "disp", 29),
GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC12, "mm_disp_dli_async12", "disp", 30),
GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC13, "mm_disp_dli_async13", "disp", 31),
/* MM1 */
GATE_HWV_MM1(CLK_MM_DISP_DLI_ASYNC14, "mm_disp_dli_async14", "disp", 0),
GATE_HWV_MM1(CLK_MM_DISP_DLI_ASYNC15, "mm_disp_dli_async15", "disp", 1),
GATE_HWV_MM1(CLK_MM_DISP_DLO_ASYNC0, "mm_disp_dlo_async0", "disp", 2),
GATE_HWV_MM1(CLK_MM_DISP_DLO_ASYNC1, "mm_disp_dlo_async1", "disp", 3),
GATE_HWV_MM1(CLK_MM_DISP_DLO_ASYNC2, "mm_disp_dlo_async2", "disp", 4),
GATE_HWV_MM1(CLK_MM_DISP_DLO_ASYNC3, "mm_disp_dlo_async3", "disp", 5),
GATE_HWV_MM1(CLK_MM_DISP_DLO_ASYNC4, "mm_disp_dlo_async4", "disp", 6),
GATE_HWV_MM1(CLK_MM_DISP_DLO_ASYNC5, "mm_disp_dlo_async5", "disp", 7),
GATE_HWV_MM1(CLK_MM_DISP_DLO_ASYNC6, "mm_disp_dlo_async6", "disp", 8),
GATE_HWV_MM1(CLK_MM_DISP_DLO_ASYNC7, "mm_disp_dlo_async7", "disp", 9),
GATE_HWV_MM1(CLK_MM_DISP_DLO_ASYNC8, "mm_disp_dlo_async8", "disp", 10),
GATE_MM1(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0", "disp", 11),
GATE_MM1(CLK_MM_DISP_GAMMA1, "mm_disp_gamma1", "disp", 12),
GATE_MM1(CLK_MM_MDP_AAL0, "mm_mdp_aal0", "disp", 13),
GATE_MM1(CLK_MM_MDP_AAL1, "mm_mdp_aal1", "disp", 14),
GATE_HWV_MM1(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "disp", 15),
GATE_HWV_MM1(CLK_MM_DISP_POSTMASK0, "mm_disp_postmask0", "disp", 16),
GATE_HWV_MM1(CLK_MM_DISP_POSTMASK1, "mm_disp_postmask1", "disp", 17),
GATE_HWV_MM1(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "disp", 18),
GATE_HWV_MM1(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "disp", 19),
GATE_HWV_MM1(CLK_MM_DISP_SPR0, "mm_disp_spr0", "disp", 20),
GATE_MM1(CLK_MM_DISP_TDSHP0, "mm_disp_tdshp0", "disp", 21),
GATE_MM1(CLK_MM_DISP_TDSHP1, "mm_disp_tdshp1", "disp", 22),
GATE_HWV_MM1(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "disp", 23),
GATE_HWV_MM1(CLK_MM_DISP_Y2R0, "mm_disp_y2r0", "disp", 24),
GATE_HWV_MM1(CLK_MM_SMI_SUB_COMM0, "mm_ssc", "disp", 25),
GATE_HWV_MM1(CLK_MM_DISP_FAKE_ENG0, "mm_disp_fake_eng0", "disp", 26),
};
static const struct mtk_clk_desc mm_mcd = {
.clks = mm_clks,
.num_clks = ARRAY_SIZE(mm_clks),
};
static const struct platform_device_id clk_mt8196_disp0_id_table[] = {
{ .name = "clk-mt8196-disp0", .driver_data = (kernel_ulong_t)&mm_mcd },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(platform, clk_mt8196_disp0_id_table);
static struct platform_driver clk_mt8196_disp0_drv = {
.probe = mtk_clk_pdev_probe,
.remove = mtk_clk_pdev_remove,
.driver = {
.name = "clk-mt8196-disp0",
},
.id_table = clk_mt8196_disp0_id_table,
};
module_platform_driver(clk_mt8196_disp0_drv);
MODULE_DESCRIPTION("MediaTek MT8196 disp0 clocks driver");
MODULE_LICENSE("GPL");

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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2025 MediaTek Inc.
* Guangjie Song <guangjie.song@mediatek.com>
* Copyright (c) 2025 Collabora Ltd.
* Laura Nao <laura.nao@collabora.com>
*/
#include <dt-bindings/clock/mediatek,mt8196-clock.h>
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
static const struct mtk_gate_regs mm10_cg_regs = {
.set_ofs = 0x104,
.clr_ofs = 0x108,
.sta_ofs = 0x100,
};
static const struct mtk_gate_regs mm10_hwv_regs = {
.set_ofs = 0x0010,
.clr_ofs = 0x0014,
.sta_ofs = 0x2c08,
};
static const struct mtk_gate_regs mm11_cg_regs = {
.set_ofs = 0x114,
.clr_ofs = 0x118,
.sta_ofs = 0x110,
};
static const struct mtk_gate_regs mm11_hwv_regs = {
.set_ofs = 0x0018,
.clr_ofs = 0x001c,
.sta_ofs = 0x2c0c,
};
#define GATE_MM10(_id, _name, _parent, _shift) {\
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &mm10_cg_regs, \
.shift = _shift, \
.flags = CLK_OPS_PARENT_ENABLE, \
.ops = &mtk_clk_gate_ops_setclr,\
}
#define GATE_HWV_MM10(_id, _name, _parent, _shift) { \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &mm10_cg_regs, \
.hwv_regs = &mm10_hwv_regs, \
.shift = _shift, \
.ops = &mtk_clk_gate_hwv_ops_setclr, \
.flags = CLK_OPS_PARENT_ENABLE, \
}
#define GATE_MM11(_id, _name, _parent, _shift) {\
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &mm11_cg_regs, \
.shift = _shift, \
.flags = CLK_OPS_PARENT_ENABLE, \
.ops = &mtk_clk_gate_ops_setclr,\
}
#define GATE_HWV_MM11(_id, _name, _parent, _shift) { \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &mm11_cg_regs, \
.hwv_regs = &mm11_hwv_regs, \
.shift = _shift, \
.ops = &mtk_clk_gate_hwv_ops_setclr, \
}
static const struct mtk_gate mm1_clks[] = {
/* MM10 */
GATE_HWV_MM10(CLK_MM1_DISPSYS1_CONFIG, "mm1_dispsys1_config", "disp", 0),
GATE_HWV_MM10(CLK_MM1_DISPSYS1_S_CONFIG, "mm1_dispsys1_s_config", "disp", 1),
GATE_HWV_MM10(CLK_MM1_DISP_MUTEX0, "mm1_disp_mutex0", "disp", 2),
GATE_HWV_MM10(CLK_MM1_DISP_DLI_ASYNC20, "mm1_disp_dli_async20", "disp", 3),
GATE_HWV_MM10(CLK_MM1_DISP_DLI_ASYNC21, "mm1_disp_dli_async21", "disp", 4),
GATE_HWV_MM10(CLK_MM1_DISP_DLI_ASYNC22, "mm1_disp_dli_async22", "disp", 5),
GATE_HWV_MM10(CLK_MM1_DISP_DLI_ASYNC23, "mm1_disp_dli_async23", "disp", 6),
GATE_HWV_MM10(CLK_MM1_DISP_DLI_ASYNC24, "mm1_disp_dli_async24", "disp", 7),
GATE_HWV_MM10(CLK_MM1_DISP_DLI_ASYNC25, "mm1_disp_dli_async25", "disp", 8),
GATE_HWV_MM10(CLK_MM1_DISP_DLI_ASYNC26, "mm1_disp_dli_async26", "disp", 9),
GATE_HWV_MM10(CLK_MM1_DISP_DLI_ASYNC27, "mm1_disp_dli_async27", "disp", 10),
GATE_HWV_MM10(CLK_MM1_DISP_DLI_ASYNC28, "mm1_disp_dli_async28", "disp", 11),
GATE_HWV_MM10(CLK_MM1_DISP_RELAY0, "mm1_disp_relay0", "disp", 12),
GATE_HWV_MM10(CLK_MM1_DISP_RELAY1, "mm1_disp_relay1", "disp", 13),
GATE_HWV_MM10(CLK_MM1_DISP_RELAY2, "mm1_disp_relay2", "disp", 14),
GATE_HWV_MM10(CLK_MM1_DISP_RELAY3, "mm1_disp_relay3", "disp", 15),
GATE_HWV_MM10(CLK_MM1_DISP_DP_INTF0, "mm1_DP_CLK", "disp", 16),
GATE_HWV_MM10(CLK_MM1_DISP_DP_INTF1, "mm1_disp_dp_intf1", "disp", 17),
GATE_HWV_MM10(CLK_MM1_DISP_DSC_WRAP0, "mm1_disp_dsc_wrap0", "disp", 18),
GATE_HWV_MM10(CLK_MM1_DISP_DSC_WRAP1, "mm1_disp_dsc_wrap1", "disp", 19),
GATE_HWV_MM10(CLK_MM1_DISP_DSC_WRAP2, "mm1_disp_dsc_wrap2", "disp", 20),
GATE_HWV_MM10(CLK_MM1_DISP_DSC_WRAP3, "mm1_disp_dsc_wrap3", "disp", 21),
GATE_HWV_MM10(CLK_MM1_DISP_DSI0, "mm1_CLK0", "disp", 22),
GATE_HWV_MM10(CLK_MM1_DISP_DSI1, "mm1_CLK1", "disp", 23),
GATE_HWV_MM10(CLK_MM1_DISP_DSI2, "mm1_CLK2", "disp", 24),
GATE_HWV_MM10(CLK_MM1_DISP_DVO0, "mm1_disp_dvo0", "disp", 25),
GATE_HWV_MM10(CLK_MM1_DISP_GDMA0, "mm1_disp_gdma0", "disp", 26),
GATE_HWV_MM10(CLK_MM1_DISP_MERGE0, "mm1_disp_merge0", "disp", 27),
GATE_HWV_MM10(CLK_MM1_DISP_MERGE1, "mm1_disp_merge1", "disp", 28),
GATE_HWV_MM10(CLK_MM1_DISP_MERGE2, "mm1_disp_merge2", "disp", 29),
GATE_HWV_MM10(CLK_MM1_DISP_ODDMR0, "mm1_disp_oddmr0", "disp", 30),
GATE_HWV_MM10(CLK_MM1_DISP_POSTALIGN0, "mm1_disp_postalign0", "disp", 31),
/* MM11 */
GATE_HWV_MM11(CLK_MM1_DISP_DITHER2, "mm1_disp_dither2", "disp", 0),
GATE_HWV_MM11(CLK_MM1_DISP_R2Y0, "mm1_disp_r2y0", "disp", 1),
GATE_HWV_MM11(CLK_MM1_DISP_SPLITTER0, "mm1_disp_splitter0", "disp", 2),
GATE_HWV_MM11(CLK_MM1_DISP_SPLITTER1, "mm1_disp_splitter1", "disp", 3),
GATE_HWV_MM11(CLK_MM1_DISP_SPLITTER2, "mm1_disp_splitter2", "disp", 4),
GATE_HWV_MM11(CLK_MM1_DISP_SPLITTER3, "mm1_disp_splitter3", "disp", 5),
GATE_HWV_MM11(CLK_MM1_DISP_VDCM0, "mm1_disp_vdcm0", "disp", 6),
GATE_HWV_MM11(CLK_MM1_DISP_WDMA1, "mm1_disp_wdma1", "disp", 7),
GATE_HWV_MM11(CLK_MM1_DISP_WDMA2, "mm1_disp_wdma2", "disp", 8),
GATE_HWV_MM11(CLK_MM1_DISP_WDMA3, "mm1_disp_wdma3", "disp", 9),
GATE_HWV_MM11(CLK_MM1_DISP_WDMA4, "mm1_disp_wdma4", "disp", 10),
GATE_HWV_MM11(CLK_MM1_MDP_RDMA1, "mm1_mdp_rdma1", "disp", 11),
GATE_HWV_MM11(CLK_MM1_SMI_LARB0, "mm1_smi_larb0", "disp", 12),
GATE_HWV_MM11(CLK_MM1_MOD1, "mm1_mod1", "clk26m", 13),
GATE_HWV_MM11(CLK_MM1_MOD2, "mm1_mod2", "clk26m", 14),
GATE_HWV_MM11(CLK_MM1_MOD3, "mm1_mod3", "clk26m", 15),
GATE_HWV_MM11(CLK_MM1_MOD4, "mm1_mod4", "dp0", 16),
GATE_HWV_MM11(CLK_MM1_MOD5, "mm1_mod5", "dp1", 17),
GATE_HWV_MM11(CLK_MM1_MOD6, "mm1_mod6", "dp1", 18),
GATE_HWV_MM11(CLK_MM1_CG0, "mm1_cg0", "disp", 20),
GATE_HWV_MM11(CLK_MM1_CG1, "mm1_cg1", "disp", 21),
GATE_HWV_MM11(CLK_MM1_CG2, "mm1_cg2", "disp", 22),
GATE_HWV_MM11(CLK_MM1_CG3, "mm1_cg3", "disp", 23),
GATE_HWV_MM11(CLK_MM1_CG4, "mm1_cg4", "disp", 24),
GATE_HWV_MM11(CLK_MM1_CG5, "mm1_cg5", "disp", 25),
GATE_HWV_MM11(CLK_MM1_CG6, "mm1_cg6", "disp", 26),
GATE_HWV_MM11(CLK_MM1_CG7, "mm1_cg7", "disp", 27),
GATE_HWV_MM11(CLK_MM1_F26M, "mm1_f26m_ck", "clk26m", 28),
};
static const struct mtk_clk_desc mm1_mcd = {
.clks = mm1_clks,
.num_clks = ARRAY_SIZE(mm1_clks),
};
static const struct platform_device_id clk_mt8196_disp1_id_table[] = {
{ .name = "clk-mt8196-disp1", .driver_data = (kernel_ulong_t)&mm1_mcd },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(platform, clk_mt8196_disp1_id_table);
static struct platform_driver clk_mt8196_disp1_drv = {
.probe = mtk_clk_pdev_probe,
.remove = mtk_clk_pdev_remove,
.driver = {
.name = "clk-mt8196-disp1",
},
.id_table = clk_mt8196_disp1_id_table,
};
module_platform_driver(clk_mt8196_disp1_drv);
MODULE_DESCRIPTION("MediaTek MT8196 disp1 clocks driver");
MODULE_LICENSE("GPL");

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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2025 MediaTek Inc.
* Guangjie Song <guangjie.song@mediatek.com>
* Copyright (c) 2025 Collabora Ltd.
* Laura Nao <laura.nao@collabora.com>
*/
#include <dt-bindings/clock/mediatek,mt8196-clock.h>
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
static const struct mtk_gate_regs imp_cg_regs = {
.set_ofs = 0xe08,
.clr_ofs = 0xe04,
.sta_ofs = 0xe00,
};
#define GATE_IMP(_id, _name, _parent, _shift) { \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &imp_cg_regs, \
.shift = _shift, \
.flags = CLK_OPS_PARENT_ENABLE, \
.ops = &mtk_clk_gate_ops_setclr, \
}
static const struct mtk_gate impc_clks[] = {
GATE_IMP(CLK_IMPC_I2C11, "impc_i2c11", "i2c_p", 0),
GATE_IMP(CLK_IMPC_I2C12, "impc_i2c12", "i2c_p", 1),
GATE_IMP(CLK_IMPC_I2C13, "impc_i2c13", "i2c_p", 2),
GATE_IMP(CLK_IMPC_I2C14, "impc_i2c14", "i2c_p", 3),
};
static const struct mtk_clk_desc impc_mcd = {
.clks = impc_clks,
.num_clks = ARRAY_SIZE(impc_clks),
};
static const struct mtk_gate impe_clks[] = {
GATE_IMP(CLK_IMPE_I2C5, "impe_i2c5", "i2c_east", 0),
};
static const struct mtk_clk_desc impe_mcd = {
.clks = impe_clks,
.num_clks = ARRAY_SIZE(impe_clks),
};
static const struct mtk_gate_regs impn_hwv_regs = {
.set_ofs = 0x0000,
.clr_ofs = 0x0004,
.sta_ofs = 0x2c00,
};
#define GATE_HWV_IMPN(_id, _name, _parent, _shift) { \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &imp_cg_regs, \
.hwv_regs = &impn_hwv_regs, \
.shift = _shift, \
.ops = &mtk_clk_gate_hwv_ops_setclr, \
.flags = CLK_OPS_PARENT_ENABLE, \
}
static const struct mtk_gate impn_clks[] = {
GATE_IMP(CLK_IMPN_I2C1, "impn_i2c1", "i2c_north", 0),
GATE_IMP(CLK_IMPN_I2C2, "impn_i2c2", "i2c_north", 1),
GATE_IMP(CLK_IMPN_I2C4, "impn_i2c4", "i2c_north", 2),
GATE_HWV_IMPN(CLK_IMPN_I2C7, "impn_i2c7", "i2c_north", 3),
GATE_IMP(CLK_IMPN_I2C8, "impn_i2c8", "i2c_north", 4),
GATE_IMP(CLK_IMPN_I2C9, "impn_i2c9", "i2c_north", 5),
};
static const struct mtk_clk_desc impn_mcd = {
.clks = impn_clks,
.num_clks = ARRAY_SIZE(impn_clks),
};
static const struct mtk_gate impw_clks[] = {
GATE_IMP(CLK_IMPW_I2C0, "impw_i2c0", "i2c_west", 0),
GATE_IMP(CLK_IMPW_I2C3, "impw_i2c3", "i2c_west", 1),
GATE_IMP(CLK_IMPW_I2C6, "impw_i2c6", "i2c_west", 2),
GATE_IMP(CLK_IMPW_I2C10, "impw_i2c10", "i2c_west", 3),
};
static const struct mtk_clk_desc impw_mcd = {
.clks = impw_clks,
.num_clks = ARRAY_SIZE(impw_clks),
};
static const struct of_device_id of_match_clk_mt8196_imp_iic_wrap[] = {
{ .compatible = "mediatek,mt8196-imp-iic-wrap-c", .data = &impc_mcd },
{ .compatible = "mediatek,mt8196-imp-iic-wrap-e", .data = &impe_mcd },
{ .compatible = "mediatek,mt8196-imp-iic-wrap-n", .data = &impn_mcd },
{ .compatible = "mediatek,mt8196-imp-iic-wrap-w", .data = &impw_mcd },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_imp_iic_wrap);
static struct platform_driver clk_mt8196_imp_iic_wrap_drv = {
.probe = mtk_clk_simple_probe,
.remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8196-imp_iic_wrap",
.of_match_table = of_match_clk_mt8196_imp_iic_wrap,
},
};
module_platform_driver(clk_mt8196_imp_iic_wrap_drv);
MODULE_DESCRIPTION("MediaTek MT8196 I2C Wrapper clocks driver");
MODULE_LICENSE("GPL");

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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2025 MediaTek Inc.
* Guangjie Song <guangjie.song@mediatek.com>
* Copyright (c) 2025 Collabora Ltd.
* Laura Nao <laura.nao@collabora.com>
*/
#include <dt-bindings/clock/mediatek,mt8196-clock.h>
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-pll.h"
#define ARMPLL_LL_CON0 0x008
#define ARMPLL_LL_CON1 0x00c
#define ARMPLL_LL_CON2 0x010
#define ARMPLL_LL_CON3 0x014
#define ARMPLL_BL_CON0 0x008
#define ARMPLL_BL_CON1 0x00c
#define ARMPLL_BL_CON2 0x010
#define ARMPLL_BL_CON3 0x014
#define ARMPLL_B_CON0 0x008
#define ARMPLL_B_CON1 0x00c
#define ARMPLL_B_CON2 0x010
#define ARMPLL_B_CON3 0x014
#define CCIPLL_CON0 0x008
#define CCIPLL_CON1 0x00c
#define CCIPLL_CON2 0x010
#define CCIPLL_CON3 0x014
#define PTPPLL_CON0 0x008
#define PTPPLL_CON1 0x00c
#define PTPPLL_CON2 0x010
#define PTPPLL_CON3 0x014
#define MT8196_PLL_FMAX (3800UL * MHZ)
#define MT8196_PLL_FMIN (1500UL * MHZ)
#define MT8196_INTEGER_BITS 8
#define PLL(_id, _name, _reg, _en_reg, _en_mask, _pll_en_bit, \
_flags, _rst_bar_mask, \
_pd_reg, _pd_shift, _tuner_reg, \
_tuner_en_reg, _tuner_en_bit, \
_pcw_reg, _pcw_shift, _pcwbits) { \
.id = _id, \
.name = _name, \
.reg = _reg, \
.en_reg = _en_reg, \
.en_mask = _en_mask, \
.pll_en_bit = _pll_en_bit, \
.flags = _flags, \
.rst_bar_mask = _rst_bar_mask, \
.fmax = MT8196_PLL_FMAX, \
.fmin = MT8196_PLL_FMIN, \
.pd_reg = _pd_reg, \
.pd_shift = _pd_shift, \
.tuner_reg = _tuner_reg, \
.tuner_en_reg = _tuner_en_reg, \
.tuner_en_bit = _tuner_en_bit, \
.pcw_reg = _pcw_reg, \
.pcw_shift = _pcw_shift, \
.pcwbits = _pcwbits, \
.pcwibits = MT8196_INTEGER_BITS, \
}
static const struct mtk_pll_data cpu_bl_plls[] = {
PLL(CLK_CPBL_ARMPLL_BL, "armpll-bl", ARMPLL_BL_CON0, ARMPLL_BL_CON0, 0,
0, PLL_AO, BIT(0), ARMPLL_BL_CON1, 24, 0, 0, 0, ARMPLL_BL_CON1, 0, 22),
};
static const struct mtk_pll_data cpu_b_plls[] = {
PLL(CLK_CPB_ARMPLL_B, "armpll-b", ARMPLL_B_CON0, ARMPLL_B_CON0, 0, 0,
PLL_AO, BIT(0), ARMPLL_B_CON1, 24, 0, 0, 0, ARMPLL_B_CON1, 0, 22),
};
static const struct mtk_pll_data cpu_ll_plls[] = {
PLL(CLK_CPLL_ARMPLL_LL, "armpll-ll", ARMPLL_LL_CON0, ARMPLL_LL_CON0, 0,
0, PLL_AO, BIT(0), ARMPLL_LL_CON1, 24, 0, 0, 0, ARMPLL_LL_CON1, 0, 22),
};
static const struct mtk_pll_data cci_plls[] = {
PLL(CLK_CCIPLL, "ccipll", CCIPLL_CON0, CCIPLL_CON0, 0, 0, PLL_AO,
BIT(0), CCIPLL_CON1, 24, 0, 0, 0, CCIPLL_CON1, 0, 22),
};
static const struct mtk_pll_data ptp_plls[] = {
PLL(CLK_PTPPLL, "ptppll", PTPPLL_CON0, PTPPLL_CON0, 0, 0, PLL_AO,
BIT(0), PTPPLL_CON1, 24, 0, 0, 0, PTPPLL_CON1, 0, 22),
};
static const struct of_device_id of_match_clk_mt8196_mcu[] = {
{ .compatible = "mediatek,mt8196-armpll-bl-pll-ctrl",
.data = &cpu_bl_plls },
{ .compatible = "mediatek,mt8196-armpll-b-pll-ctrl",
.data = &cpu_b_plls },
{ .compatible = "mediatek,mt8196-armpll-ll-pll-ctrl",
.data = &cpu_ll_plls },
{ .compatible = "mediatek,mt8196-ccipll-pll-ctrl", .data = &cci_plls },
{ .compatible = "mediatek,mt8196-ptppll-pll-ctrl", .data = &ptp_plls },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_mcu);
static int clk_mt8196_mcu_probe(struct platform_device *pdev)
{
const struct mtk_pll_data *plls;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
const int num_plls = 1;
int r;
plls = of_device_get_match_data(&pdev->dev);
if (!plls)
return -EINVAL;
clk_data = mtk_alloc_clk_data(num_plls);
if (!clk_data)
return -ENOMEM;
r = mtk_clk_register_plls(node, plls, num_plls, clk_data);
if (r)
goto free_clk_data;
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
goto unregister_plls;
platform_set_drvdata(pdev, clk_data);
return r;
unregister_plls:
mtk_clk_unregister_plls(plls, num_plls, clk_data);
free_clk_data:
mtk_free_clk_data(clk_data);
return r;
}
static void clk_mt8196_mcu_remove(struct platform_device *pdev)
{
const struct mtk_pll_data *plls = of_device_get_match_data(&pdev->dev);
struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
struct device_node *node = pdev->dev.of_node;
of_clk_del_provider(node);
mtk_clk_unregister_plls(plls, 1, clk_data);
mtk_free_clk_data(clk_data);
}
static struct platform_driver clk_mt8196_mcu_drv = {
.probe = clk_mt8196_mcu_probe,
.remove = clk_mt8196_mcu_remove,
.driver = {
.name = "clk-mt8196-mcu",
.of_match_table = of_match_clk_mt8196_mcu,
},
};
module_platform_driver(clk_mt8196_mcu_drv);
MODULE_DESCRIPTION("MediaTek MT8196 mcusys clocks driver");
MODULE_LICENSE("GPL");

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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2025 MediaTek Inc.
* Guangjie Song <guangjie.song@mediatek.com>
* Copyright (c) 2025 Collabora Ltd.
* Laura Nao <laura.nao@collabora.com>
*/
#include <dt-bindings/clock/mediatek,mt8196-clock.h>
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
static const struct mtk_gate_regs mdp0_cg_regs = {
.set_ofs = 0x104,
.clr_ofs = 0x108,
.sta_ofs = 0x100,
};
static const struct mtk_gate_regs mdp1_cg_regs = {
.set_ofs = 0x114,
.clr_ofs = 0x118,
.sta_ofs = 0x110,
};
static const struct mtk_gate_regs mdp2_cg_regs = {
.set_ofs = 0x124,
.clr_ofs = 0x128,
.sta_ofs = 0x120,
};
#define GATE_MDP0(_id, _name, _parent, _shift) { \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &mdp0_cg_regs, \
.shift = _shift, \
.flags = CLK_OPS_PARENT_ENABLE, \
.ops = &mtk_clk_gate_ops_setclr, \
}
#define GATE_MDP1(_id, _name, _parent, _shift) { \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &mdp1_cg_regs, \
.shift = _shift, \
.ops = &mtk_clk_gate_ops_setclr, \
}
#define GATE_MDP2(_id, _name, _parent, _shift) { \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &mdp2_cg_regs, \
.shift = _shift, \
.flags = CLK_OPS_PARENT_ENABLE, \
.ops = &mtk_clk_gate_ops_setclr, \
}
static const struct mtk_gate mdp1_clks[] = {
/* MDP1-0 */
GATE_MDP0(CLK_MDP1_MDP_MUTEX0, "mdp1_mdp_mutex0", "mdp", 0),
GATE_MDP0(CLK_MDP1_SMI0, "mdp1_smi0", "mdp", 1),
GATE_MDP0(CLK_MDP1_APB_BUS, "mdp1_apb_bus", "mdp", 2),
GATE_MDP0(CLK_MDP1_MDP_RDMA0, "mdp1_mdp_rdma0", "mdp", 3),
GATE_MDP0(CLK_MDP1_MDP_RDMA1, "mdp1_mdp_rdma1", "mdp", 4),
GATE_MDP0(CLK_MDP1_MDP_RDMA2, "mdp1_mdp_rdma2", "mdp", 5),
GATE_MDP0(CLK_MDP1_MDP_BIRSZ0, "mdp1_mdp_birsz0", "mdp", 6),
GATE_MDP0(CLK_MDP1_MDP_HDR0, "mdp1_mdp_hdr0", "mdp", 7),
GATE_MDP0(CLK_MDP1_MDP_AAL0, "mdp1_mdp_aal0", "mdp", 8),
GATE_MDP0(CLK_MDP1_MDP_RSZ0, "mdp1_mdp_rsz0", "mdp", 9),
GATE_MDP0(CLK_MDP1_MDP_RSZ2, "mdp1_mdp_rsz2", "mdp", 10),
GATE_MDP0(CLK_MDP1_MDP_TDSHP0, "mdp1_mdp_tdshp0", "mdp", 11),
GATE_MDP0(CLK_MDP1_MDP_COLOR0, "mdp1_mdp_color0", "mdp", 12),
GATE_MDP0(CLK_MDP1_MDP_WROT0, "mdp1_mdp_wrot0", "mdp", 13),
GATE_MDP0(CLK_MDP1_MDP_WROT1, "mdp1_mdp_wrot1", "mdp", 14),
GATE_MDP0(CLK_MDP1_MDP_WROT2, "mdp1_mdp_wrot2", "mdp", 15),
GATE_MDP0(CLK_MDP1_MDP_FAKE_ENG0, "mdp1_mdp_fake_eng0", "mdp", 16),
GATE_MDP0(CLK_MDP1_APB_DB, "mdp1_apb_db", "mdp", 17),
GATE_MDP0(CLK_MDP1_MDP_DLI_ASYNC0, "mdp1_mdp_dli_async0", "mdp", 18),
GATE_MDP0(CLK_MDP1_MDP_DLI_ASYNC1, "mdp1_mdp_dli_async1", "mdp", 19),
GATE_MDP0(CLK_MDP1_MDP_DLO_ASYNC0, "mdp1_mdp_dlo_async0", "mdp", 20),
GATE_MDP0(CLK_MDP1_MDP_DLO_ASYNC1, "mdp1_mdp_dlo_async1", "mdp", 21),
GATE_MDP0(CLK_MDP1_MDP_DLI_ASYNC2, "mdp1_mdp_dli_async2", "mdp", 22),
GATE_MDP0(CLK_MDP1_MDP_DLO_ASYNC2, "mdp1_mdp_dlo_async2", "mdp", 23),
GATE_MDP0(CLK_MDP1_MDP_DLO_ASYNC3, "mdp1_mdp_dlo_async3", "mdp", 24),
GATE_MDP0(CLK_MDP1_IMG_DL_ASYNC0, "mdp1_img_dl_async0", "mdp", 25),
GATE_MDP0(CLK_MDP1_MDP_RROT0, "mdp1_mdp_rrot0", "mdp", 26),
GATE_MDP0(CLK_MDP1_MDP_MERGE0, "mdp1_mdp_merge0", "mdp", 27),
GATE_MDP0(CLK_MDP1_MDP_C3D0, "mdp1_mdp_c3d0", "mdp", 28),
GATE_MDP0(CLK_MDP1_MDP_FG0, "mdp1_mdp_fg0", "mdp", 29),
GATE_MDP0(CLK_MDP1_MDP_CLA2, "mdp1_mdp_cla2", "mdp", 30),
GATE_MDP0(CLK_MDP1_MDP_DLO_ASYNC4, "mdp1_mdp_dlo_async4", "mdp", 31),
/* MDP1-1 */
GATE_MDP1(CLK_MDP1_VPP_RSZ0, "mdp1_vpp_rsz0", "mdp", 0),
GATE_MDP1(CLK_MDP1_VPP_RSZ1, "mdp1_vpp_rsz1", "mdp", 1),
GATE_MDP1(CLK_MDP1_MDP_DLO_ASYNC5, "mdp1_mdp_dlo_async5", "mdp", 2),
GATE_MDP1(CLK_MDP1_IMG0, "mdp1_img0", "mdp", 3),
GATE_MDP1(CLK_MDP1_F26M, "mdp1_f26m", "clk26m", 27),
/* MDP1-2 */
GATE_MDP2(CLK_MDP1_IMG_DL_RELAY0, "mdp1_img_dl_relay0", "mdp", 0),
GATE_MDP2(CLK_MDP1_IMG_DL_RELAY1, "mdp1_img_dl_relay1", "mdp", 8),
};
static const struct mtk_clk_desc mdp1_mcd = {
.clks = mdp1_clks,
.num_clks = ARRAY_SIZE(mdp1_clks),
.need_runtime_pm = true,
};
static const struct mtk_gate mdp_clks[] = {
/* MDP0 */
GATE_MDP0(CLK_MDP_MDP_MUTEX0, "mdp_mdp_mutex0", "mdp", 0),
GATE_MDP0(CLK_MDP_SMI0, "mdp_smi0", "mdp", 1),
GATE_MDP0(CLK_MDP_APB_BUS, "mdp_apb_bus", "mdp", 2),
GATE_MDP0(CLK_MDP_MDP_RDMA0, "mdp_mdp_rdma0", "mdp", 3),
GATE_MDP0(CLK_MDP_MDP_RDMA1, "mdp_mdp_rdma1", "mdp", 4),
GATE_MDP0(CLK_MDP_MDP_RDMA2, "mdp_mdp_rdma2", "mdp", 5),
GATE_MDP0(CLK_MDP_MDP_BIRSZ0, "mdp_mdp_birsz0", "mdp", 6),
GATE_MDP0(CLK_MDP_MDP_HDR0, "mdp_mdp_hdr0", "mdp", 7),
GATE_MDP0(CLK_MDP_MDP_AAL0, "mdp_mdp_aal0", "mdp", 8),
GATE_MDP0(CLK_MDP_MDP_RSZ0, "mdp_mdp_rsz0", "mdp", 9),
GATE_MDP0(CLK_MDP_MDP_RSZ2, "mdp_mdp_rsz2", "mdp", 10),
GATE_MDP0(CLK_MDP_MDP_TDSHP0, "mdp_mdp_tdshp0", "mdp", 11),
GATE_MDP0(CLK_MDP_MDP_COLOR0, "mdp_mdp_color0", "mdp", 12),
GATE_MDP0(CLK_MDP_MDP_WROT0, "mdp_mdp_wrot0", "mdp", 13),
GATE_MDP0(CLK_MDP_MDP_WROT1, "mdp_mdp_wrot1", "mdp", 14),
GATE_MDP0(CLK_MDP_MDP_WROT2, "mdp_mdp_wrot2", "mdp", 15),
GATE_MDP0(CLK_MDP_MDP_FAKE_ENG0, "mdp_mdp_fake_eng0", "mdp", 16),
GATE_MDP0(CLK_MDP_APB_DB, "mdp_apb_db", "mdp", 17),
GATE_MDP0(CLK_MDP_MDP_DLI_ASYNC0, "mdp_mdp_dli_async0", "mdp", 18),
GATE_MDP0(CLK_MDP_MDP_DLI_ASYNC1, "mdp_mdp_dli_async1", "mdp", 19),
GATE_MDP0(CLK_MDP_MDP_DLO_ASYNC0, "mdp_mdp_dlo_async0", "mdp", 20),
GATE_MDP0(CLK_MDP_MDP_DLO_ASYNC1, "mdp_mdp_dlo_async1", "mdp", 21),
GATE_MDP0(CLK_MDP_MDP_DLI_ASYNC2, "mdp_mdp_dli_async2", "mdp", 22),
GATE_MDP0(CLK_MDP_MDP_DLO_ASYNC2, "mdp_mdp_dlo_async2", "mdp", 23),
GATE_MDP0(CLK_MDP_MDP_DLO_ASYNC3, "mdp_mdp_dlo_async3", "mdp", 24),
GATE_MDP0(CLK_MDP_IMG_DL_ASYNC0, "mdp_img_dl_async0", "mdp", 25),
GATE_MDP0(CLK_MDP_MDP_RROT0, "mdp_mdp_rrot0", "mdp", 26),
GATE_MDP0(CLK_MDP_MDP_MERGE0, "mdp_mdp_merge0", "mdp", 27),
GATE_MDP0(CLK_MDP_MDP_C3D0, "mdp_mdp_c3d0", "mdp", 28),
GATE_MDP0(CLK_MDP_MDP_FG0, "mdp_mdp_fg0", "mdp", 29),
GATE_MDP0(CLK_MDP_MDP_CLA2, "mdp_mdp_cla2", "mdp", 30),
GATE_MDP0(CLK_MDP_MDP_DLO_ASYNC4, "mdp_mdp_dlo_async4", "mdp", 31),
/* MDP1 */
GATE_MDP1(CLK_MDP_VPP_RSZ0, "mdp_vpp_rsz0", "mdp", 0),
GATE_MDP1(CLK_MDP_VPP_RSZ1, "mdp_vpp_rsz1", "mdp", 1),
GATE_MDP1(CLK_MDP_MDP_DLO_ASYNC5, "mdp_mdp_dlo_async5", "mdp", 2),
GATE_MDP1(CLK_MDP_IMG0, "mdp_img0", "mdp", 3),
GATE_MDP1(CLK_MDP_F26M, "mdp_f26m", "clk26m", 27),
/* MDP2 */
GATE_MDP2(CLK_MDP_IMG_DL_RELAY0, "mdp_img_dl_relay0", "mdp", 0),
GATE_MDP2(CLK_MDP_IMG_DL_RELAY1, "mdp_img_dl_relay1", "mdp", 8),
};
static const struct mtk_clk_desc mdp_mcd = {
.clks = mdp_clks,
.num_clks = ARRAY_SIZE(mdp_clks),
.need_runtime_pm = true,
};
static const struct of_device_id of_match_clk_mt8196_mdpsys[] = {
{ .compatible = "mediatek,mt8196-mdpsys0", .data = &mdp_mcd },
{ .compatible = "mediatek,mt8196-mdpsys1", .data = &mdp1_mcd },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_mdpsys);
static struct platform_driver clk_mt8196_mdpsys_drv = {
.probe = mtk_clk_simple_probe,
.remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8196-mdpsys",
.of_match_table = of_match_clk_mt8196_mdpsys,
},
};
module_platform_driver(clk_mt8196_mdpsys_drv);
MODULE_DESCRIPTION("MediaTek MT8196 Multimedia Data Path clocks driver");
MODULE_LICENSE("GPL");

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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2025 MediaTek Inc.
* Guangjie Song <guangjie.song@mediatek.com>
* Copyright (c) 2025 Collabora Ltd.
* Laura Nao <laura.nao@collabora.com>
*/
#include <dt-bindings/clock/mediatek,mt8196-clock.h>
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-pll.h"
#define MFGPLL_CON0 0x008
#define MFGPLL_CON1 0x00c
#define MFGPLL_CON2 0x010
#define MFGPLL_CON3 0x014
#define MFGPLL_SC0_CON0 0x008
#define MFGPLL_SC0_CON1 0x00c
#define MFGPLL_SC0_CON2 0x010
#define MFGPLL_SC0_CON3 0x014
#define MFGPLL_SC1_CON0 0x008
#define MFGPLL_SC1_CON1 0x00c
#define MFGPLL_SC1_CON2 0x010
#define MFGPLL_SC1_CON3 0x014
#define MT8196_PLL_FMAX (3800UL * MHZ)
#define MT8196_PLL_FMIN (1500UL * MHZ)
#define MT8196_INTEGER_BITS 8
#define PLL(_id, _name, _reg, _en_reg, _en_mask, _pll_en_bit, \
_flags, _rst_bar_mask, \
_pd_reg, _pd_shift, _tuner_reg, \
_tuner_en_reg, _tuner_en_bit, \
_pcw_reg, _pcw_shift, _pcwbits) { \
.id = _id, \
.name = _name, \
.reg = _reg, \
.en_reg = _en_reg, \
.en_mask = _en_mask, \
.pll_en_bit = _pll_en_bit, \
.flags = _flags, \
.rst_bar_mask = _rst_bar_mask, \
.fmax = MT8196_PLL_FMAX, \
.fmin = MT8196_PLL_FMIN, \
.pd_reg = _pd_reg, \
.pd_shift = _pd_shift, \
.tuner_reg = _tuner_reg, \
.tuner_en_reg = _tuner_en_reg, \
.tuner_en_bit = _tuner_en_bit, \
.pcw_reg = _pcw_reg, \
.pcw_shift = _pcw_shift, \
.pcwbits = _pcwbits, \
.pcwibits = MT8196_INTEGER_BITS, \
}
static const struct mtk_pll_data mfg_ao_plls[] = {
PLL(CLK_MFG_AO_MFGPLL, "mfgpll", MFGPLL_CON0, MFGPLL_CON0, 0, 0, 0,
BIT(0), MFGPLL_CON1, 24, 0, 0, 0,
MFGPLL_CON1, 0, 22),
};
static const struct mtk_pll_data mfgsc0_ao_plls[] = {
PLL(CLK_MFGSC0_AO_MFGPLL_SC0, "mfgpll-sc0", MFGPLL_SC0_CON0,
MFGPLL_SC0_CON0, 0, 0, 0, BIT(0), MFGPLL_SC0_CON1, 24, 0, 0, 0,
MFGPLL_SC0_CON1, 0, 22),
};
static const struct mtk_pll_data mfgsc1_ao_plls[] = {
PLL(CLK_MFGSC1_AO_MFGPLL_SC1, "mfgpll-sc1", MFGPLL_SC1_CON0,
MFGPLL_SC1_CON0, 0, 0, 0, BIT(0), MFGPLL_SC1_CON1, 24, 0, 0, 0,
MFGPLL_SC1_CON1, 0, 22),
};
static const struct of_device_id of_match_clk_mt8196_mfg[] = {
{ .compatible = "mediatek,mt8196-mfgpll-pll-ctrl",
.data = &mfg_ao_plls },
{ .compatible = "mediatek,mt8196-mfgpll-sc0-pll-ctrl",
.data = &mfgsc0_ao_plls },
{ .compatible = "mediatek,mt8196-mfgpll-sc1-pll-ctrl",
.data = &mfgsc1_ao_plls },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_mfg);
static int clk_mt8196_mfg_probe(struct platform_device *pdev)
{
const struct mtk_pll_data *plls;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
const int num_plls = 1;
int r;
plls = of_device_get_match_data(&pdev->dev);
if (!plls)
return -EINVAL;
clk_data = mtk_alloc_clk_data(num_plls);
if (!clk_data)
return -ENOMEM;
r = mtk_clk_register_plls(node, plls, num_plls, clk_data);
if (r)
goto free_clk_data;
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
goto unregister_plls;
platform_set_drvdata(pdev, clk_data);
return r;
unregister_plls:
mtk_clk_unregister_plls(plls, num_plls, clk_data);
free_clk_data:
mtk_free_clk_data(clk_data);
return r;
}
static void clk_mt8196_mfg_remove(struct platform_device *pdev)
{
const struct mtk_pll_data *plls = of_device_get_match_data(&pdev->dev);
struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
struct device_node *node = pdev->dev.of_node;
of_clk_del_provider(node);
mtk_clk_unregister_plls(plls, 1, clk_data);
mtk_free_clk_data(clk_data);
}
static struct platform_driver clk_mt8196_mfg_drv = {
.probe = clk_mt8196_mfg_probe,
.remove = clk_mt8196_mfg_remove,
.driver = {
.name = "clk-mt8196-mfg",
.of_match_table = of_match_clk_mt8196_mfg,
},
};
module_platform_driver(clk_mt8196_mfg_drv);
MODULE_DESCRIPTION("MediaTek MT8196 GPU mfg clocks driver");
MODULE_LICENSE("GPL");

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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2025 MediaTek Inc.
* Guangjie Song <guangjie.song@mediatek.com>
* Copyright (c) 2025 Collabora Ltd.
* Laura Nao <laura.nao@collabora.com>
*/
#include <dt-bindings/clock/mediatek,mt8196-clock.h>
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
static const struct mtk_gate_regs ovl0_cg_regs = {
.set_ofs = 0x104,
.clr_ofs = 0x108,
.sta_ofs = 0x100,
};
static const struct mtk_gate_regs ovl0_hwv_regs = {
.set_ofs = 0x0060,
.clr_ofs = 0x0064,
.sta_ofs = 0x2c30,
};
static const struct mtk_gate_regs ovl1_cg_regs = {
.set_ofs = 0x114,
.clr_ofs = 0x118,
.sta_ofs = 0x110,
};
static const struct mtk_gate_regs ovl1_hwv_regs = {
.set_ofs = 0x0068,
.clr_ofs = 0x006c,
.sta_ofs = 0x2c34,
};
#define GATE_HWV_OVL0(_id, _name, _parent, _shift) { \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &ovl0_cg_regs, \
.hwv_regs = &ovl0_hwv_regs, \
.shift = _shift, \
.ops = &mtk_clk_gate_hwv_ops_setclr, \
.flags = CLK_OPS_PARENT_ENABLE, \
}
#define GATE_HWV_OVL1(_id, _name, _parent, _shift) { \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &ovl1_cg_regs, \
.hwv_regs = &ovl1_hwv_regs, \
.shift = _shift, \
.ops = &mtk_clk_gate_hwv_ops_setclr, \
.flags = CLK_OPS_PARENT_ENABLE, \
}
static const struct mtk_gate ovl_clks[] = {
/* OVL0 */
GATE_HWV_OVL0(CLK_OVLSYS_CONFIG, "ovlsys_config", "disp", 0),
GATE_HWV_OVL0(CLK_OVL_FAKE_ENG0, "ovl_fake_eng0", "disp", 1),
GATE_HWV_OVL0(CLK_OVL_FAKE_ENG1, "ovl_fake_eng1", "disp", 2),
GATE_HWV_OVL0(CLK_OVL_MUTEX0, "ovl_mutex0", "disp", 3),
GATE_HWV_OVL0(CLK_OVL_EXDMA0, "ovl_exdma0", "disp", 4),
GATE_HWV_OVL0(CLK_OVL_EXDMA1, "ovl_exdma1", "disp", 5),
GATE_HWV_OVL0(CLK_OVL_EXDMA2, "ovl_exdma2", "disp", 6),
GATE_HWV_OVL0(CLK_OVL_EXDMA3, "ovl_exdma3", "disp", 7),
GATE_HWV_OVL0(CLK_OVL_EXDMA4, "ovl_exdma4", "disp", 8),
GATE_HWV_OVL0(CLK_OVL_EXDMA5, "ovl_exdma5", "disp", 9),
GATE_HWV_OVL0(CLK_OVL_EXDMA6, "ovl_exdma6", "disp", 10),
GATE_HWV_OVL0(CLK_OVL_EXDMA7, "ovl_exdma7", "disp", 11),
GATE_HWV_OVL0(CLK_OVL_EXDMA8, "ovl_exdma8", "disp", 12),
GATE_HWV_OVL0(CLK_OVL_EXDMA9, "ovl_exdma9", "disp", 13),
GATE_HWV_OVL0(CLK_OVL_BLENDER0, "ovl_blender0", "disp", 14),
GATE_HWV_OVL0(CLK_OVL_BLENDER1, "ovl_blender1", "disp", 15),
GATE_HWV_OVL0(CLK_OVL_BLENDER2, "ovl_blender2", "disp", 16),
GATE_HWV_OVL0(CLK_OVL_BLENDER3, "ovl_blender3", "disp", 17),
GATE_HWV_OVL0(CLK_OVL_BLENDER4, "ovl_blender4", "disp", 18),
GATE_HWV_OVL0(CLK_OVL_BLENDER5, "ovl_blender5", "disp", 19),
GATE_HWV_OVL0(CLK_OVL_BLENDER6, "ovl_blender6", "disp", 20),
GATE_HWV_OVL0(CLK_OVL_BLENDER7, "ovl_blender7", "disp", 21),
GATE_HWV_OVL0(CLK_OVL_BLENDER8, "ovl_blender8", "disp", 22),
GATE_HWV_OVL0(CLK_OVL_BLENDER9, "ovl_blender9", "disp", 23),
GATE_HWV_OVL0(CLK_OVL_OUTPROC0, "ovl_outproc0", "disp", 24),
GATE_HWV_OVL0(CLK_OVL_OUTPROC1, "ovl_outproc1", "disp", 25),
GATE_HWV_OVL0(CLK_OVL_OUTPROC2, "ovl_outproc2", "disp", 26),
GATE_HWV_OVL0(CLK_OVL_OUTPROC3, "ovl_outproc3", "disp", 27),
GATE_HWV_OVL0(CLK_OVL_OUTPROC4, "ovl_outproc4", "disp", 28),
GATE_HWV_OVL0(CLK_OVL_OUTPROC5, "ovl_outproc5", "disp", 29),
GATE_HWV_OVL0(CLK_OVL_MDP_RSZ0, "ovl_mdp_rsz0", "disp", 30),
GATE_HWV_OVL0(CLK_OVL_MDP_RSZ1, "ovl_mdp_rsz1", "disp", 31),
/* OVL1 */
GATE_HWV_OVL1(CLK_OVL_DISP_WDMA0, "ovl_disp_wdma0", "disp", 0),
GATE_HWV_OVL1(CLK_OVL_DISP_WDMA1, "ovl_disp_wdma1", "disp", 1),
GATE_HWV_OVL1(CLK_OVL_UFBC_WDMA0, "ovl_ufbc_wdma0", "disp", 2),
GATE_HWV_OVL1(CLK_OVL_MDP_RDMA0, "ovl_mdp_rdma0", "disp", 3),
GATE_HWV_OVL1(CLK_OVL_MDP_RDMA1, "ovl_mdp_rdma1", "disp", 4),
GATE_HWV_OVL1(CLK_OVL_BWM0, "ovl_bwm0", "disp", 5),
GATE_HWV_OVL1(CLK_OVL_DLI0, "ovl_dli0", "disp", 6),
GATE_HWV_OVL1(CLK_OVL_DLI1, "ovl_dli1", "disp", 7),
GATE_HWV_OVL1(CLK_OVL_DLI2, "ovl_dli2", "disp", 8),
GATE_HWV_OVL1(CLK_OVL_DLI3, "ovl_dli3", "disp", 9),
GATE_HWV_OVL1(CLK_OVL_DLI4, "ovl_dli4", "disp", 10),
GATE_HWV_OVL1(CLK_OVL_DLI5, "ovl_dli5", "disp", 11),
GATE_HWV_OVL1(CLK_OVL_DLI6, "ovl_dli6", "disp", 12),
GATE_HWV_OVL1(CLK_OVL_DLI7, "ovl_dli7", "disp", 13),
GATE_HWV_OVL1(CLK_OVL_DLI8, "ovl_dli8", "disp", 14),
GATE_HWV_OVL1(CLK_OVL_DLO0, "ovl_dlo0", "disp", 15),
GATE_HWV_OVL1(CLK_OVL_DLO1, "ovl_dlo1", "disp", 16),
GATE_HWV_OVL1(CLK_OVL_DLO2, "ovl_dlo2", "disp", 17),
GATE_HWV_OVL1(CLK_OVL_DLO3, "ovl_dlo3", "disp", 18),
GATE_HWV_OVL1(CLK_OVL_DLO4, "ovl_dlo4", "disp", 19),
GATE_HWV_OVL1(CLK_OVL_DLO5, "ovl_dlo5", "disp", 20),
GATE_HWV_OVL1(CLK_OVL_DLO6, "ovl_dlo6", "disp", 21),
GATE_HWV_OVL1(CLK_OVL_DLO7, "ovl_dlo7", "disp", 22),
GATE_HWV_OVL1(CLK_OVL_DLO8, "ovl_dlo8", "disp", 23),
GATE_HWV_OVL1(CLK_OVL_DLO9, "ovl_dlo9", "disp", 24),
GATE_HWV_OVL1(CLK_OVL_DLO10, "ovl_dlo10", "disp", 25),
GATE_HWV_OVL1(CLK_OVL_DLO11, "ovl_dlo11", "disp", 26),
GATE_HWV_OVL1(CLK_OVL_DLO12, "ovl_dlo12", "disp", 27),
GATE_HWV_OVL1(CLK_OVLSYS_RELAY0, "ovlsys_relay0", "disp", 28),
GATE_HWV_OVL1(CLK_OVL_INLINEROT0, "ovl_inlinerot0", "disp", 29),
GATE_HWV_OVL1(CLK_OVL_SMI, "ovl_smi", "disp", 30),
};
static const struct mtk_clk_desc ovl_mcd = {
.clks = ovl_clks,
.num_clks = ARRAY_SIZE(ovl_clks),
};
static const struct platform_device_id clk_mt8196_ovl0_id_table[] = {
{ .name = "clk-mt8196-ovl0", .driver_data = (kernel_ulong_t)&ovl_mcd },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(platform, clk_mt8196_ovl0_id_table);
static struct platform_driver clk_mt8196_ovl0_drv = {
.probe = mtk_clk_pdev_probe,
.remove = mtk_clk_pdev_remove,
.driver = {
.name = "clk-mt8196-ovl0",
},
.id_table = clk_mt8196_ovl0_id_table,
};
module_platform_driver(clk_mt8196_ovl0_drv);
MODULE_DESCRIPTION("MediaTek MT8196 ovl0 clocks driver");
MODULE_LICENSE("GPL");

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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2025 MediaTek Inc.
* Guangjie Song <guangjie.song@mediatek.com>
* Copyright (c) 2025 Collabora Ltd.
* Laura Nao <laura.nao@collabora.com>
*/
#include <dt-bindings/clock/mediatek,mt8196-clock.h>
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
static const struct mtk_gate_regs ovl10_cg_regs = {
.set_ofs = 0x104,
.clr_ofs = 0x108,
.sta_ofs = 0x100,
};
static const struct mtk_gate_regs ovl10_hwv_regs = {
.set_ofs = 0x0050,
.clr_ofs = 0x0054,
.sta_ofs = 0x2c28,
};
static const struct mtk_gate_regs ovl11_cg_regs = {
.set_ofs = 0x114,
.clr_ofs = 0x118,
.sta_ofs = 0x110,
};
static const struct mtk_gate_regs ovl11_hwv_regs = {
.set_ofs = 0x0058,
.clr_ofs = 0x005c,
.sta_ofs = 0x2c2c,
};
#define GATE_HWV_OVL10(_id, _name, _parent, _shift) { \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &ovl10_cg_regs, \
.hwv_regs = &ovl10_hwv_regs, \
.shift = _shift, \
.ops = &mtk_clk_gate_hwv_ops_setclr, \
.flags = CLK_OPS_PARENT_ENABLE, \
}
#define GATE_HWV_OVL11(_id, _name, _parent, _shift) { \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &ovl11_cg_regs, \
.hwv_regs = &ovl11_hwv_regs, \
.shift = _shift, \
.ops = &mtk_clk_gate_hwv_ops_setclr, \
.flags = CLK_OPS_PARENT_ENABLE, \
}
static const struct mtk_gate ovl1_clks[] = {
/* OVL10 */
GATE_HWV_OVL10(CLK_OVL1_OVLSYS_CONFIG, "ovl1_ovlsys_config", "disp", 0),
GATE_HWV_OVL10(CLK_OVL1_OVL_FAKE_ENG0, "ovl1_ovl_fake_eng0", "disp", 1),
GATE_HWV_OVL10(CLK_OVL1_OVL_FAKE_ENG1, "ovl1_ovl_fake_eng1", "disp", 2),
GATE_HWV_OVL10(CLK_OVL1_OVL_MUTEX0, "ovl1_ovl_mutex0", "disp", 3),
GATE_HWV_OVL10(CLK_OVL1_OVL_EXDMA0, "ovl1_ovl_exdma0", "disp", 4),
GATE_HWV_OVL10(CLK_OVL1_OVL_EXDMA1, "ovl1_ovl_exdma1", "disp", 5),
GATE_HWV_OVL10(CLK_OVL1_OVL_EXDMA2, "ovl1_ovl_exdma2", "disp", 6),
GATE_HWV_OVL10(CLK_OVL1_OVL_EXDMA3, "ovl1_ovl_exdma3", "disp", 7),
GATE_HWV_OVL10(CLK_OVL1_OVL_EXDMA4, "ovl1_ovl_exdma4", "disp", 8),
GATE_HWV_OVL10(CLK_OVL1_OVL_EXDMA5, "ovl1_ovl_exdma5", "disp", 9),
GATE_HWV_OVL10(CLK_OVL1_OVL_EXDMA6, "ovl1_ovl_exdma6", "disp", 10),
GATE_HWV_OVL10(CLK_OVL1_OVL_EXDMA7, "ovl1_ovl_exdma7", "disp", 11),
GATE_HWV_OVL10(CLK_OVL1_OVL_EXDMA8, "ovl1_ovl_exdma8", "disp", 12),
GATE_HWV_OVL10(CLK_OVL1_OVL_EXDMA9, "ovl1_ovl_exdma9", "disp", 13),
GATE_HWV_OVL10(CLK_OVL1_OVL_BLENDER0, "ovl1_ovl_blender0", "disp", 14),
GATE_HWV_OVL10(CLK_OVL1_OVL_BLENDER1, "ovl1_ovl_blender1", "disp", 15),
GATE_HWV_OVL10(CLK_OVL1_OVL_BLENDER2, "ovl1_ovl_blender2", "disp", 16),
GATE_HWV_OVL10(CLK_OVL1_OVL_BLENDER3, "ovl1_ovl_blender3", "disp", 17),
GATE_HWV_OVL10(CLK_OVL1_OVL_BLENDER4, "ovl1_ovl_blender4", "disp", 18),
GATE_HWV_OVL10(CLK_OVL1_OVL_BLENDER5, "ovl1_ovl_blender5", "disp", 19),
GATE_HWV_OVL10(CLK_OVL1_OVL_BLENDER6, "ovl1_ovl_blender6", "disp", 20),
GATE_HWV_OVL10(CLK_OVL1_OVL_BLENDER7, "ovl1_ovl_blender7", "disp", 21),
GATE_HWV_OVL10(CLK_OVL1_OVL_BLENDER8, "ovl1_ovl_blender8", "disp", 22),
GATE_HWV_OVL10(CLK_OVL1_OVL_BLENDER9, "ovl1_ovl_blender9", "disp", 23),
GATE_HWV_OVL10(CLK_OVL1_OVL_OUTPROC0, "ovl1_ovl_outproc0", "disp", 24),
GATE_HWV_OVL10(CLK_OVL1_OVL_OUTPROC1, "ovl1_ovl_outproc1", "disp", 25),
GATE_HWV_OVL10(CLK_OVL1_OVL_OUTPROC2, "ovl1_ovl_outproc2", "disp", 26),
GATE_HWV_OVL10(CLK_OVL1_OVL_OUTPROC3, "ovl1_ovl_outproc3", "disp", 27),
GATE_HWV_OVL10(CLK_OVL1_OVL_OUTPROC4, "ovl1_ovl_outproc4", "disp", 28),
GATE_HWV_OVL10(CLK_OVL1_OVL_OUTPROC5, "ovl1_ovl_outproc5", "disp", 29),
GATE_HWV_OVL10(CLK_OVL1_OVL_MDP_RSZ0, "ovl1_ovl_mdp_rsz0", "disp", 30),
GATE_HWV_OVL10(CLK_OVL1_OVL_MDP_RSZ1, "ovl1_ovl_mdp_rsz1", "disp", 31),
/* OVL11 */
GATE_HWV_OVL11(CLK_OVL1_OVL_DISP_WDMA0, "ovl1_ovl_disp_wdma0", "disp", 0),
GATE_HWV_OVL11(CLK_OVL1_OVL_DISP_WDMA1, "ovl1_ovl_disp_wdma1", "disp", 1),
GATE_HWV_OVL11(CLK_OVL1_OVL_UFBC_WDMA0, "ovl1_ovl_ufbc_wdma0", "disp", 2),
GATE_HWV_OVL11(CLK_OVL1_OVL_MDP_RDMA0, "ovl1_ovl_mdp_rdma0", "disp", 3),
GATE_HWV_OVL11(CLK_OVL1_OVL_MDP_RDMA1, "ovl1_ovl_mdp_rdma1", "disp", 4),
GATE_HWV_OVL11(CLK_OVL1_OVL_BWM0, "ovl1_ovl_bwm0", "disp", 5),
GATE_HWV_OVL11(CLK_OVL1_DLI0, "ovl1_dli0", "disp", 6),
GATE_HWV_OVL11(CLK_OVL1_DLI1, "ovl1_dli1", "disp", 7),
GATE_HWV_OVL11(CLK_OVL1_DLI2, "ovl1_dli2", "disp", 8),
GATE_HWV_OVL11(CLK_OVL1_DLI3, "ovl1_dli3", "disp", 9),
GATE_HWV_OVL11(CLK_OVL1_DLI4, "ovl1_dli4", "disp", 10),
GATE_HWV_OVL11(CLK_OVL1_DLI5, "ovl1_dli5", "disp", 11),
GATE_HWV_OVL11(CLK_OVL1_DLI6, "ovl1_dli6", "disp", 12),
GATE_HWV_OVL11(CLK_OVL1_DLI7, "ovl1_dli7", "disp", 13),
GATE_HWV_OVL11(CLK_OVL1_DLI8, "ovl1_dli8", "disp", 14),
GATE_HWV_OVL11(CLK_OVL1_DLO0, "ovl1_dlo0", "disp", 15),
GATE_HWV_OVL11(CLK_OVL1_DLO1, "ovl1_dlo1", "disp", 16),
GATE_HWV_OVL11(CLK_OVL1_DLO2, "ovl1_dlo2", "disp", 17),
GATE_HWV_OVL11(CLK_OVL1_DLO3, "ovl1_dlo3", "disp", 18),
GATE_HWV_OVL11(CLK_OVL1_DLO4, "ovl1_dlo4", "disp", 19),
GATE_HWV_OVL11(CLK_OVL1_DLO5, "ovl1_dlo5", "disp", 20),
GATE_HWV_OVL11(CLK_OVL1_DLO6, "ovl1_dlo6", "disp", 21),
GATE_HWV_OVL11(CLK_OVL1_DLO7, "ovl1_dlo7", "disp", 22),
GATE_HWV_OVL11(CLK_OVL1_DLO8, "ovl1_dlo8", "disp", 23),
GATE_HWV_OVL11(CLK_OVL1_DLO9, "ovl1_dlo9", "disp", 24),
GATE_HWV_OVL11(CLK_OVL1_DLO10, "ovl1_dlo10", "disp", 25),
GATE_HWV_OVL11(CLK_OVL1_DLO11, "ovl1_dlo11", "disp", 26),
GATE_HWV_OVL11(CLK_OVL1_DLO12, "ovl1_dlo12", "disp", 27),
GATE_HWV_OVL11(CLK_OVL1_OVLSYS_RELAY0, "ovl1_ovlsys_relay0", "disp", 28),
GATE_HWV_OVL11(CLK_OVL1_OVL_INLINEROT0, "ovl1_ovl_inlinerot0", "disp", 29),
GATE_HWV_OVL11(CLK_OVL1_SMI, "ovl1_smi", "disp", 30),
};
static const struct mtk_clk_desc ovl1_mcd = {
.clks = ovl1_clks,
.num_clks = ARRAY_SIZE(ovl1_clks),
};
static const struct platform_device_id clk_mt8196_ovl1_id_table[] = {
{ .name = "clk-mt8196-ovl1", .driver_data = (kernel_ulong_t)&ovl1_mcd },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(platform, clk_mt8196_ovl1_id_table);
static struct platform_driver clk_mt8196_ovl1_drv = {
.probe = mtk_clk_pdev_probe,
.remove = mtk_clk_pdev_remove,
.driver = {
.name = "clk-mt8196-ovl1",
},
.id_table = clk_mt8196_ovl1_id_table,
};
module_platform_driver(clk_mt8196_ovl1_drv);
MODULE_DESCRIPTION("MediaTek MT8196 ovl1 clocks driver");
MODULE_LICENSE("GPL");

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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2025 MediaTek Inc.
* Guangjie Song <guangjie.song@mediatek.com>
* Copyright (c) 2025 Collabora Ltd.
* Laura Nao <laura.nao@collabora.com>
*/
#include <dt-bindings/clock/mediatek,mt8196-clock.h>
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
static const struct mtk_gate_regs peri_ao0_cg_regs = {
.set_ofs = 0x24,
.clr_ofs = 0x28,
.sta_ofs = 0x10,
};
static const struct mtk_gate_regs peri_ao1_cg_regs = {
.set_ofs = 0x2c,
.clr_ofs = 0x30,
.sta_ofs = 0x14,
};
static const struct mtk_gate_regs peri_ao1_hwv_regs = {
.set_ofs = 0x0008,
.clr_ofs = 0x000c,
.sta_ofs = 0x2c04,
};
static const struct mtk_gate_regs peri_ao2_cg_regs = {
.set_ofs = 0x34,
.clr_ofs = 0x38,
.sta_ofs = 0x18,
};
#define GATE_PERI_AO0(_id, _name, _parent, _shift) { \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &peri_ao0_cg_regs, \
.shift = _shift, \
.ops = &mtk_clk_gate_ops_setclr, \
}
#define GATE_PERI_AO1(_id, _name, _parent, _shift) { \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &peri_ao1_cg_regs, \
.shift = _shift, \
.ops = &mtk_clk_gate_ops_setclr, \
}
#define GATE_HWV_PERI_AO1(_id, _name, _parent, _shift) {\
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &peri_ao1_cg_regs, \
.hwv_regs = &peri_ao1_hwv_regs, \
.shift = _shift, \
.ops = &mtk_clk_gate_hwv_ops_setclr, \
}
#define GATE_PERI_AO2(_id, _name, _parent, _shift) { \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &peri_ao2_cg_regs, \
.shift = _shift, \
.ops = &mtk_clk_gate_ops_setclr, \
}
static const struct mtk_gate peri_ao_clks[] = {
/* PERI_AO0 */
GATE_PERI_AO0(CLK_PERI_AO_UART0_BCLK, "peri_ao_uart0_bclk", "uart", 0),
GATE_PERI_AO0(CLK_PERI_AO_UART1_BCLK, "peri_ao_uart1_bclk", "uart", 1),
GATE_PERI_AO0(CLK_PERI_AO_UART2_BCLK, "peri_ao_uart2_bclk", "uart", 2),
GATE_PERI_AO0(CLK_PERI_AO_UART3_BCLK, "peri_ao_uart3_bclk", "uart", 3),
GATE_PERI_AO0(CLK_PERI_AO_UART4_BCLK, "peri_ao_uart4_bclk", "uart", 4),
GATE_PERI_AO0(CLK_PERI_AO_UART5_BCLK, "peri_ao_uart5_bclk", "uart", 5),
GATE_PERI_AO0(CLK_PERI_AO_PWM_X16W_HCLK, "peri_ao_pwm_x16w", "p_axi", 12),
GATE_PERI_AO0(CLK_PERI_AO_PWM_X16W_BCLK, "peri_ao_pwm_x16w_bclk", "pwm", 13),
GATE_PERI_AO0(CLK_PERI_AO_PWM_PWM_BCLK0, "peri_ao_pwm_pwm_bclk0", "pwm", 14),
GATE_PERI_AO0(CLK_PERI_AO_PWM_PWM_BCLK1, "peri_ao_pwm_pwm_bclk1", "pwm", 15),
GATE_PERI_AO0(CLK_PERI_AO_PWM_PWM_BCLK2, "peri_ao_pwm_pwm_bclk2", "pwm", 16),
GATE_PERI_AO0(CLK_PERI_AO_PWM_PWM_BCLK3, "peri_ao_pwm_pwm_bclk3", "pwm", 17),
/* PERI_AO1 */
GATE_HWV_PERI_AO1(CLK_PERI_AO_SPI0_BCLK, "peri_ao_spi0_bclk", "spi0_b", 0),
GATE_HWV_PERI_AO1(CLK_PERI_AO_SPI1_BCLK, "peri_ao_spi1_bclk", "spi1_b", 2),
GATE_HWV_PERI_AO1(CLK_PERI_AO_SPI2_BCLK, "peri_ao_spi2_bclk", "spi2_b", 3),
GATE_HWV_PERI_AO1(CLK_PERI_AO_SPI3_BCLK, "peri_ao_spi3_bclk", "spi3_b", 4),
GATE_HWV_PERI_AO1(CLK_PERI_AO_SPI4_BCLK, "peri_ao_spi4_bclk", "spi4_b", 5),
GATE_HWV_PERI_AO1(CLK_PERI_AO_SPI5_BCLK, "peri_ao_spi5_bclk", "spi5_b", 6),
GATE_HWV_PERI_AO1(CLK_PERI_AO_SPI6_BCLK, "peri_ao_spi6_bclk", "spi6_b", 7),
GATE_HWV_PERI_AO1(CLK_PERI_AO_SPI7_BCLK, "peri_ao_spi7_bclk", "spi7_b", 8),
GATE_PERI_AO1(CLK_PERI_AO_FLASHIF_FLASH, "peri_ao_flashif_flash", "peri_ao_flashif_27m",
18),
GATE_PERI_AO1(CLK_PERI_AO_FLASHIF_27M, "peri_ao_flashif_27m", "sflash", 19),
GATE_PERI_AO1(CLK_PERI_AO_FLASHIF_DRAM, "peri_ao_flashif_dram", "p_axi", 20),
GATE_PERI_AO1(CLK_PERI_AO_FLASHIF_AXI, "peri_ao_flashif_axi", "peri_ao_flashif_dram", 21),
GATE_PERI_AO1(CLK_PERI_AO_FLASHIF_BCLK, "peri_ao_flashif_bclk", "p_axi", 22),
GATE_PERI_AO1(CLK_PERI_AO_AP_DMA_X32W_BCLK, "peri_ao_ap_dma_x32w_bclk", "p_axi", 26),
/* PERI_AO2 */
GATE_PERI_AO2(CLK_PERI_AO_MSDC1_MSDC_SRC, "peri_ao_msdc1_msdc_src", "msdc30_1", 1),
GATE_PERI_AO2(CLK_PERI_AO_MSDC1_HCLK, "peri_ao_msdc1", "peri_ao_msdc1_axi", 2),
GATE_PERI_AO2(CLK_PERI_AO_MSDC1_AXI, "peri_ao_msdc1_axi", "p_axi", 3),
GATE_PERI_AO2(CLK_PERI_AO_MSDC1_HCLK_WRAP, "peri_ao_msdc1_h_wrap", "peri_ao_msdc1", 4),
GATE_PERI_AO2(CLK_PERI_AO_MSDC2_MSDC_SRC, "peri_ao_msdc2_msdc_src", "msdc30_2", 10),
GATE_PERI_AO2(CLK_PERI_AO_MSDC2_HCLK, "peri_ao_msdc2", "peri_ao_msdc2_axi", 11),
GATE_PERI_AO2(CLK_PERI_AO_MSDC2_AXI, "peri_ao_msdc2_axi", "p_axi", 12),
GATE_PERI_AO2(CLK_PERI_AO_MSDC2_HCLK_WRAP, "peri_ao_msdc2_h_wrap", "peri_ao_msdc2", 13),
};
static const struct mtk_clk_desc peri_ao_mcd = {
.clks = peri_ao_clks,
.num_clks = ARRAY_SIZE(peri_ao_clks),
};
static const struct of_device_id of_match_clk_mt8196_peri_ao[] = {
{ .compatible = "mediatek,mt8196-pericfg-ao", .data = &peri_ao_mcd },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_peri_ao);
static struct platform_driver clk_mt8196_peri_ao_drv = {
.probe = mtk_clk_simple_probe,
.remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8196-peri-ao",
.of_match_table = of_match_clk_mt8196_peri_ao,
},
};
MODULE_DESCRIPTION("MediaTek MT8196 pericfg_ao clock controller driver");
module_platform_driver(clk_mt8196_peri_ao_drv);
MODULE_LICENSE("GPL");

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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2025 MediaTek Inc.
* Guangjie Song <guangjie.song@mediatek.com>
* Copyright (c) 2025 Collabora Ltd.
* Laura Nao <laura.nao@collabora.com>
*/
#include <dt-bindings/clock/mediatek,mt8196-clock.h>
#include <dt-bindings/reset/mediatek,mt8196-resets.h>
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
#include "reset.h"
#define MT8196_PEXTP_RST0_SET_OFFSET 0x8
static const struct mtk_gate_regs pext_cg_regs = {
.set_ofs = 0x18,
.clr_ofs = 0x1c,
.sta_ofs = 0x14,
};
#define GATE_PEXT(_id, _name, _parent, _shift) {\
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &pext_cg_regs, \
.shift = _shift, \
.ops = &mtk_clk_gate_ops_setclr,\
}
static const struct mtk_gate pext_clks[] = {
GATE_PEXT(CLK_PEXT_PEXTP_MAC_P0_TL, "pext_pm0_tl", "tl", 0),
GATE_PEXT(CLK_PEXT_PEXTP_MAC_P0_REF, "pext_pm0_ref", "clk26m", 1),
GATE_PEXT(CLK_PEXT_PEXTP_PHY_P0_MCU_BUS, "pext_pp0_mcu_bus", "clk26m", 6),
GATE_PEXT(CLK_PEXT_PEXTP_PHY_P0_PEXTP_REF, "pext_pp0_pextp_ref", "clk26m", 7),
GATE_PEXT(CLK_PEXT_PEXTP_MAC_P0_AXI_250, "pext_pm0_axi_250", "ufs_pexpt0_mem_sub", 12),
GATE_PEXT(CLK_PEXT_PEXTP_MAC_P0_AHB_APB, "pext_pm0_ahb_apb", "ufs_pextp0_axi", 13),
GATE_PEXT(CLK_PEXT_PEXTP_MAC_P0_PL_P, "pext_pm0_pl_p", "clk26m", 14),
GATE_PEXT(CLK_PEXT_PEXTP_VLP_AO_P0_LP, "pext_pextp_vlp_ao_p0_lp", "clk26m", 19),
};
static u16 pext_rst_ofs[] = { MT8196_PEXTP_RST0_SET_OFFSET };
static u16 pext_rst_idx_map[] = {
[MT8196_PEXTP0_RST0_PCIE0_MAC] = 0,
[MT8196_PEXTP0_RST0_PCIE0_PHY] = 1,
};
static const struct mtk_clk_rst_desc pext_rst_desc = {
.version = MTK_RST_SET_CLR,
.rst_bank_ofs = pext_rst_ofs,
.rst_bank_nr = ARRAY_SIZE(pext_rst_ofs),
.rst_idx_map = pext_rst_idx_map,
.rst_idx_map_nr = ARRAY_SIZE(pext_rst_idx_map),
};
static const struct mtk_clk_desc pext_mcd = {
.clks = pext_clks,
.num_clks = ARRAY_SIZE(pext_clks),
.rst_desc = &pext_rst_desc,
};
static const struct mtk_gate pext1_clks[] = {
GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P1_TL, "pext1_pm1_tl", "tl_p1", 0),
GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P1_REF, "pext1_pm1_ref", "clk26m", 1),
GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P2_TL, "pext1_pm2_tl", "tl_p2", 2),
GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P2_REF, "pext1_pm2_ref", "clk26m", 3),
GATE_PEXT(CLK_PEXT1_PEXTP_PHY_P1_MCU_BUS, "pext1_pp1_mcu_bus", "clk26m", 8),
GATE_PEXT(CLK_PEXT1_PEXTP_PHY_P1_PEXTP_REF, "pext1_pp1_pextp_ref", "clk26m", 9),
GATE_PEXT(CLK_PEXT1_PEXTP_PHY_P2_MCU_BUS, "pext1_pp2_mcu_bus", "clk26m", 10),
GATE_PEXT(CLK_PEXT1_PEXTP_PHY_P2_PEXTP_REF, "pext1_pp2_pextp_ref", "clk26m", 11),
GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P1_AXI_250, "pext1_pm1_axi_250",
"pextp1_usb_axi", 16),
GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P1_AHB_APB, "pext1_pm1_ahb_apb",
"pextp1_usb_mem_sub", 17),
GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P1_PL_P, "pext1_pm1_pl_p", "clk26m", 18),
GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P2_AXI_250, "pext1_pm2_axi_250",
"pextp1_usb_axi", 19),
GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P2_AHB_APB, "pext1_pm2_ahb_apb",
"pextp1_usb_mem_sub", 20),
GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P2_PL_P, "pext1_pm2_pl_p", "clk26m", 21),
GATE_PEXT(CLK_PEXT1_PEXTP_VLP_AO_P1_LP, "pext1_pextp_vlp_ao_p1_lp", "clk26m", 26),
GATE_PEXT(CLK_PEXT1_PEXTP_VLP_AO_P2_LP, "pext1_pextp_vlp_ao_p2_lp", "clk26m", 27),
};
static u16 pext1_rst_idx_map[] = {
[MT8196_PEXTP1_RST0_PCIE1_MAC] = 0,
[MT8196_PEXTP1_RST0_PCIE1_PHY] = 1,
[MT8196_PEXTP1_RST0_PCIE2_MAC] = 8,
[MT8196_PEXTP1_RST0_PCIE2_PHY] = 9,
};
static const struct mtk_clk_rst_desc pext1_rst_desc = {
.version = MTK_RST_SET_CLR,
.rst_bank_ofs = pext_rst_ofs,
.rst_bank_nr = ARRAY_SIZE(pext_rst_ofs),
.rst_idx_map = pext1_rst_idx_map,
.rst_idx_map_nr = ARRAY_SIZE(pext1_rst_idx_map),
};
static const struct mtk_clk_desc pext1_mcd = {
.clks = pext1_clks,
.num_clks = ARRAY_SIZE(pext1_clks),
.rst_desc = &pext1_rst_desc,
};
static const struct of_device_id of_match_clk_mt8196_pextp[] = {
{ .compatible = "mediatek,mt8196-pextp0cfg-ao", .data = &pext_mcd },
{ .compatible = "mediatek,mt8196-pextp1cfg-ao", .data = &pext1_mcd },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_pextp);
static struct platform_driver clk_mt8196_pextp_drv = {
.probe = mtk_clk_simple_probe,
.remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8196-pextp",
.of_match_table = of_match_clk_mt8196_pextp,
},
};
module_platform_driver(clk_mt8196_pextp_drv);
MODULE_DESCRIPTION("MediaTek MT8196 PCIe transmit phy clocks driver");
MODULE_LICENSE("GPL");

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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2025 MediaTek Inc.
* Guangjie Song <guangjie.song@mediatek.com>
* Copyright (c) 2025 Collabora Ltd.
* Laura Nao <laura.nao@collabora.com>
*/
#include <dt-bindings/clock/mediatek,mt8196-clock.h>
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-mux.h"
/* MUX SEL REG */
#define CLK_CFG_UPDATE 0x0004
#define CLK_CFG_UPDATE1 0x0008
#define CLK_CFG_UPDATE2 0x000c
#define CLK_CFG_0 0x0010
#define CLK_CFG_0_SET 0x0014
#define CLK_CFG_0_CLR 0x0018
#define CLK_CFG_1 0x0020
#define CLK_CFG_1_SET 0x0024
#define CLK_CFG_1_CLR 0x0028
#define CLK_CFG_2 0x0030
#define CLK_CFG_2_SET 0x0034
#define CLK_CFG_2_CLR 0x0038
#define CLK_CFG_3 0x0040
#define CLK_CFG_3_SET 0x0044
#define CLK_CFG_3_CLR 0x0048
#define CLK_CFG_4 0x0050
#define CLK_CFG_4_SET 0x0054
#define CLK_CFG_4_CLR 0x0058
#define CLK_CFG_5 0x0060
#define CLK_CFG_5_SET 0x0064
#define CLK_CFG_5_CLR 0x0068
#define CLK_CFG_6 0x0070
#define CLK_CFG_6_SET 0x0074
#define CLK_CFG_6_CLR 0x0078
#define CLK_CFG_7 0x0080
#define CLK_CFG_7_SET 0x0084
#define CLK_CFG_7_CLR 0x0088
#define CLK_CFG_8 0x0090
#define CLK_CFG_8_SET 0x0094
#define CLK_CFG_8_CLR 0x0098
#define CLK_CFG_9 0x00a0
#define CLK_CFG_9_SET 0x00a4
#define CLK_CFG_9_CLR 0x00a8
#define CLK_CFG_10 0x00b0
#define CLK_CFG_10_SET 0x00b4
#define CLK_CFG_10_CLR 0x00b8
#define CLK_CFG_11 0x00c0
#define CLK_CFG_11_SET 0x00c4
#define CLK_CFG_11_CLR 0x00c8
#define CLK_CFG_12 0x00d0
#define CLK_CFG_12_SET 0x00d4
#define CLK_CFG_12_CLR 0x00d8
#define CLK_CFG_13 0x00e0
#define CLK_CFG_13_SET 0x00e4
#define CLK_CFG_13_CLR 0x00e8
#define CLK_CFG_14 0x00f0
#define CLK_CFG_14_SET 0x00f4
#define CLK_CFG_14_CLR 0x00f8
#define CLK_CFG_15 0x0100
#define CLK_CFG_15_SET 0x0104
#define CLK_CFG_15_CLR 0x0108
#define CLK_CFG_16 0x0110
#define CLK_CFG_16_SET 0x0114
#define CLK_CFG_16_CLR 0x0118
#define CLK_CFG_17 0x0120
#define CLK_CFG_17_SET 0x0124
#define CLK_CFG_17_CLR 0x0128
#define CLK_CFG_18 0x0130
#define CLK_CFG_18_SET 0x0134
#define CLK_CFG_18_CLR 0x0138
#define CLK_CFG_19 0x0140
#define CLK_CFG_19_SET 0x0144
#define CLK_CFG_19_CLR 0x0148
#define CLK_AUDDIV_0 0x020c
#define CLK_FENC_STATUS_MON_0 0x0270
#define CLK_FENC_STATUS_MON_1 0x0274
#define CLK_FENC_STATUS_MON_2 0x0278
/* MUX SHIFT */
#define TOP_MUX_AXI_SHIFT 0
#define TOP_MUX_MEM_SUB_SHIFT 1
#define TOP_MUX_IO_NOC_SHIFT 2
#define TOP_MUX_PERI_AXI_SHIFT 3
#define TOP_MUX_UFS_PEXTP0_AXI_SHIFT 4
#define TOP_MUX_PEXTP1_USB_AXI_SHIFT 5
#define TOP_MUX_PERI_FMEM_SUB_SHIFT 6
#define TOP_MUX_UFS_PEXPT0_MEM_SUB_SHIFT 7
#define TOP_MUX_PEXTP1_USB_MEM_SUB_SHIFT 8
#define TOP_MUX_PERI_NOC_SHIFT 9
#define TOP_MUX_EMI_N_SHIFT 10
#define TOP_MUX_EMI_S_SHIFT 11
#define TOP_MUX_AP2CONN_HOST_SHIFT 14
#define TOP_MUX_ATB_SHIFT 15
#define TOP_MUX_CIRQ_SHIFT 16
#define TOP_MUX_PBUS_156M_SHIFT 17
#define TOP_MUX_EFUSE_SHIFT 20
#define TOP_MUX_MCU_L3GIC_SHIFT 21
#define TOP_MUX_MCU_INFRA_SHIFT 22
#define TOP_MUX_DSP_SHIFT 23
#define TOP_MUX_MFG_REF_SHIFT 24
#define TOP_MUX_MFG_EB_SHIFT 26
#define TOP_MUX_UART_SHIFT 27
#define TOP_MUX_SPI0_BCLK_SHIFT 28
#define TOP_MUX_SPI1_BCLK_SHIFT 29
#define TOP_MUX_SPI2_BCLK_SHIFT 30
#define TOP_MUX_SPI3_BCLK_SHIFT 0
#define TOP_MUX_SPI4_BCLK_SHIFT 1
#define TOP_MUX_SPI5_BCLK_SHIFT 2
#define TOP_MUX_SPI6_BCLK_SHIFT 3
#define TOP_MUX_SPI7_BCLK_SHIFT 4
#define TOP_MUX_MSDC30_1_SHIFT 7
#define TOP_MUX_MSDC30_2_SHIFT 8
#define TOP_MUX_DISP_PWM_SHIFT 9
#define TOP_MUX_USB_TOP_1P_SHIFT 10
#define TOP_MUX_SSUSB_XHCI_1P_SHIFT 11
#define TOP_MUX_SSUSB_FMCNT_P1_SHIFT 12
#define TOP_MUX_I2C_PERI_SHIFT 13
#define TOP_MUX_I2C_EAST_SHIFT 14
#define TOP_MUX_I2C_WEST_SHIFT 15
#define TOP_MUX_I2C_NORTH_SHIFT 16
#define TOP_MUX_AES_UFSFDE_SHIFT 17
#define TOP_MUX_UFS_SHIFT 18
#define TOP_MUX_AUD_1_SHIFT 21
#define TOP_MUX_AUD_2_SHIFT 22
#define TOP_MUX_ADSP_SHIFT 23
#define TOP_MUX_ADSP_UARTHUB_B_SHIFT 24
#define TOP_MUX_DPMAIF_MAIN_SHIFT 25
#define TOP_MUX_PWM_SHIFT 26
#define TOP_MUX_MCUPM_SHIFT 27
#define TOP_MUX_SFLASH_SHIFT 28
#define TOP_MUX_IPSEAST_SHIFT 29
#define TOP_MUX_TL_SHIFT 0
#define TOP_MUX_TL_P1_SHIFT 1
#define TOP_MUX_TL_P2_SHIFT 2
#define TOP_MUX_EMI_INTERFACE_546_SHIFT 3
#define TOP_MUX_SDF_SHIFT 4
#define TOP_MUX_UARTHUB_BCLK_SHIFT 5
#define TOP_MUX_DPSW_CMP_26M_SHIFT 6
#define TOP_MUX_SMAPCK_SHIFT 7
#define TOP_MUX_SSR_PKA_SHIFT 8
#define TOP_MUX_SSR_DMA_SHIFT 9
#define TOP_MUX_SSR_KDF_SHIFT 10
#define TOP_MUX_SSR_RNG_SHIFT 11
#define TOP_MUX_SPU0_SHIFT 12
#define TOP_MUX_SPU1_SHIFT 13
#define TOP_MUX_DXCC_SHIFT 14
/* CKSTA REG */
#define CKSTA_REG 0x01c8
#define CKSTA_REG1 0x01cc
#define CKSTA_REG2 0x01d0
/* DIVIDER REG */
#define CLK_AUDDIV_2 0x0214
#define CLK_AUDDIV_3 0x0220
#define CLK_AUDDIV_4 0x0224
#define CLK_AUDDIV_5 0x0228
/* HW Voter REG */
#define HWV_CG_0_SET 0x0000
#define HWV_CG_0_CLR 0x0004
#define HWV_CG_0_DONE 0x2c00
#define HWV_CG_1_SET 0x0008
#define HWV_CG_1_CLR 0x000c
#define HWV_CG_1_DONE 0x2c04
#define HWV_CG_2_SET 0x0010
#define HWV_CG_2_CLR 0x0014
#define HWV_CG_2_DONE 0x2c08
#define HWV_CG_3_SET 0x0018
#define HWV_CG_3_CLR 0x001c
#define HWV_CG_3_DONE 0x2c0c
#define HWV_CG_4_SET 0x0020
#define HWV_CG_4_CLR 0x0024
#define HWV_CG_4_DONE 0x2c10
#define HWV_CG_5_SET 0x0028
#define HWV_CG_5_CLR 0x002c
#define HWV_CG_5_DONE 0x2c14
#define HWV_CG_6_SET 0x0030
#define HWV_CG_6_CLR 0x0034
#define HWV_CG_6_DONE 0x2c18
#define HWV_CG_7_SET 0x0038
#define HWV_CG_7_CLR 0x003c
#define HWV_CG_7_DONE 0x2c1c
#define HWV_CG_8_SET 0x0040
#define HWV_CG_8_CLR 0x0044
#define HWV_CG_8_DONE 0x2c20
static const struct mtk_fixed_factor top_divs[] = {
FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3),
FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4),
FACTOR(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2", "mainpll", 1, 8),
FACTOR(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4", "mainpll", 1, 16),
FACTOR(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8", "mainpll", 1, 32),
FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5),
FACTOR(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll", 1, 10),
FACTOR(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll", 1, 20),
FACTOR(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8", "mainpll", 1, 40),
FACTOR(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6),
FACTOR(CLK_TOP_MAINPLL_D6_D2, "mainpll_d6_d2", "mainpll", 1, 12),
FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7),
FACTOR(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll", 1, 14),
FACTOR(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll", 1, 28),
FACTOR(CLK_TOP_MAINPLL_D7_D8, "mainpll_d7_d8", "mainpll", 1, 56),
FACTOR(CLK_TOP_MAINPLL_D9, "mainpll_d9", "mainpll", 1, 9),
FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4),
FACTOR(CLK_TOP_UNIVPLL_D4_D2, "univpll_d4_d2", "univpll", 1, 8),
FACTOR(CLK_TOP_UNIVPLL_D4_D4, "univpll_d4_d4", "univpll", 1, 16),
FACTOR(CLK_TOP_UNIVPLL_D4_D8, "univpll_d4_d8", "univpll", 1, 32),
FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll", 1, 10),
FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll", 1, 20),
FACTOR(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6),
FACTOR(CLK_TOP_UNIVPLL_D6_D2, "univpll_d6_d2", "univpll", 1, 12),
FACTOR(CLK_TOP_UNIVPLL_D6_D4, "univpll_d6_d4", "univpll", 1, 24),
FACTOR(CLK_TOP_UNIVPLL_D6_D8, "univpll_d6_d8", "univpll", 1, 48),
FACTOR(CLK_TOP_UNIVPLL_D6_D16, "univpll_d6_d16", "univpll", 1, 96),
FACTOR(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univpll", 1, 13),
FACTOR(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll", 1, 52),
FACTOR(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll", 1, 104),
FACTOR(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll", 1, 208),
FACTOR(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll", 1, 416),
FACTOR(CLK_TOP_UNIVPLL_192M_D10, "univpll_192m_d10", "univpll", 1, 130),
FACTOR(CLK_TOP_TVDPLL1_D2, "tvdpll1_d2", "tvdpll1", 1, 2),
FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
FACTOR(CLK_TOP_OSC_D2, "osc_d2", "ulposc", 1, 2),
FACTOR(CLK_TOP_OSC_D3, "osc_d3", "ulposc", 1, 3),
FACTOR(CLK_TOP_OSC_D4, "osc_d4", "ulposc", 1, 4),
FACTOR(CLK_TOP_OSC_D5, "osc_d5", "ulposc", 1, 5),
FACTOR(CLK_TOP_OSC_D7, "osc_d7", "ulposc", 1, 7),
FACTOR(CLK_TOP_OSC_D8, "osc_d8", "ulposc", 1, 8),
FACTOR(CLK_TOP_OSC_D10, "osc_d10", "ulposc", 1, 10),
FACTOR(CLK_TOP_OSC_D14, "osc_d14", "ulposc", 1, 14),
FACTOR(CLK_TOP_OSC_D20, "osc_d20", "ulposc", 1, 20),
FACTOR(CLK_TOP_OSC_D32, "osc_d32", "ulposc", 1, 32),
FACTOR(CLK_TOP_OSC_D40, "osc_d40", "ulposc", 1, 40),
};
static const char * const axi_parents[] = {
"clk26m",
"osc_d20",
"osc_d8",
"osc_d4",
"mainpll_d4_d4",
"mainpll_d7_d2"
};
static const char * const mem_sub_parents[] = {
"clk26m",
"osc_d20",
"osc_d4",
"univpll_d4_d4",
"osc_d3",
"mainpll_d5_d2",
"mainpll_d4_d2",
"mainpll_d6",
"mainpll_d5",
"univpll_d5",
"mainpll_d4",
"mainpll_d3"
};
static const char * const io_noc_parents[] = {
"clk26m",
"osc_d20",
"osc_d8",
"osc_d4",
"mainpll_d6_d2",
"mainpll_d9"
};
static const char * const shared_axi_parents[] = {
"clk26m",
"mainpll_d7_d8",
"mainpll_d5_d8",
"osc_d8",
"mainpll_d7_d4",
"mainpll_d5_d4",
"mainpll_d4_d4",
"mainpll_d7_d2"
};
static const char * const shared_sub_parents[] = {
"clk26m",
"mainpll_d5_d8",
"mainpll_d5_d4",
"osc_d4",
"univpll_d4_d4",
"mainpll_d5_d2",
"mainpll_d4_d2",
"mainpll_d6",
"mainpll_d5",
"univpll_d5",
"mainpll_d4"
};
static const char * const p_noc_parents[] = {
"clk26m",
"mainpll_d5_d8",
"mainpll_d5_d4",
"osc_d4",
"univpll_d4_d4",
"mainpll_d5_d2",
"mainpll_d4_d2",
"mainpll_d6",
"mainpll_d5",
"univpll_d5",
"mainpll_d4",
"mainpll_d3"
};
static const char * const emi_parents[] = {
"clk26m",
"osc_d4",
"mainpll_d5_d8",
"mainpll_d5_d4",
"mainpll_d4_d4",
"emipll1_ck"
};
static const char * const ap2conn_host_parents[] = {
"clk26m",
"mainpll_d7_d4"
};
static const char * const atb_parents[] = {
"clk26m",
"mainpll_d5_d2",
"mainpll_d4_d2",
"mainpll_d6"
};
static const char * const cirq_parents[] = {
"clk26m",
"osc_d20",
"mainpll_d7_d4"
};
static const char * const pbus_156m_parents[] = {
"clk26m",
"mainpll_d7_d2",
"osc_d2",
"mainpll_d7"
};
static const char * const efuse_parents[] = {
"clk26m",
"osc_d20"
};
static const char * const mcu_l3gic_parents[] = {
"clk26m",
"osc_d8",
"mainpll_d4_d4",
"mainpll_d7_d2"
};
static const char * const mcu_infra_parents[] = {
"clk26m",
"osc_d20",
"mainpll_d7_d2",
"mainpll_d5_d2",
"mainpll_d4_d2",
"mainpll_d9",
"mainpll_d6"
};
static const char * const dsp_parents[] = {
"clk26m",
"osc_d5",
"osc_d4",
"osc_d3",
"univpll_d6_d2",
"osc_d2",
"univpll_d5",
"osc"
};
static const char * const mfg_ref_parents[] = {
"clk26m",
"mainpll_d7_d2"
};
static const char * const mfg_eb_parents[] = {
"clk26m",
"mainpll_d7_d2",
"mainpll_d6_d2",
"mainpll_d5_d2"
};
static const char * const uart_parents[] = {
"clk26m",
"univpll_d6_d8",
"univpll_d6_d4",
"univpll_d6_d2"
};
static const char * const spi_b_parents[] = {
"clk26m",
"univpll_d6_d4",
"univpll_d5_d4",
"mainpll_d4_d4",
"univpll_d4_d4",
"mainpll_d6_d2",
"univpll_192m",
"univpll_d6_d2"
};
static const char * const msdc30_parents[] = {
"clk26m",
"univpll_d6_d4",
"mainpll_d6_d2",
"univpll_d6_d2",
"msdcpll_d2"
};
static const char * const disp_pwm_parents[] = {
"clk26m",
"osc_d32",
"osc_d8",
"univpll_d6_d4",
"univpll_d5_d4",
"osc_d4",
"mainpll_d4_d4"
};
static const char * const usb_1p_parents[] = {
"clk26m",
"univpll_d5_d4"
};
static const char * const usb_fmcnt_p1_parents[] = {
"clk26m",
"univpll_192m_d4"
};
static const char * const i2c_parents[] = {
"clk26m",
"mainpll_d4_d8",
"univpll_d5_d4",
"mainpll_d4_d4",
"univpll_d5_d2"
};
static const char * const aes_ufsfde_parents[] = {
"clk26m",
"mainpll_d4_d4",
"univpll_d6_d2",
"mainpll_d4_d2",
"univpll_d6",
"mainpll_d4"
};
static const char * const ufs_parents[] = {
"clk26m",
"mainpll_d4_d4",
"univpll_d6_d2",
"mainpll_d4_d2",
"univpll_d6",
"mainpll_d5",
"univpll_d5"
};
static const char * const aud_1_parents[] = {
"clk26m",
"vlp_apll1"
};
static const char * const aud_2_parents[] = {
"clk26m",
"vlp_apll2"
};
static const char * const adsp_parents[] = {
"clk26m",
"adsppll"
};
static const char * const adsp_uarthub_b_parents[] = {
"clk26m",
"univpll_d6_d4",
"univpll_d6_d2"
};
static const char * const dpmaif_main_parents[] = {
"clk26m",
"univpll_d4_d4",
"univpll_d5_d2",
"mainpll_d4_d2",
"univpll_d4_d2",
"mainpll_d6",
"univpll_d6",
"mainpll_d5",
"univpll_d5"
};
static const char * const pwm_parents[] = {
"clk26m",
"mainpll_d7_d4",
"univpll_d4_d8"
};
static const char * const mcupm_parents[] = {
"clk26m",
"mainpll_d7_d2",
"mainpll_d6_d2",
"univpll_d6_d2",
"mainpll_d5_d2"
};
static const char * const ipseast_parents[] = {
"clk26m",
"mainpll_d6",
"mainpll_d5",
"mainpll_d4",
"mainpll_d3"
};
static const char * const tl_parents[] = {
"clk26m",
"mainpll_d7_d4",
"mainpll_d4_d4",
"mainpll_d5_d2"
};
static const char * const md_emi_parents[] = {
"clk26m",
"mainpll_d4"
};
static const char * const sdf_parents[] = {
"clk26m",
"mainpll_d5_d2",
"mainpll_d4_d2",
"mainpll_d6",
"mainpll_d4",
"univpll_d4"
};
static const char * const uarthub_b_parents[] = {
"clk26m",
"univpll_d6_d4",
"univpll_d6_d2"
};
static const char * const dpsw_cmp_26m_parents[] = {
"clk26m",
"osc_d20"
};
static const char * const smapparents[] = {
"clk26m",
"mainpll_d4_d8"
};
static const char * const ssr_parents[] = {
"clk26m",
"mainpll_d4_d4",
"mainpll_d4_d2",
"mainpll_d7",
"mainpll_d6",
"mainpll_d5"
};
static const char * const ssr_kdf_parents[] = {
"clk26m",
"mainpll_d4_d4",
"mainpll_d4_d2",
"mainpll_d7"
};
static const char * const ssr_rng_parents[] = {
"clk26m",
"mainpll_d4_d4",
"mainpll_d5_d2",
"mainpll_d4_d2"
};
static const char * const spu_parents[] = {
"clk26m",
"mainpll_d4_d4",
"mainpll_d4_d2",
"mainpll_d7",
"mainpll_d6",
"mainpll_d5"
};
static const char * const dxcc_parents[] = {
"clk26m",
"mainpll_d4_d8",
"mainpll_d4_d4",
"mainpll_d4_d2"
};
static const char * const apll_m_parents[] = {
"aud_1",
"aud_2"
};
static const char * const sflash_parents[] = {
"clk26m",
"mainpll_d7_d8",
"univpll_d6_d8"
};
static const struct mtk_mux top_muxes[] = {
/* CLK_CFG_0 */
MUX_CLR_SET_UPD(CLK_TOP_AXI, "axi",
axi_parents, CLK_CFG_0, CLK_CFG_0_SET,
CLK_CFG_0_CLR, 0, 3,
CLK_CFG_UPDATE, TOP_MUX_AXI_SHIFT),
MUX_CLR_SET_UPD(CLK_TOP_MEM_SUB, "mem_sub",
mem_sub_parents, CLK_CFG_0, CLK_CFG_0_SET,
CLK_CFG_0_CLR, 8, 4,
CLK_CFG_UPDATE, TOP_MUX_MEM_SUB_SHIFT),
MUX_CLR_SET_UPD(CLK_TOP_IO_NOC, "io_noc",
io_noc_parents, CLK_CFG_0, CLK_CFG_0_SET,
CLK_CFG_0_CLR, 16, 3,
CLK_CFG_UPDATE, TOP_MUX_IO_NOC_SHIFT),
MUX_CLR_SET_UPD(CLK_TOP_P_AXI, "p_axi",
shared_axi_parents, CLK_CFG_0, CLK_CFG_0_SET,
CLK_CFG_0_CLR, 24, 3,
CLK_CFG_UPDATE, TOP_MUX_PERI_AXI_SHIFT),
/* CLK_CFG_1 */
MUX_CLR_SET_UPD(CLK_TOP_UFS_PEXTP0_AXI, "ufs_pextp0_axi",
shared_axi_parents, CLK_CFG_1, CLK_CFG_1_SET,
CLK_CFG_1_CLR, 0, 3,
CLK_CFG_UPDATE, TOP_MUX_UFS_PEXTP0_AXI_SHIFT),
MUX_CLR_SET_UPD(CLK_TOP_PEXTP1_USB_AXI, "pextp1_usb_axi",
shared_axi_parents, CLK_CFG_1, CLK_CFG_1_SET,
CLK_CFG_1_CLR, 8, 3,
CLK_CFG_UPDATE, TOP_MUX_PEXTP1_USB_AXI_SHIFT),
MUX_CLR_SET_UPD(CLK_TOP_P_FMEM_SUB, "p_fmem_sub",
shared_sub_parents, CLK_CFG_1, CLK_CFG_1_SET,
CLK_CFG_1_CLR, 16, 4,
CLK_CFG_UPDATE, TOP_MUX_PERI_FMEM_SUB_SHIFT),
MUX_CLR_SET_UPD(CLK_TOP_PEXPT0_MEM_SUB, "ufs_pexpt0_mem_sub",
shared_sub_parents, CLK_CFG_1, CLK_CFG_1_SET,
CLK_CFG_1_CLR, 24, 4,
CLK_CFG_UPDATE, TOP_MUX_UFS_PEXPT0_MEM_SUB_SHIFT),
/* CLK_CFG_2 */
MUX_CLR_SET_UPD(CLK_TOP_PEXTP1_USB_MEM_SUB, "pextp1_usb_mem_sub",
shared_sub_parents, CLK_CFG_2, CLK_CFG_2_SET,
CLK_CFG_2_CLR, 0, 4,
CLK_CFG_UPDATE, TOP_MUX_PEXTP1_USB_MEM_SUB_SHIFT),
MUX_CLR_SET_UPD(CLK_TOP_P_NOC, "p_noc",
p_noc_parents, CLK_CFG_2, CLK_CFG_2_SET,
CLK_CFG_2_CLR, 8, 4,
CLK_CFG_UPDATE, TOP_MUX_PERI_NOC_SHIFT),
MUX_CLR_SET_UPD(CLK_TOP_EMI_N, "emi_n",
emi_parents, CLK_CFG_2, CLK_CFG_2_SET,
CLK_CFG_2_CLR, 16, 3,
CLK_CFG_UPDATE, TOP_MUX_EMI_N_SHIFT),
MUX_CLR_SET_UPD(CLK_TOP_EMI_S, "emi_s",
emi_parents, CLK_CFG_2, CLK_CFG_2_SET,
CLK_CFG_2_CLR, 24, 3,
CLK_CFG_UPDATE, TOP_MUX_EMI_S_SHIFT),
/* CLK_CFG_3 */
MUX_CLR_SET_UPD(CLK_TOP_AP2CONN_HOST, "ap2conn_host",
ap2conn_host_parents, CLK_CFG_3, CLK_CFG_3_SET,
CLK_CFG_3_CLR, 16, 1,
CLK_CFG_UPDATE, TOP_MUX_AP2CONN_HOST_SHIFT),
MUX_CLR_SET_UPD(CLK_TOP_ATB, "atb",
atb_parents, CLK_CFG_3, CLK_CFG_3_SET,
CLK_CFG_3_CLR, 24, 2,
CLK_CFG_UPDATE, TOP_MUX_ATB_SHIFT),
/* CLK_CFG_4 */
MUX_CLR_SET_UPD(CLK_TOP_CIRQ, "cirq",
cirq_parents, CLK_CFG_4, CLK_CFG_4_SET,
CLK_CFG_4_CLR, 0, 2,
CLK_CFG_UPDATE, TOP_MUX_CIRQ_SHIFT),
MUX_CLR_SET_UPD(CLK_TOP_PBUS_156M, "pbus_156m",
pbus_156m_parents, CLK_CFG_4, CLK_CFG_4_SET,
CLK_CFG_4_CLR, 8, 2,
CLK_CFG_UPDATE, TOP_MUX_PBUS_156M_SHIFT),
/* CLK_CFG_5 */
MUX_CLR_SET_UPD(CLK_TOP_EFUSE, "efuse",
efuse_parents, CLK_CFG_5, CLK_CFG_5_SET,
CLK_CFG_5_CLR, 0, 1,
CLK_CFG_UPDATE, TOP_MUX_EFUSE_SHIFT),
MUX_CLR_SET_UPD(CLK_TOP_MCL3GIC, "mcu_l3gic",
mcu_l3gic_parents, CLK_CFG_5, CLK_CFG_5_SET,
CLK_CFG_5_CLR, 8, 2,
CLK_CFG_UPDATE, TOP_MUX_MCU_L3GIC_SHIFT),
MUX_CLR_SET_UPD(CLK_TOP_MCINFRA, "mcu_infra",
mcu_infra_parents, CLK_CFG_5, CLK_CFG_5_SET,
CLK_CFG_5_CLR, 16, 3,
CLK_CFG_UPDATE, TOP_MUX_MCU_INFRA_SHIFT),
MUX_CLR_SET_UPD(CLK_TOP_DSP, "dsp",
dsp_parents, CLK_CFG_5, CLK_CFG_5_SET,
CLK_CFG_5_CLR, 24, 3,
CLK_CFG_UPDATE, TOP_MUX_DSP_SHIFT),
/* CLK_CFG_6 */
MUX_GATE_FENC_CLR_SET_UPD_FLAGS(CLK_TOP_MFG_REF, "mfg_ref", mfg_ref_parents,
NULL, ARRAY_SIZE(mfg_ref_parents),
CLK_CFG_6, CLK_CFG_6_SET, CLK_CFG_6_CLR,
0, 1, 7, CLK_CFG_UPDATE, TOP_MUX_MFG_REF_SHIFT,
CLK_FENC_STATUS_MON_0, 7, CLK_IGNORE_UNUSED),
MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_EB, "mfg_eb",
mfg_eb_parents, CLK_CFG_6, CLK_CFG_6_SET,
CLK_CFG_6_CLR, 16, 2,
23, CLK_CFG_UPDATE, TOP_MUX_MFG_EB_SHIFT),
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP_UART, "uart", uart_parents,
CLK_CFG_6, CLK_CFG_6_SET, CLK_CFG_6_CLR,
HWV_CG_3_DONE, HWV_CG_3_SET, HWV_CG_3_CLR,
24, 2, 31, CLK_CFG_UPDATE, TOP_MUX_UART_SHIFT,
CLK_FENC_STATUS_MON_0, 4),
/* CLK_CFG_7 */
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP_SPI0_BCLK, "spi0_b", spi_b_parents,
CLK_CFG_7, CLK_CFG_7_SET, CLK_CFG_7_CLR,
HWV_CG_4_DONE, HWV_CG_4_SET, HWV_CG_4_CLR,
0, 3, 7, CLK_CFG_UPDATE, TOP_MUX_SPI0_BCLK_SHIFT,
CLK_FENC_STATUS_MON_0, 3),
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP_SPI1_BCLK, "spi1_b", spi_b_parents,
CLK_CFG_7, CLK_CFG_7_SET, CLK_CFG_7_CLR,
HWV_CG_4_DONE, HWV_CG_4_SET, HWV_CG_4_CLR,
8, 3, 15, CLK_CFG_UPDATE, TOP_MUX_SPI1_BCLK_SHIFT,
CLK_FENC_STATUS_MON_0, 2),
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP_SPI2_BCLK, "spi2_b", spi_b_parents,
CLK_CFG_7, CLK_CFG_7_SET, CLK_CFG_7_CLR,
HWV_CG_4_DONE, HWV_CG_4_SET, HWV_CG_4_CLR,
16, 3, 23, CLK_CFG_UPDATE, TOP_MUX_SPI2_BCLK_SHIFT,
CLK_FENC_STATUS_MON_0, 1),
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP_SPI3_BCLK, "spi3_b", spi_b_parents,
CLK_CFG_7, CLK_CFG_7_SET, CLK_CFG_7_CLR,
HWV_CG_4_DONE, HWV_CG_4_SET, HWV_CG_4_CLR,
24, 3, 31, CLK_CFG_UPDATE1, TOP_MUX_SPI3_BCLK_SHIFT,
CLK_FENC_STATUS_MON_0, 0),
/* CLK_CFG_8 */
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP_SPI4_BCLK, "spi4_b", spi_b_parents,
CLK_CFG_8, CLK_CFG_8_SET, CLK_CFG_8_CLR,
HWV_CG_5_DONE, HWV_CG_5_SET, HWV_CG_5_CLR,
0, 3, 7, CLK_CFG_UPDATE1, TOP_MUX_SPI4_BCLK_SHIFT,
CLK_FENC_STATUS_MON_1, 31),
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP_SPI5_BCLK, "spi5_b", spi_b_parents,
CLK_CFG_8, CLK_CFG_8_SET, CLK_CFG_8_CLR,
HWV_CG_5_DONE, HWV_CG_5_SET, HWV_CG_5_CLR,
8, 3, 15, CLK_CFG_UPDATE1, TOP_MUX_SPI5_BCLK_SHIFT,
CLK_FENC_STATUS_MON_1, 30),
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP_SPI6_BCLK, "spi6_b", spi_b_parents,
CLK_CFG_8, CLK_CFG_8_SET, CLK_CFG_8_CLR,
HWV_CG_5_DONE, HWV_CG_5_SET, HWV_CG_5_CLR,
16, 3, 23, CLK_CFG_UPDATE1, TOP_MUX_SPI6_BCLK_SHIFT,
CLK_FENC_STATUS_MON_1, 29),
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP_SPI7_BCLK, "spi7_b", spi_b_parents,
CLK_CFG_8, CLK_CFG_8_SET, CLK_CFG_8_CLR,
HWV_CG_5_DONE, HWV_CG_5_SET, HWV_CG_5_CLR,
24, 3, 31, CLK_CFG_UPDATE1, TOP_MUX_SPI7_BCLK_SHIFT,
CLK_FENC_STATUS_MON_1, 28),
/* CLK_CFG_9 */
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_MSDC30_1, "msdc30_1", msdc30_parents,
CLK_CFG_9, CLK_CFG_9_SET, CLK_CFG_9_CLR,
16, 3, 23, CLK_CFG_UPDATE1, TOP_MUX_MSDC30_1_SHIFT,
CLK_FENC_STATUS_MON_1, 25),
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_MSDC30_2, "msdc30_2", msdc30_parents,
CLK_CFG_9, CLK_CFG_9_SET, CLK_CFG_9_CLR,
24, 3, 31, CLK_CFG_UPDATE1, TOP_MUX_MSDC30_2_SHIFT,
CLK_FENC_STATUS_MON_1, 24),
/* CLK_CFG_10 */
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_DISP_PWM, "disp_pwm", disp_pwm_parents,
CLK_CFG_10, CLK_CFG_10_SET, CLK_CFG_10_CLR,
0, 3, 7, CLK_CFG_UPDATE1, TOP_MUX_DISP_PWM_SHIFT,
CLK_FENC_STATUS_MON_1, 23),
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_USB_TOP_1P, "usb_1p", usb_1p_parents,
CLK_CFG_10, CLK_CFG_10_SET, CLK_CFG_10_CLR,
8, 1, 15, CLK_CFG_UPDATE1, TOP_MUX_USB_TOP_1P_SHIFT,
CLK_FENC_STATUS_MON_1, 22),
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_USB_XHCI_1P, "usb_xhci_1p", usb_1p_parents,
CLK_CFG_10, CLK_CFG_10_SET, CLK_CFG_10_CLR,
16, 1, 23, CLK_CFG_UPDATE1, TOP_MUX_SSUSB_XHCI_1P_SHIFT,
CLK_FENC_STATUS_MON_1, 21),
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_USB_FMCNT_P1, "usb_fmcnt_p1", usb_fmcnt_p1_parents,
CLK_CFG_10, CLK_CFG_10_SET, CLK_CFG_10_CLR,
24, 1, 31, CLK_CFG_UPDATE1, TOP_MUX_SSUSB_FMCNT_P1_SHIFT,
CLK_FENC_STATUS_MON_1, 20),
/* CLK_CFG_11 */
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_I2C_P, "i2c_p", i2c_parents,
CLK_CFG_11, CLK_CFG_11_SET, CLK_CFG_11_CLR,
0, 3, 7, CLK_CFG_UPDATE1, TOP_MUX_I2C_PERI_SHIFT,
CLK_FENC_STATUS_MON_1, 19),
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_I2C_EAST, "i2c_east", i2c_parents,
CLK_CFG_11, CLK_CFG_11_SET, CLK_CFG_11_CLR,
8, 3, 15, CLK_CFG_UPDATE1, TOP_MUX_I2C_EAST_SHIFT,
CLK_FENC_STATUS_MON_1, 18),
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_I2C_WEST, "i2c_west", i2c_parents,
CLK_CFG_11, CLK_CFG_11_SET, CLK_CFG_11_CLR,
16, 3, 23, CLK_CFG_UPDATE1, TOP_MUX_I2C_WEST_SHIFT,
CLK_FENC_STATUS_MON_1, 17),
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP_I2C_NORTH, "i2c_north", i2c_parents,
CLK_CFG_11, CLK_CFG_11_SET, CLK_CFG_11_CLR,
HWV_CG_6_DONE, HWV_CG_6_SET, HWV_CG_6_CLR,
24, 3, 31, CLK_CFG_UPDATE1, TOP_MUX_I2C_NORTH_SHIFT,
CLK_FENC_STATUS_MON_1, 16),
/* CLK_CFG_12 */
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_AES_UFSFDE, "aes_ufsfde", aes_ufsfde_parents,
CLK_CFG_12, CLK_CFG_12_SET, CLK_CFG_12_CLR,
0, 3, 7, CLK_CFG_UPDATE1, TOP_MUX_AES_UFSFDE_SHIFT,
CLK_FENC_STATUS_MON_1, 15),
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_UFS, "ufs", ufs_parents,
CLK_CFG_12, CLK_CFG_12_SET, CLK_CFG_12_CLR,
8, 3, 15, CLK_CFG_UPDATE1, TOP_MUX_UFS_SHIFT,
CLK_FENC_STATUS_MON_1, 14),
/* CLK_CFG_13 */
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_AUD_1, "aud_1", aud_1_parents,
CLK_CFG_13, CLK_CFG_13_SET, CLK_CFG_13_CLR,
0, 1, 7, CLK_CFG_UPDATE1, TOP_MUX_AUD_1_SHIFT,
CLK_FENC_STATUS_MON_1, 11),
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_AUD_2, "aud_2", aud_2_parents,
CLK_CFG_13, CLK_CFG_13_SET, CLK_CFG_13_CLR,
8, 1, 15, CLK_CFG_UPDATE1, TOP_MUX_AUD_2_SHIFT,
CLK_FENC_STATUS_MON_1, 10),
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_ADSP, "adsp", adsp_parents,
CLK_CFG_13, CLK_CFG_13_SET, CLK_CFG_13_CLR,
16, 1, 23, CLK_CFG_UPDATE1, TOP_MUX_ADSP_SHIFT,
CLK_FENC_STATUS_MON_1, 9),
MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP_UARTHUB_B, "adsp_uarthub_b",
adsp_uarthub_b_parents, CLK_CFG_13, CLK_CFG_13_SET,
CLK_CFG_13_CLR, 24, 2, 31,
CLK_CFG_UPDATE1, TOP_MUX_ADSP_UARTHUB_B_SHIFT),
/* CLK_CFG_14 */
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_DPMAIF_MAIN, "dpmaif_main", dpmaif_main_parents,
CLK_CFG_14, CLK_CFG_14_SET, CLK_CFG_14_CLR,
0, 4, 7, CLK_CFG_UPDATE1, TOP_MUX_DPMAIF_MAIN_SHIFT,
CLK_FENC_STATUS_MON_1, 7),
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_PWM, "pwm", pwm_parents,
CLK_CFG_14, CLK_CFG_14_SET, CLK_CFG_14_CLR,
8, 2, 15, CLK_CFG_UPDATE1, TOP_MUX_PWM_SHIFT,
CLK_FENC_STATUS_MON_1, 6),
MUX_CLR_SET_UPD(CLK_TOP_MCUPM, "mcupm",
mcupm_parents, CLK_CFG_14, CLK_CFG_14_SET,
CLK_CFG_14_CLR, 16, 3,
CLK_CFG_UPDATE1, TOP_MUX_MCUPM_SHIFT),
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_SFLASH, "sflash", sflash_parents,
CLK_CFG_14, CLK_CFG_14_SET, CLK_CFG_14_CLR,
24, 2, 31, CLK_CFG_UPDATE1, TOP_MUX_SFLASH_SHIFT,
CLK_FENC_STATUS_MON_1, 4),
/* CLK_CFG_15 */
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_IPSEAST, "ipseast", ipseast_parents,
CLK_CFG_15, CLK_CFG_15_SET, CLK_CFG_15_CLR,
0, 3, 7, CLK_CFG_UPDATE1, TOP_MUX_IPSEAST_SHIFT,
CLK_FENC_STATUS_MON_1, 3),
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_TL, "tl", tl_parents,
CLK_CFG_15, CLK_CFG_15_SET, CLK_CFG_15_CLR,
16, 2, 23, CLK_CFG_UPDATE2, TOP_MUX_TL_SHIFT,
CLK_FENC_STATUS_MON_1, 1),
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_TL_P1, "tl_p1", tl_parents,
CLK_CFG_15, CLK_CFG_15_SET, CLK_CFG_15_CLR,
24, 2, 31, CLK_CFG_UPDATE2, TOP_MUX_TL_P1_SHIFT,
CLK_FENC_STATUS_MON_1, 0),
/* CLK_CFG_16 */
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP_TL_P2, "tl_p2", tl_parents,
CLK_CFG_16, CLK_CFG_16_SET, CLK_CFG_16_CLR,
0, 2, 7, CLK_CFG_UPDATE2, TOP_MUX_TL_P2_SHIFT,
CLK_FENC_STATUS_MON_2, 31),
MUX_CLR_SET_UPD(CLK_TOP_EMI_INTERFACE_546, "emi_interface_546",
md_emi_parents, CLK_CFG_16, CLK_CFG_16_SET,
CLK_CFG_16_CLR, 8, 1,
CLK_CFG_UPDATE2, TOP_MUX_EMI_INTERFACE_546_SHIFT),
MUX_CLR_SET_UPD(CLK_TOP_SDF, "sdf",
sdf_parents, CLK_CFG_16, CLK_CFG_16_SET,
CLK_CFG_16_CLR, 16, 3,
CLK_CFG_UPDATE2, TOP_MUX_SDF_SHIFT),
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP_UARTHUB_BCLK, "uarthub_b", uarthub_b_parents,
CLK_CFG_16, CLK_CFG_16_SET, CLK_CFG_16_CLR,
HWV_CG_7_DONE, HWV_CG_7_SET, HWV_CG_7_CLR,
24, 2, 31, CLK_CFG_UPDATE2, TOP_MUX_UARTHUB_BCLK_SHIFT,
CLK_FENC_STATUS_MON_2, 28),
/* CLK_CFG_17 */
MUX_CLR_SET_UPD(CLK_TOP_DPSW_CMP_26M, "dpsw_cmp_26m",
dpsw_cmp_26m_parents, CLK_CFG_17, CLK_CFG_17_SET,
CLK_CFG_17_CLR, 0, 1,
CLK_CFG_UPDATE2, TOP_MUX_DPSW_CMP_26M_SHIFT),
MUX_CLR_SET_UPD(CLK_TOP_SMAP, "smap",
smapparents, CLK_CFG_17, CLK_CFG_17_SET,
CLK_CFG_17_CLR, 8, 1,
CLK_CFG_UPDATE2, TOP_MUX_SMAPCK_SHIFT),
MUX_CLR_SET_UPD(CLK_TOP_SSR_PKA, "ssr_pka",
ssr_parents, CLK_CFG_17, CLK_CFG_17_SET,
CLK_CFG_17_CLR, 16, 3,
CLK_CFG_UPDATE2, TOP_MUX_SSR_PKA_SHIFT),
MUX_CLR_SET_UPD(CLK_TOP_SSR_DMA, "ssr_dma",
ssr_parents, CLK_CFG_17, CLK_CFG_17_SET,
CLK_CFG_17_CLR, 24, 3,
CLK_CFG_UPDATE2, TOP_MUX_SSR_DMA_SHIFT),
/* CLK_CFG_18 */
MUX_CLR_SET_UPD(CLK_TOP_SSR_KDF, "ssr_kdf",
ssr_kdf_parents, CLK_CFG_18, CLK_CFG_18_SET,
CLK_CFG_18_CLR, 0, 2,
CLK_CFG_UPDATE2, TOP_MUX_SSR_KDF_SHIFT),
MUX_CLR_SET_UPD(CLK_TOP_SSR_RNG, "ssr_rng",
ssr_rng_parents, CLK_CFG_18, CLK_CFG_18_SET,
CLK_CFG_18_CLR, 8, 2,
CLK_CFG_UPDATE2, TOP_MUX_SSR_RNG_SHIFT),
MUX_CLR_SET_UPD(CLK_TOP_SPU0, "spu0",
spu_parents, CLK_CFG_18, CLK_CFG_18_SET,
CLK_CFG_18_CLR, 16, 3,
CLK_CFG_UPDATE2, TOP_MUX_SPU0_SHIFT),
MUX_CLR_SET_UPD(CLK_TOP_SPU1, "spu1",
spu_parents, CLK_CFG_18, CLK_CFG_18_SET,
CLK_CFG_18_CLR, 24, 3,
CLK_CFG_UPDATE2, TOP_MUX_SPU1_SHIFT),
/* CLK_CFG_19 */
MUX_CLR_SET_UPD(CLK_TOP_DXCC, "dxcc",
dxcc_parents, CLK_CFG_19, CLK_CFG_19_SET,
CLK_CFG_19_CLR, 0, 2,
CLK_CFG_UPDATE2, TOP_MUX_DXCC_SHIFT),
};
static const struct mtk_composite top_aud_divs[] = {
/* CLK_AUDDIV_2 */
MUX_DIV_GATE(CLK_TOP_APLL_I2SIN0, "apll_i2sin0_m", apll_m_parents,
CLK_AUDDIV_0, 16, 1, CLK_AUDDIV_2, 0, 8, CLK_AUDDIV_0, 0),
MUX_DIV_GATE(CLK_TOP_APLL_I2SIN1, "apll_i2sin1_m", apll_m_parents,
CLK_AUDDIV_0, 17, 1, CLK_AUDDIV_2, 8, 8, CLK_AUDDIV_0, 1),
MUX_DIV_GATE(CLK_TOP_APLL_I2SIN2, "apll_i2sin2_m", apll_m_parents,
CLK_AUDDIV_0, 18, 1, CLK_AUDDIV_2, 16, 8, CLK_AUDDIV_0, 2),
MUX_DIV_GATE(CLK_TOP_APLL_I2SIN3, "apll_i2sin3_m", apll_m_parents,
CLK_AUDDIV_0, 19, 1, CLK_AUDDIV_2, 24, 8, CLK_AUDDIV_0, 3),
/* CLK_AUDDIV_3 */
MUX_DIV_GATE(CLK_TOP_APLL_I2SIN4, "apll_i2sin4_m", apll_m_parents,
CLK_AUDDIV_0, 20, 1, CLK_AUDDIV_3, 0, 8, CLK_AUDDIV_0, 4),
MUX_DIV_GATE(CLK_TOP_APLL_I2SIN6, "apll_i2sin6_m", apll_m_parents,
CLK_AUDDIV_0, 21, 1, CLK_AUDDIV_3, 8, 8, CLK_AUDDIV_0, 5),
MUX_DIV_GATE(CLK_TOP_APLL_I2SOUT0, "apll_i2sout0_m", apll_m_parents,
CLK_AUDDIV_0, 22, 1, CLK_AUDDIV_3, 16, 8, CLK_AUDDIV_0, 6),
MUX_DIV_GATE(CLK_TOP_APLL_I2SOUT1, "apll_i2sout1_m", apll_m_parents,
CLK_AUDDIV_0, 23, 1, CLK_AUDDIV_3, 24, 8, CLK_AUDDIV_0, 7),
/* CLK_AUDDIV_4 */
MUX_DIV_GATE(CLK_TOP_APLL_I2SOUT2, "apll_i2sout2_m", apll_m_parents,
CLK_AUDDIV_0, 24, 1, CLK_AUDDIV_4, 0, 8, CLK_AUDDIV_0, 8),
MUX_DIV_GATE(CLK_TOP_APLL_I2SOUT3, "apll_i2sout3_m", apll_m_parents,
CLK_AUDDIV_0, 25, 1, CLK_AUDDIV_4, 8, 8, CLK_AUDDIV_0, 9),
MUX_DIV_GATE(CLK_TOP_APLL_I2SOUT4, "apll_i2sout4_m", apll_m_parents,
CLK_AUDDIV_0, 26, 1, CLK_AUDDIV_4, 16, 8, CLK_AUDDIV_0, 10),
MUX_DIV_GATE(CLK_TOP_APLL_I2SOUT6, "apll_i2sout6_m", apll_m_parents,
CLK_AUDDIV_0, 27, 1, CLK_AUDDIV_4, 24, 8, CLK_AUDDIV_0, 11),
/* CLK_AUDDIV_5 */
MUX_DIV_GATE(CLK_TOP_APLL_FMI2S, "apll_fmi2s_m", apll_m_parents,
CLK_AUDDIV_0, 28, 1, CLK_AUDDIV_5, 0, 8, CLK_AUDDIV_0, 12),
MUX(CLK_TOP_APLL_TDMOUT, "apll_tdmout_m",
apll_m_parents, CLK_AUDDIV_0, 29, 1),
DIV_GATE(CLK_TOP_APLL12_DIV_TDMOUT_M, "apll12_div_tdmout_m",
"apll_tdmout_m", CLK_AUDDIV_0,
13, CLK_AUDDIV_5, 8, 8),
DIV_GATE(CLK_TOP_APLL12_DIV_TDMOUT_B, "apll12_div_tdmout_b",
"apll_tdmout_m", CLK_AUDDIV_0,
14, CLK_AUDDIV_5, 8, 16),
};
static const struct mtk_clk_desc topck_desc = {
.factor_clks = top_divs,
.num_factor_clks = ARRAY_SIZE(top_divs),
.mux_clks = top_muxes,
.num_mux_clks = ARRAY_SIZE(top_muxes),
.composite_clks = top_aud_divs,
.num_composite_clks = ARRAY_SIZE(top_aud_divs)
};
static const struct of_device_id of_match_clk_mt8196_ck[] = {
{ .compatible = "mediatek,mt8196-topckgen", .data = &topck_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_ck);
static struct platform_driver clk_mt8196_topck_drv = {
.probe = mtk_clk_simple_probe,
.remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8196-topck",
.of_match_table = of_match_clk_mt8196_ck,
},
};
MODULE_DESCRIPTION("MediaTek MT8196 top clock generators driver");
module_platform_driver(clk_mt8196_topck_drv);
MODULE_LICENSE("GPL");

568
drivers/clk/mediatek/clk-mt8196-topckgen2.c Normal file
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2025 MediaTek Inc.
* Guangjie Song <guangjie.song@mediatek.com>
* Copyright (c) 2025 Collabora Ltd.
* Laura Nao <laura.nao@collabora.com>
*/
#include <dt-bindings/clock/mediatek,mt8196-clock.h>
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-mux.h"
/* MUX SEL REG */
#define CKSYS2_CLK_CFG_UPDATE 0x0004
#define CKSYS2_CLK_CFG_0 0x0010
#define CKSYS2_CLK_CFG_0_SET 0x0014
#define CKSYS2_CLK_CFG_0_CLR 0x0018
#define CKSYS2_CLK_CFG_1 0x0020
#define CKSYS2_CLK_CFG_1_SET 0x0024
#define CKSYS2_CLK_CFG_1_CLR 0x0028
#define CKSYS2_CLK_CFG_2 0x0030
#define CKSYS2_CLK_CFG_2_SET 0x0034
#define CKSYS2_CLK_CFG_2_CLR 0x0038
#define CKSYS2_CLK_CFG_3 0x0040
#define CKSYS2_CLK_CFG_3_SET 0x0044
#define CKSYS2_CLK_CFG_3_CLR 0x0048
#define CKSYS2_CLK_CFG_4 0x0050
#define CKSYS2_CLK_CFG_4_SET 0x0054
#define CKSYS2_CLK_CFG_4_CLR 0x0058
#define CKSYS2_CLK_CFG_5 0x0060
#define CKSYS2_CLK_CFG_5_SET 0x0064
#define CKSYS2_CLK_CFG_5_CLR 0x0068
#define CKSYS2_CLK_CFG_6 0x0070
#define CKSYS2_CLK_CFG_6_SET 0x0074
#define CKSYS2_CLK_CFG_6_CLR 0x0078
#define CKSYS2_CLK_FENC_STATUS_MON_0 0x0174
/* MUX SHIFT */
#define TOP_MUX_SENINF0_SHIFT 0
#define TOP_MUX_SENINF1_SHIFT 1
#define TOP_MUX_SENINF2_SHIFT 2
#define TOP_MUX_SENINF3_SHIFT 3
#define TOP_MUX_SENINF4_SHIFT 4
#define TOP_MUX_SENINF5_SHIFT 5
#define TOP_MUX_IMG1_SHIFT 6
#define TOP_MUX_IPE_SHIFT 7
#define TOP_MUX_CAM_SHIFT 8
#define TOP_MUX_CAMTM_SHIFT 9
#define TOP_MUX_DPE_SHIFT 10
#define TOP_MUX_VDEC_SHIFT 11
#define TOP_MUX_CCUSYS_SHIFT 12
#define TOP_MUX_CCUTM_SHIFT 13
#define TOP_MUX_VENC_SHIFT 14
#define TOP_MUX_DVO_SHIFT 15
#define TOP_MUX_DVO_FAVT_SHIFT 16
#define TOP_MUX_DP1_SHIFT 17
#define TOP_MUX_DP0_SHIFT 18
#define TOP_MUX_DISP_SHIFT 19
#define TOP_MUX_MDP_SHIFT 20
#define TOP_MUX_MMINFRA_SHIFT 21
#define TOP_MUX_MMINFRA_SNOC_SHIFT 22
#define TOP_MUX_MMUP_SHIFT 23
#define TOP_MUX_MMINFRA_AO_SHIFT 26
/* HW Voter REG */
#define HWV_CG_30_SET 0x0058
#define HWV_CG_30_CLR 0x005c
#define HWV_CG_30_DONE 0x2c2c
#define MM_HWV_CG_30_SET 0x00f0
#define MM_HWV_CG_30_CLR 0x00f4
#define MM_HWV_CG_30_DONE 0x2c78
#define MM_HWV_CG_31_SET 0x00f8
#define MM_HWV_CG_31_CLR 0x00fc
#define MM_HWV_CG_31_DONE 0x2c7c
#define MM_HWV_CG_32_SET 0x0100
#define MM_HWV_CG_32_CLR 0x0104
#define MM_HWV_CG_32_DONE 0x2c80
#define MM_HWV_CG_33_SET 0x0108
#define MM_HWV_CG_33_CLR 0x010c
#define MM_HWV_CG_33_DONE 0x2c84
#define MM_HWV_CG_34_SET 0x0110
#define MM_HWV_CG_34_CLR 0x0114
#define MM_HWV_CG_34_DONE 0x2c88
#define MM_HWV_CG_35_SET 0x0118
#define MM_HWV_CG_35_CLR 0x011c
#define MM_HWV_CG_35_DONE 0x2c8c
#define MM_HWV_CG_36_SET 0x0120
#define MM_HWV_CG_36_CLR 0x0124
#define MM_HWV_CG_36_DONE 0x2c90
#define MM_HWV_MUX_UPDATE_31_0 0x0240
static const struct mtk_fixed_factor top_divs[] = {
FACTOR(CLK_TOP2_MAINPLL2_D2, "mainpll2_d2", "mainpll2", 1, 2),
FACTOR(CLK_TOP2_MAINPLL2_D3, "mainpll2_d3", "mainpll2", 1, 3),
FACTOR(CLK_TOP2_MAINPLL2_D4, "mainpll2_d4", "mainpll2", 1, 4),
FACTOR(CLK_TOP2_MAINPLL2_D4_D2, "mainpll2_d4_d2", "mainpll2", 1, 8),
FACTOR(CLK_TOP2_MAINPLL2_D4_D4, "mainpll2_d4_d4", "mainpll2", 1, 16),
FACTOR(CLK_TOP2_MAINPLL2_D5, "mainpll2_d5", "mainpll2", 1, 5),
FACTOR(CLK_TOP2_MAINPLL2_D5_D2, "mainpll2_d5_d2", "mainpll2", 1, 10),
FACTOR(CLK_TOP2_MAINPLL2_D6, "mainpll2_d6", "mainpll2", 1, 6),
FACTOR(CLK_TOP2_MAINPLL2_D6_D2, "mainpll2_d6_d2", "mainpll2", 1, 12),
FACTOR(CLK_TOP2_MAINPLL2_D7, "mainpll2_d7", "mainpll2", 1, 7),
FACTOR(CLK_TOP2_MAINPLL2_D7_D2, "mainpll2_d7_d2", "mainpll2", 1, 14),
FACTOR(CLK_TOP2_MAINPLL2_D9, "mainpll2_d9", "mainpll2", 1, 9),
FACTOR(CLK_TOP2_UNIVPLL2_D3, "univpll2_d3", "univpll2", 1, 3),
FACTOR(CLK_TOP2_UNIVPLL2_D4, "univpll2_d4", "univpll2", 1, 4),
FACTOR(CLK_TOP2_UNIVPLL2_D4_D2, "univpll2_d4_d2", "univpll2", 1, 8),
FACTOR(CLK_TOP2_UNIVPLL2_D5, "univpll2_d5", "univpll2", 1, 5),
FACTOR(CLK_TOP2_UNIVPLL2_D5_D2, "univpll2_d5_d2", "univpll2", 1, 10),
FACTOR(CLK_TOP2_UNIVPLL2_D6, "univpll2_d6", "univpll2", 1, 6),
FACTOR(CLK_TOP2_UNIVPLL2_D6_D2, "univpll2_d6_d2", "univpll2", 1, 12),
FACTOR(CLK_TOP2_UNIVPLL2_D6_D4, "univpll2_d6_d4", "univpll2", 1, 24),
FACTOR(CLK_TOP2_UNIVPLL2_D7, "univpll2_d7", "univpll2", 1, 7),
FACTOR(CLK_TOP2_IMGPLL_D2, "imgpll_d2", "imgpll", 1, 2),
FACTOR(CLK_TOP2_IMGPLL_D4, "imgpll_d4", "imgpll", 1, 4),
FACTOR(CLK_TOP2_IMGPLL_D5, "imgpll_d5", "imgpll", 1, 5),
FACTOR(CLK_TOP2_IMGPLL_D5_D2, "imgpll_d5_d2", "imgpll", 1, 10),
FACTOR(CLK_TOP2_MMPLL2_D3, "mmpll2_d3", "mmpll2", 1, 3),
FACTOR(CLK_TOP2_MMPLL2_D4, "mmpll2_d4", "mmpll2", 1, 4),
FACTOR(CLK_TOP2_MMPLL2_D4_D2, "mmpll2_d4_d2", "mmpll2", 1, 8),
FACTOR(CLK_TOP2_MMPLL2_D5, "mmpll2_d5", "mmpll2", 1, 5),
FACTOR(CLK_TOP2_MMPLL2_D5_D2, "mmpll2_d5_d2", "mmpll2", 1, 10),
FACTOR(CLK_TOP2_MMPLL2_D6, "mmpll2_d6", "mmpll2", 1, 6),
FACTOR(CLK_TOP2_MMPLL2_D6_D2, "mmpll2_d6_d2", "mmpll2", 1, 12),
FACTOR(CLK_TOP2_MMPLL2_D7, "mmpll2_d7", "mmpll2", 1, 7),
FACTOR(CLK_TOP2_MMPLL2_D9, "mmpll2_d9", "mmpll2", 1, 9),
FACTOR(CLK_TOP2_TVDPLL1_D4, "tvdpll1_d4", "tvdpll1", 1, 4),
FACTOR(CLK_TOP2_TVDPLL1_D8, "tvdpll1_d8", "tvdpll1", 1, 8),
FACTOR(CLK_TOP2_TVDPLL1_D16, "tvdpll1_d16", "tvdpll1", 1, 16),
FACTOR(CLK_TOP2_TVDPLL2_D2, "tvdpll2_d2", "tvdpll2", 1, 2),
FACTOR(CLK_TOP2_TVDPLL2_D4, "tvdpll2_d4", "tvdpll2", 1, 4),
FACTOR(CLK_TOP2_TVDPLL2_D8, "tvdpll2_d8", "tvdpll2", 1, 8),
FACTOR(CLK_TOP2_TVDPLL2_D16, "tvdpll2_d16", "tvdpll2", 92, 1473),
FACTOR(CLK_TOP2_TVDPLL3_D2, "tvdpll3_d2", "tvdpll3", 1, 2),
FACTOR(CLK_TOP2_TVDPLL3_D4, "tvdpll3_d4", "tvdpll3", 1, 4),
FACTOR(CLK_TOP2_TVDPLL3_D8, "tvdpll3_d8", "tvdpll3", 1, 8),
FACTOR(CLK_TOP2_TVDPLL3_D16, "tvdpll3_d16", "tvdpll3", 92, 1473),
};
static const char * const seninf_parents[] = {
"clk26m",
"ck_osc_d10",
"ck_osc_d8",
"ck_osc_d5",
"ck_osc_d4",
"univpll2_d6_d2",
"mainpll2_d9",
"ck_osc_d2",
"mainpll2_d4_d2",
"univpll2_d4_d2",
"mmpll2_d4_d2",
"univpll2_d7",
"mainpll2_d6",
"mmpll2_d7",
"univpll2_d6",
"univpll2_d5"
};
static const char * const img1_parents[] = {
"clk26m",
"ck_osc_d4",
"ck_osc_d3",
"mmpll2_d6_d2",
"ck_osc_d2",
"imgpll_d5_d2",
"mmpll2_d5_d2",
"univpll2_d4_d2",
"mmpll2_d4_d2",
"mmpll2_d7",
"univpll2_d6",
"mmpll2_d6",
"univpll2_d5",
"mmpll2_d5",
"univpll2_d4",
"imgpll_d4"
};
static const char * const ipe_parents[] = {
"clk26m",
"ck_osc_d4",
"ck_osc_d3",
"ck_osc_d2",
"univpll2_d6",
"mmpll2_d6",
"univpll2_d5",
"imgpll_d5",
"ck_mainpll_d4",
"mmpll2_d5",
"imgpll_d4"
};
static const char * const cam_parents[] = {
"clk26m",
"ck_osc_d10",
"ck_osc_d4",
"ck_osc_d3",
"ck_osc_d2",
"mmpll2_d5_d2",
"univpll2_d4_d2",
"univpll2_d7",
"mmpll2_d7",
"univpll2_d6",
"mmpll2_d6",
"univpll2_d5",
"mmpll2_d5",
"univpll2_d4",
"imgpll_d4",
"mmpll2_d4"
};
static const char * const camtm_parents[] = {
"clk26m",
"univpll2_d6_d4",
"ck_osc_d4",
"ck_osc_d3",
"univpll2_d6_d2"
};
static const char * const dpe_parents[] = {
"clk26m",
"mmpll2_d5_d2",
"univpll2_d4_d2",
"mmpll2_d7",
"univpll2_d6",
"mmpll2_d6",
"univpll2_d5",
"mmpll2_d5",
"imgpll_d4",
"mmpll2_d4"
};
static const char * const vdec_parents[] = {
"clk26m",
"ck_mainpll_d5_d2",
"mainpll2_d4_d4",
"mainpll2_d7_d2",
"mainpll2_d6_d2",
"mainpll2_d5_d2",
"mainpll2_d9",
"mainpll2_d4_d2",
"mainpll2_d7",
"mainpll2_d6",
"univpll2_d6",
"mainpll2_d5",
"mainpll2_d4",
"imgpll_d2"
};
static const char * const ccusys_parents[] = {
"clk26m",
"ck_osc_d4",
"ck_osc_d3",
"ck_osc_d2",
"mmpll2_d5_d2",
"univpll2_d4_d2",
"mmpll2_d7",
"univpll2_d6",
"mmpll2_d6",
"univpll2_d5",
"mainpll2_d4",
"mainpll2_d3",
"univpll2_d3"
};
static const char * const ccutm_parents[] = {
"clk26m",
"univpll2_d6_d4",
"ck_osc_d4",
"ck_osc_d3",
"univpll2_d6_d2"
};
static const char * const venc_parents[] = {
"clk26m",
"mainpll2_d5_d2",
"univpll2_d5_d2",
"mainpll2_d4_d2",
"mmpll2_d9",
"univpll2_d4_d2",
"mmpll2_d4_d2",
"mainpll2_d6",
"univpll2_d6",
"mainpll2_d5",
"mmpll2_d6",
"univpll2_d5",
"mainpll2_d4",
"univpll2_d4",
"univpll2_d3"
};
static const char * const dp1_parents[] = {
"clk26m",
"tvdpll2_d16",
"tvdpll2_d8",
"tvdpll2_d4",
"tvdpll2_d2"
};
static const char * const dp0_parents[] = {
"clk26m",
"tvdpll1_d16",
"tvdpll1_d8",
"tvdpll1_d4",
"ck_tvdpll1_d2"
};
static const char * const disp_parents[] = {
"clk26m",
"ck_mainpll_d5_d2",
"ck_mainpll_d4_d2",
"ck_mainpll_d6",
"mainpll2_d5",
"mmpll2_d6",
"mainpll2_d4",
"univpll2_d4",
"mainpll2_d3"
};
static const char * const mdp_parents[] = {
"clk26m",
"ck_mainpll_d5_d2",
"mainpll2_d5_d2",
"mmpll2_d6_d2",
"mainpll2_d9",
"mainpll2_d4_d2",
"mainpll2_d7",
"mainpll2_d6",
"mainpll2_d5",
"mmpll2_d6",
"mainpll2_d4",
"univpll2_d4",
"mainpll2_d3"
};
static const char * const mminfra_parents[] = {
"clk26m",
"ck_osc_d4",
"ck_mainpll_d7_d2",
"ck_mainpll_d5_d2",
"ck_mainpll_d9",
"mmpll2_d6_d2",
"mainpll2_d4_d2",
"ck_mainpll_d6",
"univpll2_d6",
"mainpll2_d5",
"mmpll2_d6",
"univpll2_d5",
"mainpll2_d4",
"univpll2_d4",
"mainpll2_d3",
"univpll2_d3"
};
static const char * const mminfra_snoc_parents[] = {
"clk26m",
"ck_osc_d4",
"ck_mainpll_d7_d2",
"ck_mainpll_d9",
"ck_mainpll_d7",
"ck_mainpll_d6",
"mmpll2_d4_d2",
"ck_mainpll_d5",
"ck_mainpll_d4",
"univpll2_d4",
"mmpll2_d4",
"mainpll2_d3",
"univpll2_d3",
"mmpll2_d3",
"mainpll2_d2"
};
static const char * const mmup_parents[] = {
"clk26m",
"mainpll2_d6",
"mainpll2_d5",
"ck_osc_d2",
"ck_osc",
"ck_mainpll_d4",
"univpll2_d4",
"mainpll2_d3"
};
static const char * const mminfra_ao_parents[] = {
"clk26m",
"ck_osc_d4",
"ck_mainpll_d3"
};
static const char * const dvo_parents[] = {
"clk26m",
"tvdpll3_d16",
"tvdpll3_d8",
"tvdpll3_d4",
"tvdpll3_d2"
};
static const char * const dvo_favt_parents[] = {
"clk26m",
"tvdpll3_d16",
"tvdpll3_d8",
"tvdpll3_d4",
"vlp_apll1",
"vlp_apll2",
"tvdpll3_d2"
};
static const struct mtk_mux top_muxes[] = {
/* CKSYS2_CLK_CFG_0 */
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_SENINF0, "seninf0", seninf_parents,
CKSYS2_CLK_CFG_0, CKSYS2_CLK_CFG_0_SET, CKSYS2_CLK_CFG_0_CLR,
MM_HWV_CG_30_DONE, MM_HWV_CG_30_SET, MM_HWV_CG_30_CLR,
0, 4, 7, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_SENINF0_SHIFT,
CKSYS2_CLK_FENC_STATUS_MON_0, 31),
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_SENINF1, "seninf1", seninf_parents,
CKSYS2_CLK_CFG_0, CKSYS2_CLK_CFG_0_SET, CKSYS2_CLK_CFG_0_CLR,
MM_HWV_CG_30_DONE, MM_HWV_CG_30_SET, MM_HWV_CG_30_CLR,
8, 4, 15, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_SENINF1_SHIFT,
CKSYS2_CLK_FENC_STATUS_MON_0, 30),
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_SENINF2, "seninf2", seninf_parents,
CKSYS2_CLK_CFG_0, CKSYS2_CLK_CFG_0_SET, CKSYS2_CLK_CFG_0_CLR,
MM_HWV_CG_30_DONE, MM_HWV_CG_30_SET, MM_HWV_CG_30_CLR,
16, 4, 23, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_SENINF2_SHIFT,
CKSYS2_CLK_FENC_STATUS_MON_0, 29),
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_SENINF3, "seninf3", seninf_parents,
CKSYS2_CLK_CFG_0, CKSYS2_CLK_CFG_0_SET, CKSYS2_CLK_CFG_0_CLR,
MM_HWV_CG_30_DONE, MM_HWV_CG_30_SET, MM_HWV_CG_30_CLR,
24, 4, 31, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_SENINF3_SHIFT,
CKSYS2_CLK_FENC_STATUS_MON_0, 28),
/* CKSYS2_CLK_CFG_1 */
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_SENINF4, "seninf4", seninf_parents,
CKSYS2_CLK_CFG_1, CKSYS2_CLK_CFG_1_SET, CKSYS2_CLK_CFG_1_CLR,
MM_HWV_CG_31_DONE, MM_HWV_CG_31_SET, MM_HWV_CG_31_CLR,
0, 4, 7, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_SENINF4_SHIFT,
CKSYS2_CLK_FENC_STATUS_MON_0, 27),
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_SENINF5, "seninf5", seninf_parents,
CKSYS2_CLK_CFG_1, CKSYS2_CLK_CFG_1_SET, CKSYS2_CLK_CFG_1_CLR,
MM_HWV_CG_31_DONE, MM_HWV_CG_31_SET, MM_HWV_CG_31_CLR,
8, 4, 15, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_SENINF5_SHIFT,
CKSYS2_CLK_FENC_STATUS_MON_0, 26),
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_IMG1, "img1", img1_parents,
CKSYS2_CLK_CFG_1, CKSYS2_CLK_CFG_1_SET, CKSYS2_CLK_CFG_1_CLR,
MM_HWV_CG_31_DONE, MM_HWV_CG_31_SET, MM_HWV_CG_31_CLR,
16, 4, 23, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_IMG1_SHIFT,
CKSYS2_CLK_FENC_STATUS_MON_0, 25),
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_IPE, "ipe", ipe_parents,
CKSYS2_CLK_CFG_1, CKSYS2_CLK_CFG_1_SET, CKSYS2_CLK_CFG_1_CLR,
MM_HWV_CG_31_DONE, MM_HWV_CG_31_SET, MM_HWV_CG_31_CLR,
24, 4, 31, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_IPE_SHIFT,
CKSYS2_CLK_FENC_STATUS_MON_0, 24),
/* CKSYS2_CLK_CFG_2 */
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_CAM, "cam", cam_parents,
CKSYS2_CLK_CFG_2, CKSYS2_CLK_CFG_2_SET, CKSYS2_CLK_CFG_2_CLR,
MM_HWV_CG_32_DONE, MM_HWV_CG_32_SET, MM_HWV_CG_32_CLR,
0, 4, 7, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_CAM_SHIFT,
CKSYS2_CLK_FENC_STATUS_MON_0, 23),
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_CAMTM, "camtm", camtm_parents,
CKSYS2_CLK_CFG_2, CKSYS2_CLK_CFG_2_SET, CKSYS2_CLK_CFG_2_CLR,
MM_HWV_CG_32_DONE, MM_HWV_CG_32_SET, MM_HWV_CG_32_CLR,
8, 3, 15, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_CAMTM_SHIFT,
CKSYS2_CLK_FENC_STATUS_MON_0, 22),
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_DPE, "dpe", dpe_parents,
CKSYS2_CLK_CFG_2, CKSYS2_CLK_CFG_2_SET, CKSYS2_CLK_CFG_2_CLR,
MM_HWV_CG_32_DONE, MM_HWV_CG_32_SET, MM_HWV_CG_32_CLR,
16, 4, 23, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_DPE_SHIFT,
CKSYS2_CLK_FENC_STATUS_MON_0, 21),
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_VDEC, "vdec", vdec_parents,
CKSYS2_CLK_CFG_2, CKSYS2_CLK_CFG_2_SET, CKSYS2_CLK_CFG_2_CLR,
MM_HWV_CG_32_DONE, MM_HWV_CG_32_SET, MM_HWV_CG_32_CLR,
24, 4, 31, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_VDEC_SHIFT,
CKSYS2_CLK_FENC_STATUS_MON_0, 20),
/* CKSYS2_CLK_CFG_3 */
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_CCUSYS, "ccusys", ccusys_parents,
CKSYS2_CLK_CFG_3, CKSYS2_CLK_CFG_3_SET, CKSYS2_CLK_CFG_3_CLR,
MM_HWV_CG_33_DONE, MM_HWV_CG_33_SET, MM_HWV_CG_33_CLR,
0, 4, 7, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_CCUSYS_SHIFT,
CKSYS2_CLK_FENC_STATUS_MON_0, 19),
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_CCUTM, "ccutm", ccutm_parents,
CKSYS2_CLK_CFG_3, CKSYS2_CLK_CFG_3_SET, CKSYS2_CLK_CFG_3_CLR,
MM_HWV_CG_33_DONE, MM_HWV_CG_33_SET, MM_HWV_CG_33_CLR,
8, 3, 15, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_CCUTM_SHIFT,
CKSYS2_CLK_FENC_STATUS_MON_0, 18),
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_VENC, "venc", venc_parents,
CKSYS2_CLK_CFG_3, CKSYS2_CLK_CFG_3_SET, CKSYS2_CLK_CFG_3_CLR,
MM_HWV_CG_33_DONE, MM_HWV_CG_33_SET, MM_HWV_CG_33_CLR,
16, 4, 23, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_VENC_SHIFT,
CKSYS2_CLK_FENC_STATUS_MON_0, 17),
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP2_DVO, "dvo", dvo_parents,
CKSYS2_CLK_CFG_3, CKSYS2_CLK_CFG_3_SET, CKSYS2_CLK_CFG_3_CLR,
24, 3, 31, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_DVO_SHIFT,
CKSYS2_CLK_FENC_STATUS_MON_0, 16),
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP2_DVO_FAVT, "dvo_favt", dvo_favt_parents,
CKSYS2_CLK_CFG_4, CKSYS2_CLK_CFG_4_SET, CKSYS2_CLK_CFG_4_CLR,
0, 3, 7, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_DVO_FAVT_SHIFT,
CKSYS2_CLK_FENC_STATUS_MON_0, 15),
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP2_DP1, "dp1", dp1_parents,
CKSYS2_CLK_CFG_4, CKSYS2_CLK_CFG_4_SET, CKSYS2_CLK_CFG_4_CLR,
8, 3, 15, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_DP1_SHIFT,
CKSYS2_CLK_FENC_STATUS_MON_0, 14),
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP2_DP0, "dp0", dp0_parents,
CKSYS2_CLK_CFG_4, CKSYS2_CLK_CFG_4_SET, CKSYS2_CLK_CFG_4_CLR,
16, 3, 23, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_DP0_SHIFT,
CKSYS2_CLK_FENC_STATUS_MON_0, 13),
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_DISP, "disp", disp_parents,
CKSYS2_CLK_CFG_4, CKSYS2_CLK_CFG_4_SET, CKSYS2_CLK_CFG_4_CLR,
MM_HWV_CG_34_DONE, MM_HWV_CG_34_SET, MM_HWV_CG_34_CLR,
24, 4, 31, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_DISP_SHIFT,
CKSYS2_CLK_FENC_STATUS_MON_0, 12),
/* CKSYS2_CLK_CFG_5 */
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_MDP, "mdp", mdp_parents,
CKSYS2_CLK_CFG_5, CKSYS2_CLK_CFG_5_SET, CKSYS2_CLK_CFG_5_CLR,
MM_HWV_CG_35_DONE, MM_HWV_CG_35_SET, MM_HWV_CG_35_CLR,
0, 4, 7, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_MDP_SHIFT,
CKSYS2_CLK_FENC_STATUS_MON_0, 11),
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_MMINFRA, "mminfra", mminfra_parents,
CKSYS2_CLK_CFG_5, CKSYS2_CLK_CFG_5_SET, CKSYS2_CLK_CFG_5_CLR,
MM_HWV_CG_35_DONE, MM_HWV_CG_35_SET, MM_HWV_CG_35_CLR,
8, 4, 15, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_MMINFRA_SHIFT,
CKSYS2_CLK_FENC_STATUS_MON_0, 10),
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_MMINFRA_SNOC, "mminfra_snoc", mminfra_snoc_parents,
CKSYS2_CLK_CFG_5, CKSYS2_CLK_CFG_5_SET, CKSYS2_CLK_CFG_5_CLR,
MM_HWV_CG_35_DONE, MM_HWV_CG_35_SET, MM_HWV_CG_35_CLR,
16, 4, 23, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_MMINFRA_SNOC_SHIFT,
CKSYS2_CLK_FENC_STATUS_MON_0, 9),
MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP2_MMUP, "mmup", mmup_parents,
CKSYS2_CLK_CFG_5, CKSYS2_CLK_CFG_5_SET, CKSYS2_CLK_CFG_5_CLR,
24, 3, 31, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_MMUP_SHIFT,
CKSYS2_CLK_FENC_STATUS_MON_0, 8),
/* CKSYS2_CLK_CFG_6 */
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_MMINFRA_AO, "mminfra_ao", mminfra_ao_parents,
CKSYS2_CLK_CFG_6, CKSYS2_CLK_CFG_6_SET, CKSYS2_CLK_CFG_6_CLR,
MM_HWV_CG_36_DONE, MM_HWV_CG_36_SET, MM_HWV_CG_36_CLR,
16, 2, 7, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_MMINFRA_AO_SHIFT,
CKSYS2_CLK_FENC_STATUS_MON_0, 5),
};
static const struct mtk_clk_desc topck_desc = {
.factor_clks = top_divs,
.num_factor_clks = ARRAY_SIZE(top_divs),
.mux_clks = top_muxes,
.num_mux_clks = ARRAY_SIZE(top_muxes),
};
static const struct of_device_id of_match_clk_mt8196_ck[] = {
{ .compatible = "mediatek,mt8196-topckgen-gp2", .data = &topck_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_ck);
static struct platform_driver clk_mt8196_topck_drv = {
.probe = mtk_clk_simple_probe,
.remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8196-topck2",
.of_match_table = of_match_clk_mt8196_ck,
},
};
MODULE_DESCRIPTION("MediaTek MT8196 GP2 top clock generators driver");
module_platform_driver(clk_mt8196_topck_drv);
MODULE_LICENSE("GPL");

108
drivers/clk/mediatek/clk-mt8196-ufs_ao.c Normal file
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@ -0,0 +1,108 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2025 MediaTek Inc.
* Guangjie Song <guangjie.song@mediatek.com>
* Copyright (c) 2025 Collabora Ltd.
* Laura Nao <laura.nao@collabora.com>
*/
#include <dt-bindings/clock/mediatek,mt8196-clock.h>
#include <dt-bindings/reset/mediatek,mt8196-resets.h>
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
#define MT8196_UFSAO_RST0_SET_OFFSET 0x48
#define MT8196_UFSAO_RST1_SET_OFFSET 0x148
static const struct mtk_gate_regs ufsao0_cg_regs = {
.set_ofs = 0x108,
.clr_ofs = 0x10c,
.sta_ofs = 0x104,
};
static const struct mtk_gate_regs ufsao1_cg_regs = {
.set_ofs = 0x8,
.clr_ofs = 0xc,
.sta_ofs = 0x4,
};
#define GATE_UFSAO0(_id, _name, _parent, _shift) { \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &ufsao0_cg_regs, \
.shift = _shift, \
.ops = &mtk_clk_gate_ops_setclr, \
}
#define GATE_UFSAO1(_id, _name, _parent, _shift) { \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &ufsao1_cg_regs, \
.shift = _shift, \
.ops = &mtk_clk_gate_ops_setclr, \
}
static const struct mtk_gate ufsao_clks[] = {
/* UFSAO0 */
GATE_UFSAO0(CLK_UFSAO_UFSHCI_UFS, "ufsao_ufshci_ufs", "ufs", 0),
GATE_UFSAO0(CLK_UFSAO_UFSHCI_AES, "ufsao_ufshci_aes", "aes_ufsfde", 1),
/* UFSAO1 */
GATE_UFSAO1(CLK_UFSAO_UNIPRO_TX_SYM, "ufsao_unipro_tx_sym", "clk26m", 0),
GATE_UFSAO1(CLK_UFSAO_UNIPRO_RX_SYM0, "ufsao_unipro_rx_sym0", "clk26m", 1),
GATE_UFSAO1(CLK_UFSAO_UNIPRO_RX_SYM1, "ufsao_unipro_rx_sym1", "clk26m", 2),
GATE_UFSAO1(CLK_UFSAO_UNIPRO_SYS, "ufsao_unipro_sys", "ufs", 3),
GATE_UFSAO1(CLK_UFSAO_UNIPRO_SAP, "ufsao_unipro_sap", "clk26m", 4),
GATE_UFSAO1(CLK_UFSAO_PHY_SAP, "ufsao_phy_sap", "clk26m", 8),
};
static u16 ufsao_rst_ofs[] = {
MT8196_UFSAO_RST0_SET_OFFSET,
MT8196_UFSAO_RST1_SET_OFFSET
};
static u16 ufsao_rst_idx_map[] = {
[MT8196_UFSAO_RST0_UFS_MPHY] = 8,
[MT8196_UFSAO_RST1_UFS_UNIPRO] = 1 * RST_NR_PER_BANK + 0,
[MT8196_UFSAO_RST1_UFS_CRYPTO] = 1 * RST_NR_PER_BANK + 1,
[MT8196_UFSAO_RST1_UFSHCI] = 1 * RST_NR_PER_BANK + 2,
};
static const struct mtk_clk_rst_desc ufsao_rst_desc = {
.version = MTK_RST_SET_CLR,
.rst_bank_ofs = ufsao_rst_ofs,
.rst_bank_nr = ARRAY_SIZE(ufsao_rst_ofs),
.rst_idx_map = ufsao_rst_idx_map,
.rst_idx_map_nr = ARRAY_SIZE(ufsao_rst_idx_map),
};
static const struct mtk_clk_desc ufsao_mcd = {
.clks = ufsao_clks,
.num_clks = ARRAY_SIZE(ufsao_clks),
.rst_desc = &ufsao_rst_desc,
};
static const struct of_device_id of_match_clk_mt8196_ufs_ao[] = {
{ .compatible = "mediatek,mt8196-ufscfg-ao", .data = &ufsao_mcd },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_ufs_ao);
static struct platform_driver clk_mt8196_ufs_ao_drv = {
.probe = mtk_clk_simple_probe,
.remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8196-ufs-ao",
.of_match_table = of_match_clk_mt8196_ufs_ao,
},
};
module_platform_driver(clk_mt8196_ufs_ao_drv);
MODULE_DESCRIPTION("MediaTek MT8196 ufs_ao clocks driver");
MODULE_LICENSE("GPL");

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drivers/clk/mediatek/clk-mt8196-vdec.c Normal file
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2025 MediaTek Inc.
* Guangjie Song <guangjie.song@mediatek.com>
* Copyright (c) 2025 Collabora Ltd.
* Laura Nao <laura.nao@collabora.com>
*/
#include <dt-bindings/clock/mediatek,mt8196-clock.h>
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
static const struct mtk_gate_regs vde20_cg_regs = {
.set_ofs = 0x0,
.clr_ofs = 0x4,
.sta_ofs = 0x0,
};
static const struct mtk_gate_regs vde20_hwv_regs = {
.set_ofs = 0x0088,
.clr_ofs = 0x008c,
.sta_ofs = 0x2c44,
};
static const struct mtk_gate_regs vde21_cg_regs = {
.set_ofs = 0x200,
.clr_ofs = 0x204,
.sta_ofs = 0x200,
};
static const struct mtk_gate_regs vde21_hwv_regs = {
.set_ofs = 0x0080,
.clr_ofs = 0x0084,
.sta_ofs = 0x2c40,
};
static const struct mtk_gate_regs vde22_cg_regs = {
.set_ofs = 0x8,
.clr_ofs = 0xc,
.sta_ofs = 0x8,
};
static const struct mtk_gate_regs vde22_hwv_regs = {
.set_ofs = 0x0078,
.clr_ofs = 0x007c,
.sta_ofs = 0x2c3c,
};
#define GATE_HWV_VDE20(_id, _name, _parent, _shift) { \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &vde20_cg_regs, \
.hwv_regs = &vde20_hwv_regs, \
.shift = _shift, \
.ops = &mtk_clk_gate_hwv_ops_setclr_inv,\
.flags = CLK_OPS_PARENT_ENABLE, \
}
#define GATE_HWV_VDE21(_id, _name, _parent, _shift) { \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &vde21_cg_regs, \
.hwv_regs = &vde21_hwv_regs, \
.shift = _shift, \
.ops = &mtk_clk_gate_hwv_ops_setclr_inv,\
.flags = CLK_OPS_PARENT_ENABLE, \
}
#define GATE_HWV_VDE22(_id, _name, _parent, _shift) { \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &vde22_cg_regs, \
.hwv_regs = &vde22_hwv_regs, \
.shift = _shift, \
.ops = &mtk_clk_gate_hwv_ops_setclr_inv,\
.flags = CLK_OPS_PARENT_ENABLE | \
CLK_IGNORE_UNUSED, \
}
static const struct mtk_gate vde2_clks[] = {
/* VDE20 */
GATE_HWV_VDE20(CLK_VDE2_VDEC_CKEN, "vde2_vdec_cken", "vdec", 0),
GATE_HWV_VDE20(CLK_VDE2_VDEC_ACTIVE, "vde2_vdec_active", "vdec", 4),
GATE_HWV_VDE20(CLK_VDE2_VDEC_CKEN_ENG, "vde2_vdec_cken_eng", "vdec", 8),
/* VDE21 */
GATE_HWV_VDE21(CLK_VDE2_LAT_CKEN, "vde2_lat_cken", "vdec", 0),
GATE_HWV_VDE21(CLK_VDE2_LAT_ACTIVE, "vde2_lat_active", "vdec", 4),
GATE_HWV_VDE21(CLK_VDE2_LAT_CKEN_ENG, "vde2_lat_cken_eng", "vdec", 8),
/* VDE22 */
GATE_HWV_VDE22(CLK_VDE2_LARB1_CKEN, "vde2_larb1_cken", "vdec", 0),
};
static const struct mtk_clk_desc vde2_mcd = {
.clks = vde2_clks,
.num_clks = ARRAY_SIZE(vde2_clks),
.need_runtime_pm = true,
};
static const struct mtk_gate_regs vde10_hwv_regs = {
.set_ofs = 0x00a0,
.clr_ofs = 0x00a4,
.sta_ofs = 0x2c50,
};
static const struct mtk_gate_regs vde11_cg_regs = {
.set_ofs = 0x1e0,
.clr_ofs = 0x1e0,
.sta_ofs = 0x1e0,
};
static const struct mtk_gate_regs vde11_hwv_regs = {
.set_ofs = 0x00b0,
.clr_ofs = 0x00b4,
.sta_ofs = 0x2c58,
};
static const struct mtk_gate_regs vde12_cg_regs = {
.set_ofs = 0x1ec,
.clr_ofs = 0x1ec,
.sta_ofs = 0x1ec,
};
static const struct mtk_gate_regs vde12_hwv_regs = {
.set_ofs = 0x00a8,
.clr_ofs = 0x00ac,
.sta_ofs = 0x2c54,
};
static const struct mtk_gate_regs vde13_cg_regs = {
.set_ofs = 0x200,
.clr_ofs = 0x204,
.sta_ofs = 0x200,
};
static const struct mtk_gate_regs vde13_hwv_regs = {
.set_ofs = 0x0098,
.clr_ofs = 0x009c,
.sta_ofs = 0x2c4c,
};
static const struct mtk_gate_regs vde14_hwv_regs = {
.set_ofs = 0x0090,
.clr_ofs = 0x0094,
.sta_ofs = 0x2c48,
};
#define GATE_HWV_VDE10(_id, _name, _parent, _shift) { \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &vde20_cg_regs, \
.hwv_regs = &vde10_hwv_regs, \
.shift = _shift, \
.ops = &mtk_clk_gate_hwv_ops_setclr_inv,\
.flags = CLK_OPS_PARENT_ENABLE, \
}
#define GATE_HWV_VDE11(_id, _name, _parent, _shift) { \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &vde11_cg_regs, \
.hwv_regs = &vde11_hwv_regs, \
.shift = _shift, \
.ops = &mtk_clk_gate_hwv_ops_setclr_inv, \
.flags = CLK_OPS_PARENT_ENABLE, \
}
#define GATE_HWV_VDE12(_id, _name, _parent, _shift) { \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &vde12_cg_regs, \
.hwv_regs = &vde12_hwv_regs, \
.shift = _shift, \
.ops = &mtk_clk_gate_hwv_ops_setclr_inv, \
.flags = CLK_OPS_PARENT_ENABLE \
}
#define GATE_HWV_VDE13(_id, _name, _parent, _shift) { \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &vde13_cg_regs, \
.hwv_regs = &vde13_hwv_regs, \
.shift = _shift, \
.ops = &mtk_clk_gate_hwv_ops_setclr_inv,\
.flags = CLK_OPS_PARENT_ENABLE, \
}
#define GATE_HWV_VDE14(_id, _name, _parent, _shift) { \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &vde22_cg_regs, \
.hwv_regs = &vde14_hwv_regs, \
.shift = _shift, \
.ops = &mtk_clk_gate_hwv_ops_setclr_inv,\
.flags = CLK_OPS_PARENT_ENABLE | \
CLK_IGNORE_UNUSED, \
}
static const struct mtk_gate vde1_clks[] = {
/* VDE10 */
GATE_HWV_VDE10(CLK_VDE1_VDEC_CKEN, "vde1_vdec_cken", "vdec", 0),
GATE_HWV_VDE10(CLK_VDE1_VDEC_ACTIVE, "vde1_vdec_active", "vdec", 4),
GATE_HWV_VDE10(CLK_VDE1_VDEC_CKEN_ENG, "vde1_vdec_cken_eng", "vdec", 8),
/* VDE11 */
GATE_HWV_VDE11(CLK_VDE1_VDEC_SOC_IPS_EN, "vde1_vdec_soc_ips_en", "vdec", 0),
/* VDE12 */
GATE_HWV_VDE12(CLK_VDE1_VDEC_SOC_APTV_EN, "vde1_aptv_en", "ck_tck_26m_mx9_ck", 0),
GATE_HWV_VDE12(CLK_VDE1_VDEC_SOC_APTV_TOP_EN, "vde1_aptv_topen", "ck_tck_26m_mx9_ck", 1),
/* VDE13 */
GATE_HWV_VDE13(CLK_VDE1_LAT_CKEN, "vde1_lat_cken", "vdec", 0),
GATE_HWV_VDE13(CLK_VDE1_LAT_ACTIVE, "vde1_lat_active", "vdec", 4),
GATE_HWV_VDE13(CLK_VDE1_LAT_CKEN_ENG, "vde1_lat_cken_eng", "vdec", 8),
/* VDE14 */
GATE_HWV_VDE14(CLK_VDE1_LARB1_CKEN, "vde1_larb1_cken", "vdec", 0),
};
static const struct mtk_clk_desc vde1_mcd = {
.clks = vde1_clks,
.num_clks = ARRAY_SIZE(vde1_clks),
.need_runtime_pm = true,
};
static const struct of_device_id of_match_clk_mt8196_vdec[] = {
{ .compatible = "mediatek,mt8196-vdecsys", .data = &vde2_mcd },
{ .compatible = "mediatek,mt8196-vdecsys-soc", .data = &vde1_mcd },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_vdec);
static struct platform_driver clk_mt8196_vdec_drv = {
.probe = mtk_clk_simple_probe,
.remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8196-vdec",
.of_match_table = of_match_clk_mt8196_vdec,
},
};
module_platform_driver(clk_mt8196_vdec_drv);
MODULE_DESCRIPTION("MediaTek MT8196 Video Decoders clocks driver");
MODULE_LICENSE("GPL");

80
drivers/clk/mediatek/clk-mt8196-vdisp_ao.c Normal file
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2025 MediaTek Inc.
* Guangjie Song <guangjie.song@mediatek.com>
* Copyright (c) 2025 Collabora Ltd.
* Laura Nao <laura.nao@collabora.com>
*/
#include <dt-bindings/clock/mediatek,mt8196-clock.h>
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
static const struct mtk_gate_regs mm_v_cg_regs = {
.set_ofs = 0x104,
.clr_ofs = 0x108,
.sta_ofs = 0x100,
};
static const struct mtk_gate_regs mm_v_hwv_regs = {
.set_ofs = 0x0030,
.clr_ofs = 0x0034,
.sta_ofs = 0x2c18,
};
#define GATE_MM_AO_V(_id, _name, _parent, _shift) { \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &mm_v_cg_regs, \
.shift = _shift, \
.ops = &mtk_clk_gate_ops_setclr, \
.flags = CLK_OPS_PARENT_ENABLE | \
CLK_IS_CRITICAL, \
}
#define GATE_HWV_MM_V(_id, _name, _parent, _shift) { \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &mm_v_cg_regs, \
.hwv_regs = &mm_v_hwv_regs, \
.shift = _shift, \
.ops = &mtk_clk_gate_hwv_ops_setclr, \
.flags = CLK_OPS_PARENT_ENABLE, \
}
static const struct mtk_gate mm_v_clks[] = {
GATE_HWV_MM_V(CLK_MM_V_DISP_VDISP_AO_CONFIG, "mm_v_disp_vdisp_ao_config", "disp", 0),
GATE_HWV_MM_V(CLK_MM_V_DISP_DPC, "mm_v_disp_dpc", "disp", 16),
GATE_MM_AO_V(CLK_MM_V_SMI_SUB_SOMM0, "mm_v_smi_sub_somm0", "disp", 2),
};
static const struct mtk_clk_desc mm_v_mcd = {
.clks = mm_v_clks,
.num_clks = ARRAY_SIZE(mm_v_clks),
};
static const struct of_device_id of_match_clk_mt8196_vdisp_ao[] = {
{ .compatible = "mediatek,mt8196-vdisp-ao", .data = &mm_v_mcd },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_vdisp_ao);
static struct platform_driver clk_mt8196_vdisp_ao_drv = {
.probe = mtk_clk_pdev_probe,
.remove = mtk_clk_pdev_remove,
.driver = {
.name = "clk-mt8196-vdisp-ao",
.of_match_table = of_match_clk_mt8196_vdisp_ao,
},
};
module_platform_driver(clk_mt8196_vdisp_ao_drv);
MODULE_DESCRIPTION("MediaTek MT8196 vdisp_ao clocks driver");
MODULE_LICENSE("GPL");

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drivers/clk/mediatek/clk-mt8196-venc.c Normal file
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2025 MediaTek Inc.
* Guangjie Song <guangjie.song@mediatek.com>
* Copyright (c) 2025 Collabora Ltd.
* Laura Nao <laura.nao@collabora.com>
*/
#include <dt-bindings/clock/mediatek,mt8196-clock.h>
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
static const struct mtk_gate_regs ven10_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
static const struct mtk_gate_regs ven10_hwv_regs = {
.set_ofs = 0x00b8,
.clr_ofs = 0x00bc,
.sta_ofs = 0x2c5c,
};
static const struct mtk_gate_regs ven11_cg_regs = {
.set_ofs = 0x10,
.clr_ofs = 0x14,
.sta_ofs = 0x10,
};
static const struct mtk_gate_regs ven11_hwv_regs = {
.set_ofs = 0x00c0,
.clr_ofs = 0x00c4,
.sta_ofs = 0x2c60,
};
#define GATE_VEN10(_id, _name, _parent, _shift) { \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &ven10_cg_regs, \
.shift = _shift, \
.flags = CLK_OPS_PARENT_ENABLE, \
.ops = &mtk_clk_gate_ops_setclr_inv, \
}
#define GATE_HWV_VEN10_FLAGS(_id, _name, _parent, _shift, _flags) { \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &ven10_cg_regs, \
.hwv_regs = &ven10_hwv_regs, \
.shift = _shift, \
.ops = &mtk_clk_gate_hwv_ops_setclr_inv, \
.flags = (_flags) | \
CLK_OPS_PARENT_ENABLE, \
}
#define GATE_HWV_VEN10(_id, _name, _parent, _shift) \
GATE_HWV_VEN10_FLAGS(_id, _name, _parent, _shift, 0)
#define GATE_HWV_VEN11(_id, _name, _parent, _shift) { \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &ven11_cg_regs, \
.hwv_regs = &ven11_hwv_regs, \
.shift = _shift, \
.ops = &mtk_clk_gate_hwv_ops_setclr_inv,\
.flags = CLK_OPS_PARENT_ENABLE \
}
static const struct mtk_gate ven1_clks[] = {
/* VEN10 */
GATE_HWV_VEN10(CLK_VEN1_CKE0_LARB, "ven1_larb", "venc", 0),
GATE_HWV_VEN10(CLK_VEN1_CKE1_VENC, "ven1_venc", "venc", 4),
GATE_VEN10(CLK_VEN1_CKE2_JPGENC, "ven1_jpgenc", "venc", 8),
GATE_VEN10(CLK_VEN1_CKE3_JPGDEC, "ven1_jpgdec", "venc", 12),
GATE_VEN10(CLK_VEN1_CKE4_JPGDEC_C1, "ven1_jpgdec_c1", "venc", 16),
GATE_HWV_VEN10(CLK_VEN1_CKE5_GALS, "ven1_gals", "venc", 28),
GATE_HWV_VEN10(CLK_VEN1_CKE29_VENC_ADAB_CTRL, "ven1_venc_adab_ctrl",
"venc", 29),
GATE_HWV_VEN10_FLAGS(CLK_VEN1_CKE29_VENC_XPC_CTRL,
"ven1_venc_xpc_ctrl", "venc", 30,
CLK_IGNORE_UNUSED),
GATE_HWV_VEN10(CLK_VEN1_CKE6_GALS_SRAM, "ven1_gals_sram", "venc", 31),
/* VEN11 */
GATE_HWV_VEN11(CLK_VEN1_RES_FLAT, "ven1_res_flat", "venc", 0),
};
static const struct mtk_clk_desc ven1_mcd = {
.clks = ven1_clks,
.num_clks = ARRAY_SIZE(ven1_clks),
.need_runtime_pm = true,
};
static const struct mtk_gate_regs ven20_hwv_regs = {
.set_ofs = 0x00c8,
.clr_ofs = 0x00cc,
.sta_ofs = 0x2c64,
};
static const struct mtk_gate_regs ven21_hwv_regs = {
.set_ofs = 0x00d0,
.clr_ofs = 0x00d4,
.sta_ofs = 0x2c68,
};
#define GATE_VEN20(_id, _name, _parent, _shift) { \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &ven10_cg_regs, \
.shift = _shift, \
.flags = CLK_OPS_PARENT_ENABLE, \
.ops = &mtk_clk_gate_ops_setclr_inv, \
}
#define GATE_HWV_VEN20(_id, _name, _parent, _shift) { \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &ven10_cg_regs, \
.hwv_regs = &ven20_hwv_regs, \
.shift = _shift, \
.ops = &mtk_clk_gate_hwv_ops_setclr_inv,\
.flags = CLK_OPS_PARENT_ENABLE, \
}
#define GATE_HWV_VEN21(_id, _name, _parent, _shift) { \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &ven11_cg_regs, \
.hwv_regs = &ven21_hwv_regs, \
.shift = _shift, \
.ops = &mtk_clk_gate_hwv_ops_setclr, \
.flags = CLK_OPS_PARENT_ENABLE \
}
static const struct mtk_gate ven2_clks[] = {
/* VEN20 */
GATE_HWV_VEN20(CLK_VEN2_CKE0_LARB, "ven2_larb", "venc", 0),
GATE_HWV_VEN20(CLK_VEN2_CKE1_VENC, "ven2_venc", "venc", 4),
GATE_VEN20(CLK_VEN2_CKE2_JPGENC, "ven2_jpgenc", "venc", 8),
GATE_VEN20(CLK_VEN2_CKE3_JPGDEC, "ven2_jpgdec", "venc", 12),
GATE_HWV_VEN20(CLK_VEN2_CKE5_GALS, "ven2_gals", "venc", 28),
GATE_HWV_VEN20(CLK_VEN2_CKE29_VENC_XPC_CTRL, "ven2_venc_xpc_ctrl", "venc", 30),
GATE_HWV_VEN20(CLK_VEN2_CKE6_GALS_SRAM, "ven2_gals_sram", "venc", 31),
/* VEN21 */
GATE_HWV_VEN21(CLK_VEN2_RES_FLAT, "ven2_res_flat", "venc", 0),
};
static const struct mtk_clk_desc ven2_mcd = {
.clks = ven2_clks,
.num_clks = ARRAY_SIZE(ven2_clks),
.need_runtime_pm = true,
};
static const struct mtk_gate_regs ven_c20_hwv_regs = {
.set_ofs = 0x00d8,
.clr_ofs = 0x00dc,
.sta_ofs = 0x2c6c,
};
static const struct mtk_gate_regs ven_c21_hwv_regs = {
.set_ofs = 0x00e0,
.clr_ofs = 0x00e4,
.sta_ofs = 0x2c70,
};
#define GATE_HWV_VEN_C20(_id, _name, _parent, _shift) {\
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &ven10_cg_regs, \
.hwv_regs = &ven_c20_hwv_regs, \
.shift = _shift, \
.ops = &mtk_clk_gate_hwv_ops_setclr_inv,\
.flags = CLK_OPS_PARENT_ENABLE, \
}
#define GATE_HWV_VEN_C21(_id, _name, _parent, _shift) {\
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &ven11_cg_regs, \
.hwv_regs = &ven_c21_hwv_regs, \
.shift = _shift, \
.ops = &mtk_clk_gate_hwv_ops_setclr, \
.flags = CLK_OPS_PARENT_ENABLE, \
}
static const struct mtk_gate ven_c2_clks[] = {
/* VEN_C20 */
GATE_HWV_VEN_C20(CLK_VEN_C2_CKE0_LARB, "ven_c2_larb", "venc", 0),
GATE_HWV_VEN_C20(CLK_VEN_C2_CKE1_VENC, "ven_c2_venc", "venc", 4),
GATE_HWV_VEN_C20(CLK_VEN_C2_CKE5_GALS, "ven_c2_gals", "venc", 28),
GATE_HWV_VEN_C20(CLK_VEN_C2_CKE29_VENC_XPC_CTRL, "ven_c2_venc_xpc_ctrl",
"venc", 30),
GATE_HWV_VEN_C20(CLK_VEN_C2_CKE6_GALS_SRAM, "ven_c2_gals_sram", "venc", 31),
/* VEN_C21 */
GATE_HWV_VEN_C21(CLK_VEN_C2_RES_FLAT, "ven_c2_res_flat", "venc", 0),
};
static const struct mtk_clk_desc ven_c2_mcd = {
.clks = ven_c2_clks,
.num_clks = ARRAY_SIZE(ven_c2_clks),
.need_runtime_pm = true,
};
static const struct of_device_id of_match_clk_mt8196_venc[] = {
{ .compatible = "mediatek,mt8196-vencsys", .data = &ven1_mcd },
{ .compatible = "mediatek,mt8196-vencsys-c1", .data = &ven2_mcd },
{ .compatible = "mediatek,mt8196-vencsys-c2", .data = &ven_c2_mcd },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_venc);
static struct platform_driver clk_mt8196_venc_drv = {
.probe = mtk_clk_simple_probe,
.remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8196-venc",
.of_match_table = of_match_clk_mt8196_venc,
},
};
module_platform_driver(clk_mt8196_venc_drv);
MODULE_DESCRIPTION("MediaTek MT8196 Video Encoders clocks driver");
MODULE_LICENSE("GPL");

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drivers/clk/mediatek/clk-mt8196-vlpckgen.c Normal file
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2025 MediaTek Inc.
* Guangjie Song <guangjie.song@mediatek.com>
* Copyright (c) 2025 Collabora Ltd.
* Laura Nao <laura.nao@collabora.com>
*/
#include <dt-bindings/clock/mediatek,mt8196-clock.h>
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include "clk-mtk.h"
#include "clk-mux.h"
#include "clk-pll.h"
/* MUX SEL REG */
#define VLP_CLK_CFG_UPDATE 0x0004
#define VLP_CLK_CFG_UPDATE1 0x0008
#define VLP_CLK_CFG_0 0x0010
#define VLP_CLK_CFG_0_SET 0x0014
#define VLP_CLK_CFG_0_CLR 0x0018
#define VLP_CLK_CFG_1 0x0020
#define VLP_CLK_CFG_1_SET 0x0024
#define VLP_CLK_CFG_1_CLR 0x0028
#define VLP_CLK_CFG_2 0x0030
#define VLP_CLK_CFG_2_SET 0x0034
#define VLP_CLK_CFG_2_CLR 0x0038
#define VLP_CLK_CFG_3 0x0040
#define VLP_CLK_CFG_3_SET 0x0044
#define VLP_CLK_CFG_3_CLR 0x0048
#define VLP_CLK_CFG_4 0x0050
#define VLP_CLK_CFG_4_SET 0x0054
#define VLP_CLK_CFG_4_CLR 0x0058
#define VLP_CLK_CFG_5 0x0060
#define VLP_CLK_CFG_5_SET 0x0064
#define VLP_CLK_CFG_5_CLR 0x0068
#define VLP_CLK_CFG_6 0x0070
#define VLP_CLK_CFG_6_SET 0x0074
#define VLP_CLK_CFG_6_CLR 0x0078
#define VLP_CLK_CFG_7 0x0080
#define VLP_CLK_CFG_7_SET 0x0084
#define VLP_CLK_CFG_7_CLR 0x0088
#define VLP_CLK_CFG_8 0x0090
#define VLP_CLK_CFG_8_SET 0x0094
#define VLP_CLK_CFG_8_CLR 0x0098
#define VLP_CLK_CFG_9 0x00a0
#define VLP_CLK_CFG_9_SET 0x00a4
#define VLP_CLK_CFG_9_CLR 0x00a8
#define VLP_CLK_CFG_10 0x00b0
#define VLP_CLK_CFG_10_SET 0x00b4
#define VLP_CLK_CFG_10_CLR 0x00b8
#define VLP_OCIC_FENC_STATUS_MON_0 0x039c
#define VLP_OCIC_FENC_STATUS_MON_1 0x03a0
/* MUX SHIFT */
#define TOP_MUX_SCP_SHIFT 0
#define TOP_MUX_SCP_SPI_SHIFT 1
#define TOP_MUX_SCP_IIC_SHIFT 2
#define TOP_MUX_SCP_IIC_HS_SHIFT 3
#define TOP_MUX_PWRAP_ULPOSC_SHIFT 4
#define TOP_MUX_SPMI_M_TIA_32K_SHIFT 5
#define TOP_MUX_APXGPT_26M_B_SHIFT 6
#define TOP_MUX_DPSW_SHIFT 7
#define TOP_MUX_DPSW_CENTRAL_SHIFT 8
#define TOP_MUX_SPMI_M_MST_SHIFT 9
#define TOP_MUX_DVFSRC_SHIFT 10
#define TOP_MUX_PWM_VLP_SHIFT 11
#define TOP_MUX_AXI_VLP_SHIFT 12
#define TOP_MUX_SYSTIMER_26M_SHIFT 13
#define TOP_MUX_SSPM_SHIFT 14
#define TOP_MUX_SRCK_SHIFT 15
#define TOP_MUX_CAMTG0_SHIFT 16
#define TOP_MUX_CAMTG1_SHIFT 17
#define TOP_MUX_CAMTG2_SHIFT 18
#define TOP_MUX_CAMTG3_SHIFT 19
#define TOP_MUX_CAMTG4_SHIFT 20
#define TOP_MUX_CAMTG5_SHIFT 21
#define TOP_MUX_CAMTG6_SHIFT 22
#define TOP_MUX_CAMTG7_SHIFT 23
#define TOP_MUX_SSPM_26M_SHIFT 25
#define TOP_MUX_ULPOSC_SSPM_SHIFT 26
#define TOP_MUX_VLP_PBUS_26M_SHIFT 27
#define TOP_MUX_DEBUG_ERR_FLAG_VLP_26M_SHIFT 28
#define TOP_MUX_DPMSRDMA_SHIFT 29
#define TOP_MUX_VLP_PBUS_156M_SHIFT 30
#define TOP_MUX_SPM_SHIFT 0
#define TOP_MUX_MMINFRA_VLP_SHIFT 1
#define TOP_MUX_USB_TOP_SHIFT 2
#define TOP_MUX_SSUSB_XHCI_SHIFT 3
#define TOP_MUX_NOC_VLP_SHIFT 4
#define TOP_MUX_AUDIO_H_SHIFT 5
#define TOP_MUX_AUD_ENGEN1_SHIFT 6
#define TOP_MUX_AUD_ENGEN2_SHIFT 7
#define TOP_MUX_AUD_INTBUS_SHIFT 8
#define TOP_MUX_SPU_VLP_26M_SHIFT 9
#define TOP_MUX_SPU0_VLP_SHIFT 10
#define TOP_MUX_SPU1_VLP_SHIFT 11
/* CKSTA REG */
#define VLP_CKSTA_REG0 0x0250
#define VLP_CKSTA_REG1 0x0254
/* HW Voter REG */
#define HWV_CG_9_SET 0x0048
#define HWV_CG_9_CLR 0x004c
#define HWV_CG_9_DONE 0x2c24
#define HWV_CG_10_SET 0x0050
#define HWV_CG_10_CLR 0x0054
#define HWV_CG_10_DONE 0x2c28
/* PLL REG */
#define VLP_AP_PLL_CON3 0x264
#define VLP_APLL1_TUNER_CON0 0x2a4
#define VLP_APLL2_TUNER_CON0 0x2a8
#define VLP_APLL1_CON0 0x274
#define VLP_APLL1_CON1 0x278
#define VLP_APLL1_CON2 0x27c
#define VLP_APLL1_CON3 0x280
#define VLP_APLL2_CON0 0x28c
#define VLP_APLL2_CON1 0x290
#define VLP_APLL2_CON2 0x294
#define VLP_APLL2_CON3 0x298
/* vlp apll1 tuner default value*/
#define VLP_APLL1_TUNER_CON0_VALUE 0x6f28bd4d
/* vlp apll2 tuner default value + 1*/
#define VLP_APLL2_TUNER_CON0_VALUE 0x78fd5265
#define VLP_PLLEN_ALL 0x080
#define VLP_PLLEN_ALL_SET 0x084
#define VLP_PLLEN_ALL_CLR 0x088
#define MT8196_PLL_FMAX (3800UL * MHZ)
#define MT8196_PLL_FMIN (1500UL * MHZ)
#define MT8196_INTEGER_BITS 8
#define PLL_FENC(_id, _name, _reg, _fenc_sta_ofs, _fenc_sta_bit,\
_flags, _pd_reg, _pd_shift, \
_pcw_reg, _pcw_shift, _pcwbits, \
_pll_en_bit) { \
.id = _id, \
.name = _name, \
.reg = _reg, \
.fenc_sta_ofs = _fenc_sta_ofs, \
.fenc_sta_bit = _fenc_sta_bit, \
.flags = _flags, \
.fmax = MT8196_PLL_FMAX, \
.fmin = MT8196_PLL_FMIN, \
.pd_reg = _pd_reg, \
.pd_shift = _pd_shift, \
.pcw_reg = _pcw_reg, \
.pcw_shift = _pcw_shift, \
.pcwbits = _pcwbits, \
.pcwibits = MT8196_INTEGER_BITS, \
.en_reg = VLP_PLLEN_ALL, \
.en_set_reg = VLP_PLLEN_ALL_SET, \
.en_clr_reg = VLP_PLLEN_ALL_CLR, \
.pll_en_bit = _pll_en_bit, \
.ops = &mtk_pll_fenc_clr_set_ops, \
}
static DEFINE_SPINLOCK(mt8196_clk_vlp_lock);
static const struct mtk_fixed_factor vlp_divs[] = {
FACTOR(CLK_VLP_CLK26M, "vlp_clk26m", "clk26m", 1, 1),
FACTOR(CLK_VLP_APLL1_D4, "apll1_d4", "vlp_apll1", 1, 4),
FACTOR(CLK_VLP_APLL1_D8, "apll1_d8", "vlp_apll1", 1, 8),
FACTOR(CLK_VLP_APLL2_D4, "apll2_d4", "vlp_apll2", 1, 4),
FACTOR(CLK_VLP_APLL2_D8, "apll2_d8", "vlp_apll2", 1, 8),
};
static const char * const vlp_scp_parents[] = {
"clk26m",
"osc_d20",
"mainpll_d6",
"mainpll_d4",
"mainpll_d3",
"vlp_apll1"
};
static const char * const vlp_scp_spi_parents[] = {
"clk26m",
"osc_d20",
"mainpll_d7_d2",
"mainpll_d5_d2"
};
static const char * const vlp_scp_iic_parents[] = {
"clk26m",
"osc_d20",
"mainpll_d5_d4",
"mainpll_d7_d2"
};
static const char * const vlp_scp_iic_hs_parents[] = {
"clk26m",
"osc_d20",
"mainpll_d5_d4",
"mainpll_d7_d2",
"mainpll_d7"
};
static const char * const vlp_pwrap_ulposc_parents[] = {
"clk26m",
"osc_d20",
"osc_d14",
"osc_d10"
};
static const char * const vlp_spmi_32k_parents[] = {
"clk26m",
"clk32k",
"osc_d20",
"osc_d14",
"osc_d10"
};
static const char * const vlp_apxgpt_26m_b_parents[] = {
"clk26m",
"osc_d20"
};
static const char * const vlp_dpsw_parents[] = {
"clk26m",
"osc_d10",
"osc_d7",
"mainpll_d7_d4"
};
static const char * const vlp_dpsw_central_parents[] = {
"clk26m",
"osc_d10",
"osc_d7",
"mainpll_d7_d4"
};
static const char * const vlp_spmi_m_parents[] = {
"clk26m",
"osc_d20",
"osc_d14",
"osc_d10"
};
static const char * const vlp_dvfsrc_parents[] = {
"clk26m",
"osc_d20"
};
static const char * const vlp_pwm_vlp_parents[] = {
"clk26m",
"clk32k",
"osc_d20",
"osc_d8",
"mainpll_d4_d8"
};
static const char * const vlp_axi_vlp_parents[] = {
"clk26m",
"osc_d20",
"mainpll_d7_d4",
"osc_d4",
"mainpll_d7_d2"
};
static const char * const vlp_systimer_26m_parents[] = {
"clk26m",
"osc_d20"
};
static const char * const vlp_sspm_parents[] = {
"clk26m",
"osc_d20",
"mainpll_d5_d2",
"osc_d2",
"mainpll_d6"
};
static const char * const vlp_srck_parents[] = {
"clk26m",
"osc_d20"
};
static const char * const vlp_camtg0_1_parents[] = {
"clk26m",
"univpll_192m_d32",
"univpll_192m_d16",
"clk13m",
"osc_d40",
"osc_d32",
"univpll_192m_d10",
"univpll_192m_d8",
"univpll_d6_d16",
"ulposc3",
"osc_d20",
"ck2_tvdpll1_d16",
"univpll_d6_d8"
};
static const char * const vlp_camtg2_7_parents[] = {
"clk26m",
"univpll_192m_d32",
"univpll_192m_d16",
"clk13m",
"osc_d40",
"osc_d32",
"univpll_192m_d10",
"univpll_192m_d8",
"univpll_d6_d16",
"osc_d20",
"ck2_tvdpll1_d16",
"univpll_d6_d8"
};
static const char * const vlp_sspm_26m_parents[] = {
"clk26m",
"osc_d20"
};
static const char * const vlp_ulposc_sspm_parents[] = {
"clk26m",
"osc_d2",
"mainpll_d4_d2"
};
static const char * const vlp_vlp_pbus_26m_parents[] = {
"clk26m",
"osc_d20"
};
static const char * const vlp_debug_err_flag_parents[] = {
"clk26m",
"osc_d20"
};
static const char * const vlp_dpmsrdma_parents[] = {
"clk26m",
"mainpll_d7_d2"
};
static const char * const vlp_vlp_pbus_156m_parents[] = {
"clk26m",
"osc_d2",
"mainpll_d7_d2",
"mainpll_d7"
};
static const char * const vlp_spm_parents[] = {
"clk26m",
"mainpll_d7_d4"
};
static const char * const vlp_mminfra_parents[] = {
"clk26m",
"osc_d4",
"mainpll_d3"
};
static const char * const vlp_usb_parents[] = {
"clk26m",
"mainpll_d9"
};
static const char * const vlp_noc_vlp_parents[] = {
"clk26m",
"osc_d20",
"mainpll_d9"
};
static const char * const vlp_audio_h_parents[] = {
"vlp_clk26m",
"vlp_apll1",
"vlp_apll2"
};
static const char * const vlp_aud_engen1_parents[] = {
"vlp_clk26m",
"apll1_d8",
"apll1_d4"
};
static const char * const vlp_aud_engen2_parents[] = {
"vlp_clk26m",
"apll2_d8",
"apll2_d4"
};
static const char * const vlp_aud_intbus_parents[] = {
"vlp_clk26m",
"mainpll_d7_d4",
"mainpll_d4_d4"
};
static const u8 vlp_aud_parent_index[] = { 1, 2, 3 };
static const char * const vlp_spvlp_26m_parents[] = {
"clk26m",
"osc_d20"
};
static const char * const vlp_spu0_vlp_parents[] = {
"clk26m",
"osc_d20",
"mainpll_d4_d4",
"mainpll_d4_d2",
"mainpll_d7",
"mainpll_d6",
"mainpll_d5"
};
static const char * const vlp_spu1_vlp_parents[] = {
"clk26m",
"osc_d20",
"mainpll_d4_d4",
"mainpll_d4_d2",
"mainpll_d7",
"mainpll_d6",
"mainpll_d5"
};
static const struct mtk_mux vlp_muxes[] = {
/* VLP_CLK_CFG_0 */
MUX_GATE_FENC_CLR_SET_UPD(CLK_VLP_SCP, "vlp_scp", vlp_scp_parents,
VLP_CLK_CFG_0, VLP_CLK_CFG_0_SET, VLP_CLK_CFG_0_CLR,
0, 3, 7, VLP_CLK_CFG_UPDATE, TOP_MUX_SCP_SHIFT,
VLP_OCIC_FENC_STATUS_MON_0, 31),
MUX_CLR_SET_UPD(CLK_VLP_SCP_SPI, "vlp_scp_spi",
vlp_scp_spi_parents, VLP_CLK_CFG_0, VLP_CLK_CFG_0_SET,
VLP_CLK_CFG_0_CLR, 8, 2,
VLP_CLK_CFG_UPDATE, TOP_MUX_SCP_SPI_SHIFT),
MUX_CLR_SET_UPD(CLK_VLP_SCP_IIC, "vlp_scp_iic",
vlp_scp_iic_parents, VLP_CLK_CFG_0, VLP_CLK_CFG_0_SET,
VLP_CLK_CFG_0_CLR, 16, 2,
VLP_CLK_CFG_UPDATE, TOP_MUX_SCP_IIC_SHIFT),
MUX_CLR_SET_UPD(CLK_VLP_SCP_IIC_HS, "vlp_scp_iic_hs",
vlp_scp_iic_hs_parents, VLP_CLK_CFG_0, VLP_CLK_CFG_0_SET,
VLP_CLK_CFG_0_CLR, 24, 3,
VLP_CLK_CFG_UPDATE, TOP_MUX_SCP_IIC_HS_SHIFT),
/* VLP_CLK_CFG_1 */
MUX_CLR_SET_UPD(CLK_VLP_PWRAP_ULPOSC, "vlp_pwrap_ulposc",
vlp_pwrap_ulposc_parents, VLP_CLK_CFG_1, VLP_CLK_CFG_1_SET,
VLP_CLK_CFG_1_CLR, 0, 2,
VLP_CLK_CFG_UPDATE, TOP_MUX_PWRAP_ULPOSC_SHIFT),
MUX_CLR_SET_UPD(CLK_VLP_SPMI_M_TIA_32K, "vlp_spmi_32k",
vlp_spmi_32k_parents, VLP_CLK_CFG_1, VLP_CLK_CFG_1_SET,
VLP_CLK_CFG_1_CLR, 8, 3,
VLP_CLK_CFG_UPDATE, TOP_MUX_SPMI_M_TIA_32K_SHIFT),
MUX_CLR_SET_UPD(CLK_VLP_APXGPT_26M_B, "vlp_apxgpt_26m_b",
vlp_apxgpt_26m_b_parents, VLP_CLK_CFG_1, VLP_CLK_CFG_1_SET,
VLP_CLK_CFG_1_CLR, 16, 1,
VLP_CLK_CFG_UPDATE, TOP_MUX_APXGPT_26M_B_SHIFT),
MUX_CLR_SET_UPD(CLK_VLP_DPSW, "vlp_dpsw",
vlp_dpsw_parents, VLP_CLK_CFG_1, VLP_CLK_CFG_1_SET,
VLP_CLK_CFG_1_CLR, 24, 2,
VLP_CLK_CFG_UPDATE, TOP_MUX_DPSW_SHIFT),
/* VLP_CLK_CFG_2 */
MUX_CLR_SET_UPD(CLK_VLP_DPSW_CENTRAL, "vlp_dpsw_central",
vlp_dpsw_central_parents, VLP_CLK_CFG_2, VLP_CLK_CFG_2_SET,
VLP_CLK_CFG_2_CLR, 0, 2,
VLP_CLK_CFG_UPDATE, TOP_MUX_DPSW_CENTRAL_SHIFT),
MUX_CLR_SET_UPD(CLK_VLP_SPMI_M_MST, "vlp_spmi_m",
vlp_spmi_m_parents, VLP_CLK_CFG_2, VLP_CLK_CFG_2_SET,
VLP_CLK_CFG_2_CLR, 8, 2,
VLP_CLK_CFG_UPDATE, TOP_MUX_SPMI_M_MST_SHIFT),
MUX_CLR_SET_UPD(CLK_VLP_DVFSRC, "vlp_dvfsrc",
vlp_dvfsrc_parents, VLP_CLK_CFG_2, VLP_CLK_CFG_2_SET,
VLP_CLK_CFG_2_CLR, 16, 1,
VLP_CLK_CFG_UPDATE, TOP_MUX_DVFSRC_SHIFT),
MUX_GATE_FENC_CLR_SET_UPD(CLK_VLP_PWM_VLP, "vlp_pwm_vlp", vlp_pwm_vlp_parents,
VLP_CLK_CFG_2, VLP_CLK_CFG_2_SET, VLP_CLK_CFG_2_CLR,
24, 3, 31, VLP_CLK_CFG_UPDATE, TOP_MUX_PWM_VLP_SHIFT,
VLP_OCIC_FENC_STATUS_MON_0, 20),
/* VLP_CLK_CFG_3 */
MUX_CLR_SET_UPD(CLK_VLP_AXI_VLP, "vlp_axi_vlp",
vlp_axi_vlp_parents, VLP_CLK_CFG_3, VLP_CLK_CFG_3_SET,
VLP_CLK_CFG_3_CLR, 0, 3,
VLP_CLK_CFG_UPDATE, TOP_MUX_AXI_VLP_SHIFT),
MUX_CLR_SET_UPD(CLK_VLP_SYSTIMER_26M, "vlp_systimer_26m",
vlp_systimer_26m_parents, VLP_CLK_CFG_3, VLP_CLK_CFG_3_SET,
VLP_CLK_CFG_3_CLR, 8, 1,
VLP_CLK_CFG_UPDATE, TOP_MUX_SYSTIMER_26M_SHIFT),
MUX_CLR_SET_UPD(CLK_VLP_SSPM, "vlp_sspm",
vlp_sspm_parents, VLP_CLK_CFG_3, VLP_CLK_CFG_3_SET,
VLP_CLK_CFG_3_CLR, 16, 3,
VLP_CLK_CFG_UPDATE, TOP_MUX_SSPM_SHIFT),
MUX_CLR_SET_UPD(CLK_VLP_SRCK, "vlp_srck",
vlp_srck_parents, VLP_CLK_CFG_3, VLP_CLK_CFG_3_SET,
VLP_CLK_CFG_3_CLR, 24, 1,
VLP_CLK_CFG_UPDATE, TOP_MUX_SRCK_SHIFT),
/* VLP_CLK_CFG_4 */
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_VLP_CAMTG0, "vlp_camtg0", vlp_camtg0_1_parents,
VLP_CLK_CFG_4, VLP_CLK_CFG_4_SET, VLP_CLK_CFG_4_CLR,
HWV_CG_9_DONE, HWV_CG_9_SET, HWV_CG_9_CLR,
0, 4, 7, VLP_CLK_CFG_UPDATE, TOP_MUX_CAMTG0_SHIFT,
VLP_OCIC_FENC_STATUS_MON_0, 15),
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_VLP_CAMTG1, "vlp_camtg1", vlp_camtg0_1_parents,
VLP_CLK_CFG_4, VLP_CLK_CFG_4_SET, VLP_CLK_CFG_4_CLR,
HWV_CG_9_DONE, HWV_CG_9_SET, HWV_CG_9_CLR,
8, 4, 15, VLP_CLK_CFG_UPDATE, TOP_MUX_CAMTG1_SHIFT,
VLP_OCIC_FENC_STATUS_MON_0, 14),
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_VLP_CAMTG2, "vlp_camtg2", vlp_camtg2_7_parents,
VLP_CLK_CFG_4, VLP_CLK_CFG_4_SET, VLP_CLK_CFG_4_CLR,
HWV_CG_9_DONE, HWV_CG_9_SET, HWV_CG_9_CLR,
16, 4, 23, VLP_CLK_CFG_UPDATE, TOP_MUX_CAMTG2_SHIFT,
VLP_OCIC_FENC_STATUS_MON_0, 13),
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_VLP_CAMTG3, "vlp_camtg3", vlp_camtg2_7_parents,
VLP_CLK_CFG_4, VLP_CLK_CFG_4_SET, VLP_CLK_CFG_4_CLR,
HWV_CG_9_DONE, HWV_CG_9_SET, HWV_CG_9_CLR,
24, 4, 31, VLP_CLK_CFG_UPDATE, TOP_MUX_CAMTG3_SHIFT,
VLP_OCIC_FENC_STATUS_MON_0, 12),
/* VLP_CLK_CFG_5 */
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_VLP_CAMTG4, "vlp_camtg4", vlp_camtg2_7_parents,
VLP_CLK_CFG_5, VLP_CLK_CFG_5_SET, VLP_CLK_CFG_5_CLR,
HWV_CG_10_DONE, HWV_CG_10_SET, HWV_CG_10_CLR,
0, 4, 7, VLP_CLK_CFG_UPDATE, TOP_MUX_CAMTG4_SHIFT,
VLP_OCIC_FENC_STATUS_MON_0, 11),
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_VLP_CAMTG5, "vlp_camtg5", vlp_camtg2_7_parents,
VLP_CLK_CFG_5, VLP_CLK_CFG_5_SET, VLP_CLK_CFG_5_CLR,
HWV_CG_10_DONE, HWV_CG_10_SET, HWV_CG_10_CLR,
8, 4, 15, VLP_CLK_CFG_UPDATE, TOP_MUX_CAMTG5_SHIFT,
VLP_OCIC_FENC_STATUS_MON_0, 10),
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_VLP_CAMTG6, "vlp_camtg6", vlp_camtg2_7_parents,
VLP_CLK_CFG_5, VLP_CLK_CFG_5_SET, VLP_CLK_CFG_5_CLR,
HWV_CG_10_DONE, HWV_CG_10_SET, HWV_CG_10_CLR,
16, 4, 23, VLP_CLK_CFG_UPDATE, TOP_MUX_CAMTG6_SHIFT,
VLP_OCIC_FENC_STATUS_MON_0, 9),
MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_VLP_CAMTG7, "vlp_camtg7", vlp_camtg2_7_parents,
VLP_CLK_CFG_5, VLP_CLK_CFG_5_SET, VLP_CLK_CFG_5_CLR,
HWV_CG_10_DONE, HWV_CG_10_SET, HWV_CG_10_CLR,
24, 4, 31, VLP_CLK_CFG_UPDATE, TOP_MUX_CAMTG7_SHIFT,
VLP_OCIC_FENC_STATUS_MON_0, 8),
/* VLP_CLK_CFG_6 */
MUX_CLR_SET_UPD(CLK_VLP_SSPM_26M, "vlp_sspm_26m",
vlp_sspm_26m_parents, VLP_CLK_CFG_6, VLP_CLK_CFG_6_SET,
VLP_CLK_CFG_6_CLR, 8, 1,
VLP_CLK_CFG_UPDATE, TOP_MUX_SSPM_26M_SHIFT),
MUX_CLR_SET_UPD(CLK_VLP_ULPOSC_SSPM, "vlp_ulposc_sspm",
vlp_ulposc_sspm_parents, VLP_CLK_CFG_6, VLP_CLK_CFG_6_SET,
VLP_CLK_CFG_6_CLR, 16, 2,
VLP_CLK_CFG_UPDATE, TOP_MUX_ULPOSC_SSPM_SHIFT),
MUX_CLR_SET_UPD(CLK_VLP_VLP_PBUS_26M, "vlp_vlp_pbus_26m",
vlp_vlp_pbus_26m_parents, VLP_CLK_CFG_6, VLP_CLK_CFG_6_SET,
VLP_CLK_CFG_6_CLR, 24, 1,
VLP_CLK_CFG_UPDATE, TOP_MUX_VLP_PBUS_26M_SHIFT),
/* VLP_CLK_CFG_7 */
MUX_CLR_SET_UPD(CLK_VLP_DEBUG_ERR_FLAG, "vlp_debug_err_flag",
vlp_debug_err_flag_parents, VLP_CLK_CFG_7, VLP_CLK_CFG_7_SET,
VLP_CLK_CFG_7_CLR, 0, 1,
VLP_CLK_CFG_UPDATE, TOP_MUX_DEBUG_ERR_FLAG_VLP_26M_SHIFT),
MUX_CLR_SET_UPD(CLK_VLP_DPMSRDMA, "vlp_dpmsrdma",
vlp_dpmsrdma_parents, VLP_CLK_CFG_7, VLP_CLK_CFG_7_SET,
VLP_CLK_CFG_7_CLR, 8, 1,
VLP_CLK_CFG_UPDATE, TOP_MUX_DPMSRDMA_SHIFT),
MUX_CLR_SET_UPD(CLK_VLP_VLP_PBUS_156M, "vlp_vlp_pbus_156m",
vlp_vlp_pbus_156m_parents, VLP_CLK_CFG_7, VLP_CLK_CFG_7_SET,
VLP_CLK_CFG_7_CLR, 16, 2,
VLP_CLK_CFG_UPDATE, TOP_MUX_VLP_PBUS_156M_SHIFT),
MUX_CLR_SET_UPD(CLK_VLP_SPM, "vlp_spm",
vlp_spm_parents, VLP_CLK_CFG_7, VLP_CLK_CFG_7_SET,
VLP_CLK_CFG_7_CLR, 24, 1,
VLP_CLK_CFG_UPDATE1, TOP_MUX_SPM_SHIFT),
/* VLP_CLK_CFG_8 */
MUX_GATE_FENC_CLR_SET_UPD(CLK_VLP_MMINFRA, "vlp_mminfra", vlp_mminfra_parents,
VLP_CLK_CFG_8, VLP_CLK_CFG_8_SET, VLP_CLK_CFG_8_CLR,
0, 2, 7, VLP_CLK_CFG_UPDATE1, TOP_MUX_MMINFRA_VLP_SHIFT,
VLP_OCIC_FENC_STATUS_MON_1, 31),
MUX_GATE_FENC_CLR_SET_UPD(CLK_VLP_USB_TOP, "vlp_usb", vlp_usb_parents,
VLP_CLK_CFG_8, VLP_CLK_CFG_8_SET, VLP_CLK_CFG_8_CLR,
8, 1, 15, VLP_CLK_CFG_UPDATE1, TOP_MUX_USB_TOP_SHIFT,
VLP_OCIC_FENC_STATUS_MON_1, 30),
MUX_GATE_FENC_CLR_SET_UPD(CLK_VLP_USB_XHCI, "vlp_usb_xhci", vlp_usb_parents,
VLP_CLK_CFG_8, VLP_CLK_CFG_8_SET, VLP_CLK_CFG_8_CLR,
16, 1, 23, VLP_CLK_CFG_UPDATE1, TOP_MUX_SSUSB_XHCI_SHIFT,
VLP_OCIC_FENC_STATUS_MON_1, 29),
MUX_CLR_SET_UPD(CLK_VLP_NOC_VLP, "vlp_noc_vlp",
vlp_noc_vlp_parents, VLP_CLK_CFG_8, VLP_CLK_CFG_8_SET,
VLP_CLK_CFG_8_CLR, 24, 2,
VLP_CLK_CFG_UPDATE1, TOP_MUX_NOC_VLP_SHIFT),
/* VLP_CLK_CFG_9 */
MUX_GATE_FENC_CLR_SET_UPD_INDEXED(CLK_VLP_AUDIO_H, "vlp_audio_h",
vlp_audio_h_parents, vlp_aud_parent_index,
VLP_CLK_CFG_9, VLP_CLK_CFG_9_SET, VLP_CLK_CFG_9_CLR,
0, 2, 7, VLP_CLK_CFG_UPDATE1, TOP_MUX_AUDIO_H_SHIFT,
VLP_OCIC_FENC_STATUS_MON_1, 27),
MUX_GATE_FENC_CLR_SET_UPD_INDEXED(CLK_VLP_AUD_ENGEN1, "vlp_aud_engen1",
vlp_aud_engen1_parents, vlp_aud_parent_index,
VLP_CLK_CFG_9, VLP_CLK_CFG_9_SET, VLP_CLK_CFG_9_CLR,
8, 2, 15, VLP_CLK_CFG_UPDATE1, TOP_MUX_AUD_ENGEN1_SHIFT,
VLP_OCIC_FENC_STATUS_MON_1, 26),
MUX_GATE_FENC_CLR_SET_UPD_INDEXED(CLK_VLP_AUD_ENGEN2, "vlp_aud_engen2",
vlp_aud_engen2_parents, vlp_aud_parent_index,
VLP_CLK_CFG_9, VLP_CLK_CFG_9_SET, VLP_CLK_CFG_9_CLR,
16, 2, 23, VLP_CLK_CFG_UPDATE1, TOP_MUX_AUD_ENGEN2_SHIFT,
VLP_OCIC_FENC_STATUS_MON_1, 25),
MUX_GATE_FENC_CLR_SET_UPD_INDEXED(CLK_VLP_AUD_INTBUS, "vlp_aud_intbus",
vlp_aud_intbus_parents, vlp_aud_parent_index,
VLP_CLK_CFG_9, VLP_CLK_CFG_9_SET, VLP_CLK_CFG_9_CLR,
24, 2, 31, VLP_CLK_CFG_UPDATE1, TOP_MUX_AUD_INTBUS_SHIFT,
VLP_OCIC_FENC_STATUS_MON_1, 24),
/* VLP_CLK_CFG_10 */
MUX_CLR_SET_UPD(CLK_VLP_SPVLP_26M, "vlp_spvlp_26m",
vlp_spvlp_26m_parents, VLP_CLK_CFG_10, VLP_CLK_CFG_10_SET,
VLP_CLK_CFG_10_CLR, 0, 1,
VLP_CLK_CFG_UPDATE1, TOP_MUX_SPU_VLP_26M_SHIFT),
MUX_CLR_SET_UPD(CLK_VLP_SPU0_VLP, "vlp_spu0_vlp",
vlp_spu0_vlp_parents, VLP_CLK_CFG_10, VLP_CLK_CFG_10_SET,
VLP_CLK_CFG_10_CLR, 8, 3,
VLP_CLK_CFG_UPDATE1, TOP_MUX_SPU0_VLP_SHIFT),
MUX_CLR_SET_UPD(CLK_VLP_SPU1_VLP, "vlp_spu1_vlp",
vlp_spu1_vlp_parents, VLP_CLK_CFG_10, VLP_CLK_CFG_10_SET,
VLP_CLK_CFG_10_CLR, 16, 3,
VLP_CLK_CFG_UPDATE1, TOP_MUX_SPU1_VLP_SHIFT),
};
static const struct mtk_pll_data vlp_plls[] = {
PLL_FENC(CLK_VLP_APLL1, "vlp_apll1", VLP_APLL1_CON0, 0x0358, 1, 0,
VLP_APLL1_CON1, 24, VLP_APLL1_CON2, 0, 32, 0),
PLL_FENC(CLK_VLP_APLL2, "vlp_apll2", VLP_APLL2_CON0, 0x0358, 0, 0,
VLP_APLL2_CON1, 24, VLP_APLL2_CON2, 0, 32, 1),
};
static const struct regmap_config vlpckgen_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.max_register = 0x1000,
.fast_io = true,
};
static int clk_mt8196_vlp_probe(struct platform_device *pdev)
{
static void __iomem *base;
struct clk_hw_onecell_data *clk_data;
int r;
struct device_node *node = pdev->dev.of_node;
struct device *dev = &pdev->dev;
struct regmap *regmap;
clk_data = mtk_alloc_clk_data(ARRAY_SIZE(vlp_muxes) +
ARRAY_SIZE(vlp_plls) +
ARRAY_SIZE(vlp_divs));
if (!clk_data)
return -ENOMEM;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
regmap = devm_regmap_init_mmio(dev, base, &vlpckgen_regmap_config);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
r = mtk_clk_register_factors(vlp_divs, ARRAY_SIZE(vlp_divs), clk_data);
if (r)
goto free_clk_data;
r = mtk_clk_register_muxes(&pdev->dev, vlp_muxes, ARRAY_SIZE(vlp_muxes),
node, &mt8196_clk_vlp_lock, clk_data);
if (r)
goto unregister_factors;
r = mtk_clk_register_plls(node, vlp_plls, ARRAY_SIZE(vlp_plls),
clk_data);
if (r)
goto unregister_muxes;
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
goto unregister_plls;
platform_set_drvdata(pdev, clk_data);
/* Initialize APLL tuner registers */
regmap_write(regmap, VLP_APLL1_TUNER_CON0, VLP_APLL1_TUNER_CON0_VALUE);
regmap_write(regmap, VLP_APLL2_TUNER_CON0, VLP_APLL2_TUNER_CON0_VALUE);
return r;
unregister_plls:
mtk_clk_unregister_plls(vlp_plls, ARRAY_SIZE(vlp_plls), clk_data);
unregister_muxes:
mtk_clk_unregister_muxes(vlp_muxes, ARRAY_SIZE(vlp_muxes), clk_data);
unregister_factors:
mtk_clk_unregister_factors(vlp_divs, ARRAY_SIZE(vlp_divs), clk_data);
free_clk_data:
mtk_free_clk_data(clk_data);
return r;
}
static void clk_mt8196_vlp_remove(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
struct device_node *node = pdev->dev.of_node;
of_clk_del_provider(node);
mtk_clk_unregister_plls(vlp_plls, ARRAY_SIZE(vlp_plls), clk_data);
mtk_clk_unregister_muxes(vlp_muxes, ARRAY_SIZE(vlp_muxes), clk_data);
mtk_clk_unregister_factors(vlp_divs, ARRAY_SIZE(vlp_divs), clk_data);
mtk_free_clk_data(clk_data);
}
static const struct of_device_id of_match_clk_mt8196_vlp_ck[] = {
{ .compatible = "mediatek,mt8196-vlpckgen" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_vlp_ck);
static struct platform_driver clk_mt8196_vlp_drv = {
.probe = clk_mt8196_vlp_probe,
.remove = clk_mt8196_vlp_remove,
.driver = {
.name = "clk-mt8196-vlpck",
.of_match_table = of_match_clk_mt8196_vlp_ck,
},
};
MODULE_DESCRIPTION("MediaTek MT8196 VLP clock generator driver");
module_platform_driver(clk_mt8196_vlp_drv);
MODULE_LICENSE("GPL");

16
drivers/clk/mediatek/clk-mtk.c
View File

@ -685,4 +685,20 @@ void mtk_clk_simple_remove(struct platform_device *pdev)
}
EXPORT_SYMBOL_GPL(mtk_clk_simple_remove);
struct regmap *mtk_clk_get_hwv_regmap(struct device_node *node)
{
struct device_node *hwv_node;
struct regmap *regmap_hwv;
hwv_node = of_parse_phandle(node, "mediatek,hardware-voter", 0);
if (!hwv_node)
return NULL;
regmap_hwv = device_node_to_regmap(hwv_node);
of_node_put(hwv_node);
return regmap_hwv;
}
EXPORT_SYMBOL_GPL(mtk_clk_get_hwv_regmap);
MODULE_LICENSE("GPL");

22
drivers/clk/mediatek/clk-mtk.h
View File

@ -20,6 +20,8 @@
#define MHZ (1000 * 1000)
#define MTK_WAIT_HWV_DONE_US 30
struct platform_device;
/*
@ -173,6 +175,25 @@ struct mtk_composite {
.flags = 0, \
}
#define MUX_DIV_GATE(_id, _name, _parents, \
_mux_reg, _mux_shift, _mux_width, \
_div_reg, _div_shift, _div_width, \
_gate_reg, _gate_shift) { \
.id = _id, \
.name = _name, \
.parent_names = _parents, \
.num_parents = ARRAY_SIZE(_parents), \
.mux_reg = _mux_reg, \
.mux_shift = _mux_shift, \
.mux_width = _mux_width, \
.divider_reg = _div_reg, \
.divider_shift = _div_shift, \
.divider_width = _div_width, \
.gate_reg = _gate_reg, \
.gate_shift = _gate_shift, \
.flags = CLK_SET_RATE_PARENT, \
}
int mtk_clk_register_composites(struct device *dev,
const struct mtk_composite *mcs, int num,
void __iomem *base, spinlock_t *lock,
@ -245,5 +266,6 @@ int mtk_clk_pdev_probe(struct platform_device *pdev);
void mtk_clk_pdev_remove(struct platform_device *pdev);
int mtk_clk_simple_probe(struct platform_device *pdev);
void mtk_clk_simple_remove(struct platform_device *pdev);
struct regmap *mtk_clk_get_hwv_regmap(struct device_node *node);
#endif /* __DRV_CLK_MTK_H */

122
drivers/clk/mediatek/clk-mux.c
View File

@ -8,6 +8,7 @@
#include <linux/clk-provider.h>
#include <linux/compiler_types.h>
#include <linux/container_of.h>
#include <linux/dev_printk.h>
#include <linux/err.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
@ -15,11 +16,15 @@
#include <linux/spinlock.h>
#include <linux/slab.h>
#include "clk-mtk.h"
#include "clk-mux.h"
#define MTK_WAIT_FENC_DONE_US 30
struct mtk_clk_mux {
struct clk_hw hw;
struct regmap *regmap;
struct regmap *regmap_hwv;
const struct mtk_mux *data;
spinlock_t *lock;
bool reparent;
@ -30,6 +35,33 @@ static inline struct mtk_clk_mux *to_mtk_clk_mux(struct clk_hw *hw)
return container_of(hw, struct mtk_clk_mux, hw);
}
static int mtk_clk_mux_fenc_enable_setclr(struct clk_hw *hw)
{
struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
unsigned long flags;
u32 val;
int ret;
if (mux->lock)
spin_lock_irqsave(mux->lock, flags);
else
__acquire(mux->lock);
regmap_write(mux->regmap, mux->data->clr_ofs,
BIT(mux->data->gate_shift));
ret = regmap_read_poll_timeout_atomic(mux->regmap, mux->data->fenc_sta_mon_ofs,
val, val & BIT(mux->data->fenc_shift), 1,
MTK_WAIT_FENC_DONE_US);
if (mux->lock)
spin_unlock_irqrestore(mux->lock, flags);
else
__release(mux->lock);
return ret;
}
static int mtk_clk_mux_enable_setclr(struct clk_hw *hw)
{
struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
@ -70,6 +102,16 @@ static void mtk_clk_mux_disable_setclr(struct clk_hw *hw)
BIT(mux->data->gate_shift));
}
static int mtk_clk_mux_fenc_is_enabled(struct clk_hw *hw)
{
struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
u32 val;
regmap_read(mux->regmap, mux->data->fenc_sta_mon_ofs, &val);
return !!(val & BIT(mux->data->fenc_shift));
}
static int mtk_clk_mux_is_enabled(struct clk_hw *hw)
{
struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
@ -80,6 +122,41 @@ static int mtk_clk_mux_is_enabled(struct clk_hw *hw)
return (val & BIT(mux->data->gate_shift)) == 0;
}
static int mtk_clk_mux_hwv_fenc_enable(struct clk_hw *hw)
{
struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
u32 val;
int ret;
regmap_write(mux->regmap_hwv, mux->data->hwv_set_ofs,
BIT(mux->data->gate_shift));
ret = regmap_read_poll_timeout_atomic(mux->regmap_hwv, mux->data->hwv_sta_ofs,
val, val & BIT(mux->data->gate_shift), 0,
MTK_WAIT_HWV_DONE_US);
if (ret)
return ret;
ret = regmap_read_poll_timeout_atomic(mux->regmap, mux->data->fenc_sta_mon_ofs,
val, val & BIT(mux->data->fenc_shift), 1,
MTK_WAIT_FENC_DONE_US);
return ret;
}
static void mtk_clk_mux_hwv_disable(struct clk_hw *hw)
{
struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
u32 val;
regmap_write(mux->regmap_hwv, mux->data->hwv_clr_ofs,
BIT(mux->data->gate_shift));
regmap_read_poll_timeout_atomic(mux->regmap_hwv, mux->data->hwv_sta_ofs,
val, (val & BIT(mux->data->gate_shift)),
0, MTK_WAIT_HWV_DONE_US);
}
static u8 mtk_clk_mux_get_parent(struct clk_hw *hw)
{
struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
@ -146,9 +223,15 @@ static int mtk_clk_mux_set_parent_setclr_lock(struct clk_hw *hw, u8 index)
static int mtk_clk_mux_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
return clk_mux_determine_rate_flags(hw, req, 0);
}
return clk_mux_determine_rate_flags(hw, req, mux->data->flags);
static bool mtk_clk_mux_uses_hwv(const struct clk_ops *ops)
{
if (ops == &mtk_mux_gate_hwv_fenc_clr_set_upd_ops)
return true;
return false;
}
const struct clk_ops mtk_mux_clr_set_upd_ops = {
@ -168,9 +251,30 @@ const struct clk_ops mtk_mux_gate_clr_set_upd_ops = {
};
EXPORT_SYMBOL_GPL(mtk_mux_gate_clr_set_upd_ops);
const struct clk_ops mtk_mux_gate_fenc_clr_set_upd_ops = {
.enable = mtk_clk_mux_fenc_enable_setclr,
.disable = mtk_clk_mux_disable_setclr,
.is_enabled = mtk_clk_mux_fenc_is_enabled,
.get_parent = mtk_clk_mux_get_parent,
.set_parent = mtk_clk_mux_set_parent_setclr_lock,
.determine_rate = mtk_clk_mux_determine_rate,
};
EXPORT_SYMBOL_GPL(mtk_mux_gate_fenc_clr_set_upd_ops);
const struct clk_ops mtk_mux_gate_hwv_fenc_clr_set_upd_ops = {
.enable = mtk_clk_mux_hwv_fenc_enable,
.disable = mtk_clk_mux_hwv_disable,
.is_enabled = mtk_clk_mux_fenc_is_enabled,
.get_parent = mtk_clk_mux_get_parent,
.set_parent = mtk_clk_mux_set_parent_setclr_lock,
.determine_rate = mtk_clk_mux_determine_rate,
};
EXPORT_SYMBOL_GPL(mtk_mux_gate_hwv_fenc_clr_set_upd_ops);
static struct clk_hw *mtk_clk_register_mux(struct device *dev,
const struct mtk_mux *mux,
struct regmap *regmap,
struct regmap *regmap_hwv,
spinlock_t *lock)
{
struct mtk_clk_mux *clk_mux;
@ -186,8 +290,13 @@ static struct clk_hw *mtk_clk_register_mux(struct device *dev,
init.parent_names = mux->parent_names;
init.num_parents = mux->num_parents;
init.ops = mux->ops;
if (mtk_clk_mux_uses_hwv(init.ops) && !regmap_hwv)
return dev_err_ptr_probe(
dev, -ENXIO,
"regmap not found for hardware voter clocks\n");
clk_mux->regmap = regmap;
clk_mux->regmap_hwv = regmap_hwv;
clk_mux->data = mux;
clk_mux->lock = lock;
clk_mux->hw.init = &init;
@ -220,6 +329,7 @@ int mtk_clk_register_muxes(struct device *dev,
struct clk_hw_onecell_data *clk_data)
{
struct regmap *regmap;
struct regmap *regmap_hwv;
struct clk_hw *hw;
int i;
@ -229,6 +339,12 @@ int mtk_clk_register_muxes(struct device *dev,
return PTR_ERR(regmap);
}
regmap_hwv = mtk_clk_get_hwv_regmap(node);
if (IS_ERR(regmap_hwv))
return dev_err_probe(
dev, PTR_ERR(regmap_hwv),
"Cannot find hardware voter regmap for %pOF\n", node);
for (i = 0; i < num; i++) {
const struct mtk_mux *mux = &muxes[i];
@ -238,7 +354,7 @@ int mtk_clk_register_muxes(struct device *dev,
continue;
}
hw = mtk_clk_register_mux(dev, mux, regmap, lock);
hw = mtk_clk_register_mux(dev, mux, regmap, regmap_hwv, lock);
if (IS_ERR(hw)) {
pr_err("Failed to register clk %s: %pe\n", mux->name,

87
drivers/clk/mediatek/clk-mux.h
View File

@ -29,10 +29,16 @@ struct mtk_mux {
u32 clr_ofs;
u32 upd_ofs;
u32 hwv_set_ofs;
u32 hwv_clr_ofs;
u32 hwv_sta_ofs;
u32 fenc_sta_mon_ofs;
u8 mux_shift;
u8 mux_width;
u8 gate_shift;
s8 upd_shift;
u8 fenc_shift;
const struct clk_ops *ops;
signed char num_parents;
@ -77,6 +83,8 @@ struct mtk_mux {
extern const struct clk_ops mtk_mux_clr_set_upd_ops;
extern const struct clk_ops mtk_mux_gate_clr_set_upd_ops;
extern const struct clk_ops mtk_mux_gate_fenc_clr_set_upd_ops;
extern const struct clk_ops mtk_mux_gate_hwv_fenc_clr_set_upd_ops;
#define MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
_mux_set_ofs, _mux_clr_ofs, _shift, _width, \
@ -118,6 +126,85 @@ extern const struct clk_ops mtk_mux_gate_clr_set_upd_ops;
0, _upd_ofs, _upd, CLK_SET_RATE_PARENT, \
mtk_mux_clr_set_upd_ops)
#define MUX_GATE_HWV_FENC_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
_mux_ofs, _mux_set_ofs, _mux_clr_ofs, \
_hwv_sta_ofs, _hwv_set_ofs, _hwv_clr_ofs, \
_shift, _width, _gate, _upd_ofs, _upd, \
_fenc_sta_mon_ofs, _fenc, _flags) { \
.id = _id, \
.name = _name, \
.mux_ofs = _mux_ofs, \
.set_ofs = _mux_set_ofs, \
.clr_ofs = _mux_clr_ofs, \
.hwv_sta_ofs = _hwv_sta_ofs, \
.hwv_set_ofs = _hwv_set_ofs, \
.hwv_clr_ofs = _hwv_clr_ofs, \
.upd_ofs = _upd_ofs, \
.fenc_sta_mon_ofs = _fenc_sta_mon_ofs, \
.mux_shift = _shift, \
.mux_width = _width, \
.gate_shift = _gate, \
.upd_shift = _upd, \
.fenc_shift = _fenc, \
.parent_names = _parents, \
.num_parents = ARRAY_SIZE(_parents), \
.flags = _flags, \
.ops = &mtk_mux_gate_hwv_fenc_clr_set_upd_ops, \
}
#define MUX_GATE_HWV_FENC_CLR_SET_UPD(_id, _name, _parents, \
_mux_ofs, _mux_set_ofs, _mux_clr_ofs, \
_hwv_sta_ofs, _hwv_set_ofs, _hwv_clr_ofs, \
_shift, _width, _gate, _upd_ofs, _upd, \
_fenc_sta_mon_ofs, _fenc) \
MUX_GATE_HWV_FENC_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
_mux_ofs, _mux_set_ofs, _mux_clr_ofs, \
_hwv_sta_ofs, _hwv_set_ofs, _hwv_clr_ofs, \
_shift, _width, _gate, _upd_ofs, _upd, \
_fenc_sta_mon_ofs, _fenc, 0)
#define MUX_GATE_FENC_CLR_SET_UPD_FLAGS(_id, _name, _parents, _paridx, \
_num_parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \
_shift, _width, _gate, _upd_ofs, _upd, \
_fenc_sta_mon_ofs, _fenc, _flags) { \
.id = _id, \
.name = _name, \
.mux_ofs = _mux_ofs, \
.set_ofs = _mux_set_ofs, \
.clr_ofs = _mux_clr_ofs, \
.upd_ofs = _upd_ofs, \
.fenc_sta_mon_ofs = _fenc_sta_mon_ofs, \
.mux_shift = _shift, \
.mux_width = _width, \
.gate_shift = _gate, \
.upd_shift = _upd, \
.fenc_shift = _fenc, \
.parent_names = _parents, \
.parent_index = _paridx, \
.num_parents = _num_parents, \
.flags = _flags, \
.ops = &mtk_mux_gate_fenc_clr_set_upd_ops, \
}
#define MUX_GATE_FENC_CLR_SET_UPD(_id, _name, _parents, \
_mux_ofs, _mux_set_ofs, _mux_clr_ofs, \
_shift, _width, _gate, _upd_ofs, _upd, \
_fenc_sta_mon_ofs, _fenc) \
MUX_GATE_FENC_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
NULL, ARRAY_SIZE(_parents), _mux_ofs, \
_mux_set_ofs, _mux_clr_ofs, _shift, \
_width, _gate, _upd_ofs, _upd, \
_fenc_sta_mon_ofs, _fenc, 0)
#define MUX_GATE_FENC_CLR_SET_UPD_INDEXED(_id, _name, _parents, _paridx, \
_mux_ofs, _mux_set_ofs, _mux_clr_ofs, \
_shift, _width, _gate, _upd_ofs, _upd, \
_fenc_sta_mon_ofs, _fenc) \
MUX_GATE_FENC_CLR_SET_UPD_FLAGS(_id, _name, _parents, _paridx, \
ARRAY_SIZE(_paridx), _mux_ofs, _mux_set_ofs, \
_mux_clr_ofs, _shift, _width, _gate, _upd_ofs, _upd, \
_fenc_sta_mon_ofs, _fenc, 0)
int mtk_clk_register_muxes(struct device *dev,
const struct mtk_mux *muxes,
int num, struct device_node *node,

45
drivers/clk/mediatek/clk-pll.c
View File

@ -37,6 +37,13 @@ int mtk_pll_is_prepared(struct clk_hw *hw)
return (readl(pll->en_addr) & BIT(pll->data->pll_en_bit)) != 0;
}
static int mtk_pll_fenc_is_prepared(struct clk_hw *hw)
{
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
return !!(readl(pll->fenc_addr) & BIT(pll->data->fenc_sta_bit));
}
static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,
u32 pcw, int postdiv)
{
@ -274,6 +281,25 @@ void mtk_pll_unprepare(struct clk_hw *hw)
writel(r, pll->pwr_addr);
}
static int mtk_pll_prepare_setclr(struct clk_hw *hw)
{
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
writel(BIT(pll->data->pll_en_bit), pll->en_set_addr);
/* Wait 20us after enable for the PLL to stabilize */
udelay(20);
return 0;
}
static void mtk_pll_unprepare_setclr(struct clk_hw *hw)
{
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
writel(BIT(pll->data->pll_en_bit), pll->en_clr_addr);
}
const struct clk_ops mtk_pll_ops = {
.is_prepared = mtk_pll_is_prepared,
.prepare = mtk_pll_prepare,
@ -283,6 +309,16 @@ const struct clk_ops mtk_pll_ops = {
.set_rate = mtk_pll_set_rate,
};
const struct clk_ops mtk_pll_fenc_clr_set_ops = {
.is_prepared = mtk_pll_fenc_is_prepared,
.prepare = mtk_pll_prepare_setclr,
.unprepare = mtk_pll_unprepare_setclr,
.recalc_rate = mtk_pll_recalc_rate,
.round_rate = mtk_pll_round_rate,
.set_rate = mtk_pll_set_rate,
};
EXPORT_SYMBOL_GPL(mtk_pll_fenc_clr_set_ops);
struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll,
const struct mtk_pll_data *data,
void __iomem *base,
@ -308,9 +344,15 @@ struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll,
pll->en_addr = base + data->en_reg;
else
pll->en_addr = pll->base_addr + REG_CON0;
if (data->en_set_reg)
pll->en_set_addr = base + data->en_set_reg;
if (data->en_clr_reg)
pll->en_clr_addr = base + data->en_clr_reg;
pll->hw.init = &init;
pll->data = data;
pll->fenc_addr = base + data->fenc_sta_ofs;
init.name = data->name;
init.flags = (data->flags & PLL_AO) ? CLK_IS_CRITICAL : 0;
init.ops = pll_ops;
@ -333,12 +375,13 @@ struct clk_hw *mtk_clk_register_pll(const struct mtk_pll_data *data,
{
struct mtk_clk_pll *pll;
struct clk_hw *hw;
const struct clk_ops *pll_ops = data->ops ? data->ops : &mtk_pll_ops;
pll = kzalloc(sizeof(*pll), GFP_KERNEL);
if (!pll)
return ERR_PTR(-ENOMEM);
hw = mtk_clk_register_pll_ops(pll, data, base, &mtk_pll_ops);
hw = mtk_clk_register_pll_ops(pll, data, base, pll_ops);
if (IS_ERR(hw))
kfree(pll);

8
drivers/clk/mediatek/clk-pll.h
View File

@ -29,6 +29,7 @@ struct mtk_pll_data {
u32 reg;
u32 pwr_reg;
u32 en_mask;
u32 fenc_sta_ofs;
u32 pd_reg;
u32 tuner_reg;
u32 tuner_en_reg;
@ -47,8 +48,11 @@ struct mtk_pll_data {
const struct mtk_pll_div_table *div_table;
const char *parent_name;
u32 en_reg;
u32 en_set_reg;
u32 en_clr_reg;
u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */
u8 pcw_chg_bit;
u8 fenc_sta_bit;
};
/*
@ -68,6 +72,9 @@ struct mtk_clk_pll {
void __iomem *pcw_addr;
void __iomem *pcw_chg_addr;
void __iomem *en_addr;
void __iomem *en_set_addr;
void __iomem *en_clr_addr;
void __iomem *fenc_addr;
const struct mtk_pll_data *data;
};
@ -78,6 +85,7 @@ void mtk_clk_unregister_plls(const struct mtk_pll_data *plls, int num_plls,
struct clk_hw_onecell_data *clk_data);
extern const struct clk_ops mtk_pll_ops;
extern const struct clk_ops mtk_pll_fenc_clr_set_ops;
static inline struct mtk_clk_pll *to_mtk_clk_pll(struct clk_hw *hw)
{

10
drivers/clk/mmp/Kconfig Normal file
View File

@ -0,0 +1,10 @@
# SPDX-License-Identifier: GPL-2.0-only
config COMMON_CLK_PXA1908
bool "Clock driver for Marvell PXA1908"
depends on ARCH_MMP || COMPILE_TEST
depends on OF
default y if ARCH_MMP && ARM64
select AUXILIARY_BUS
help
This driver supports the Marvell PXA1908 SoC clocks.

5
drivers/clk/mmp/Makefile
View File

@ -11,4 +11,7 @@ obj-$(CONFIG_MACH_MMP_DT) += clk-of-pxa168.o clk-of-pxa910.o
obj-$(CONFIG_COMMON_CLK_MMP2) += clk-of-mmp2.o clk-pll.o pwr-island.o
obj-$(CONFIG_COMMON_CLK_MMP2_AUDIO) += clk-audio.o
obj-$(CONFIG_ARCH_MMP) += clk-of-pxa1928.o clk-pxa1908-apbc.o clk-pxa1908-apbcp.o clk-pxa1908-apmu.o clk-pxa1908-mpmu.o
obj-$(CONFIG_COMMON_CLK_PXA1908) += clk-pxa1908-apbc.o clk-pxa1908-apbcp.o \
clk-pxa1908-mpmu.o clk-pxa1908-apmu.o
obj-$(CONFIG_ARCH_MMP) += clk-of-pxa1928.o

7
drivers/clk/mmp/clk-pxa1908-apmu.c
View File

@ -1,4 +1,5 @@
// SPDX-License-Identifier: GPL-2.0-only
#include <linux/auxiliary_bus.h>
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
@ -85,6 +86,7 @@ static void pxa1908_axi_periph_clk_init(struct pxa1908_clk_unit *pxa_unit)
static int pxa1908_apmu_probe(struct platform_device *pdev)
{
struct pxa1908_clk_unit *pxa_unit;
struct auxiliary_device *adev;
pxa_unit = devm_kzalloc(&pdev->dev, sizeof(*pxa_unit), GFP_KERNEL);
if (!pxa_unit)
@ -94,6 +96,11 @@ static int pxa1908_apmu_probe(struct platform_device *pdev)
if (IS_ERR(pxa_unit->base))
return PTR_ERR(pxa_unit->base);
adev = devm_auxiliary_device_create(&pdev->dev, "power", NULL);
if (IS_ERR(adev))
return dev_err_probe(&pdev->dev, PTR_ERR(adev),
"Failed to register power controller\n");
mmp_clk_init(pdev->dev.of_node, &pxa_unit->unit, APMU_NR_CLKS);
pxa1908_axi_periph_clk_init(pxa_unit);

32
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
View File

@ -340,7 +340,7 @@ static int clk_wzrd_get_divisors_ver(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
u64 vco_freq, freq, diff, vcomin, vcomax;
u64 vco_freq, freq, diff, vcomin, vcomax, best_diff = -1ULL;
u32 m, d, o;
u32 mmin, mmax, dmin, dmax, omin, omax;
@ -356,22 +356,26 @@ static int clk_wzrd_get_divisors_ver(struct clk_hw *hw, unsigned long rate,
for (m = mmin; m <= mmax; m++) {
for (d = dmin; d <= dmax; d++) {
vco_freq = DIV_ROUND_CLOSEST((parent_rate * m), d);
if (vco_freq >= vcomin && vco_freq <= vcomax) {
for (o = omin; o <= omax; o++) {
freq = DIV_ROUND_CLOSEST_ULL(vco_freq, o);
diff = abs(freq - rate);
if (vco_freq < vcomin || vco_freq > vcomax)
continue;
if (diff < WZRD_MIN_ERR) {
divider->m = m;
divider->d = d;
divider->o = o;
return 0;
}
}
o = DIV_ROUND_CLOSEST_ULL(vco_freq, rate);
if (o < omin || o > omax)
continue;
freq = DIV_ROUND_CLOSEST_ULL(vco_freq, o);
diff = abs(freq - rate);
if (diff < best_diff) {
best_diff = diff;
divider->m = m;
divider->d = d;
divider->o = o;
if (!diff)
return 0;
}
}
}
return -EBUSY;
return 0;
}
static int clk_wzrd_get_divisors(struct clk_hw *hw, unsigned long rate,
@ -1108,7 +1112,7 @@ static int clk_wzrd_register_output_clocks(struct device *dev, int nr_outputs)
(dev,
clkout_name, clk_name, 0,
clk_wzrd->base,
(WZRD_CLK_CFG_REG(is_versal, 3) + i * 8),
(WZRD_CLK_CFG_REG(is_versal, 2) + i * 8),
WZRD_CLKOUT_DIVIDE_SHIFT,
WZRD_CLKOUT_DIVIDE_WIDTH,
CLK_DIVIDER_ONE_BASED |

36
include/dt-bindings/clock/loongson,ls2k-clk.h
View File

@ -43,4 +43,40 @@
#define LOONGSON2_I2S_CLK 33
#define LOONGSON2_MISC_CLK 34
#define LS2K0300_CLK_STABLE 0
#define LS2K0300_NODE_PLL 1
#define LS2K0300_DDR_PLL 2
#define LS2K0300_PIX_PLL 3
#define LS2K0300_CLK_THSENS 4
#define LS2K0300_CLK_NODE_DIV 5
#define LS2K0300_CLK_NODE_PLL_GATE 6
#define LS2K0300_CLK_NODE_SCALE 7
#define LS2K0300_CLK_NODE_GATE 8
#define LS2K0300_CLK_GMAC_DIV 9
#define LS2K0300_CLK_GMAC_GATE 10
#define LS2K0300_CLK_I2S_DIV 11
#define LS2K0300_CLK_I2S_SCALE 12
#define LS2K0300_CLK_I2S_GATE 13
#define LS2K0300_CLK_DDR_DIV 14
#define LS2K0300_CLK_DDR_GATE 15
#define LS2K0300_CLK_NET_DIV 16
#define LS2K0300_CLK_NET_GATE 17
#define LS2K0300_CLK_DEV_DIV 18
#define LS2K0300_CLK_DEV_GATE 19
#define LS2K0300_CLK_PIX_DIV 20
#define LS2K0300_CLK_PIX_PLL_GATE 21
#define LS2K0300_CLK_PIX_SCALE 22
#define LS2K0300_CLK_PIX_GATE 23
#define LS2K0300_CLK_GMACBP_DIV 24
#define LS2K0300_CLK_GMACBP_GATE 25
#define LS2K0300_CLK_USB_SCALE 26
#define LS2K0300_CLK_USB_GATE 27
#define LS2K0300_CLK_APB_SCALE 28
#define LS2K0300_CLK_APB_GATE 29
#define LS2K0300_CLK_BOOT_SCALE 30
#define LS2K0300_CLK_BOOT_GATE 31
#define LS2K0300_CLK_SDIO_SCALE 32
#define LS2K0300_CLK_SDIO_GATE 33
#define LS2K0300_CLK_GMAC_IN 34
#endif

803
include/dt-bindings/clock/mediatek,mt8196-clock.h Normal file
View File

@ -0,0 +1,803 @@
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
/*
* Copyright (c) 2025 MediaTek Inc.
* Guangjie Song <guangjie.song@mediatek.com>
* Copyright (c) 2025 Collabora Ltd.
* Laura Nao <laura.nao@collabora.com>
*/
#ifndef _DT_BINDINGS_CLK_MT8196_H
#define _DT_BINDINGS_CLK_MT8196_H
/* CKSYS */
#define CLK_TOP_AXI 0
#define CLK_TOP_MEM_SUB 1
#define CLK_TOP_IO_NOC 2
#define CLK_TOP_P_AXI 3
#define CLK_TOP_UFS_PEXTP0_AXI 4
#define CLK_TOP_PEXTP1_USB_AXI 5
#define CLK_TOP_P_FMEM_SUB 6
#define CLK_TOP_PEXPT0_MEM_SUB 7
#define CLK_TOP_PEXTP1_USB_MEM_SUB 8
#define CLK_TOP_P_NOC 9
#define CLK_TOP_EMI_N 10
#define CLK_TOP_EMI_S 11
#define CLK_TOP_AP2CONN_HOST 12
#define CLK_TOP_ATB 13
#define CLK_TOP_CIRQ 14
#define CLK_TOP_PBUS_156M 15
#define CLK_TOP_EFUSE 16
#define CLK_TOP_MCL3GIC 17
#define CLK_TOP_MCINFRA 18
#define CLK_TOP_DSP 19
#define CLK_TOP_MFG_REF 20
#define CLK_TOP_MFG_EB 21
#define CLK_TOP_UART 22
#define CLK_TOP_SPI0_BCLK 23
#define CLK_TOP_SPI1_BCLK 24
#define CLK_TOP_SPI2_BCLK 25
#define CLK_TOP_SPI3_BCLK 26
#define CLK_TOP_SPI4_BCLK 27
#define CLK_TOP_SPI5_BCLK 28
#define CLK_TOP_SPI6_BCLK 29
#define CLK_TOP_SPI7_BCLK 30
#define CLK_TOP_MSDC30_1 31
#define CLK_TOP_MSDC30_2 32
#define CLK_TOP_DISP_PWM 33
#define CLK_TOP_USB_TOP_1P 34
#define CLK_TOP_USB_XHCI_1P 35
#define CLK_TOP_USB_FMCNT_P1 36
#define CLK_TOP_I2C_P 37
#define CLK_TOP_I2C_EAST 38
#define CLK_TOP_I2C_WEST 39
#define CLK_TOP_I2C_NORTH 40
#define CLK_TOP_AES_UFSFDE 41
#define CLK_TOP_UFS 42
#define CLK_TOP_AUD_1 43
#define CLK_TOP_AUD_2 44
#define CLK_TOP_ADSP 45
#define CLK_TOP_ADSP_UARTHUB_B 46
#define CLK_TOP_DPMAIF_MAIN 47
#define CLK_TOP_PWM 48
#define CLK_TOP_MCUPM 49
#define CLK_TOP_IPSEAST 50
#define CLK_TOP_TL 51
#define CLK_TOP_TL_P1 52
#define CLK_TOP_TL_P2 53
#define CLK_TOP_EMI_INTERFACE_546 54
#define CLK_TOP_SDF 55
#define CLK_TOP_UARTHUB_BCLK 56
#define CLK_TOP_DPSW_CMP_26M 57
#define CLK_TOP_SMAP 58
#define CLK_TOP_SSR_PKA 59
#define CLK_TOP_SSR_DMA 60
#define CLK_TOP_SSR_KDF 61
#define CLK_TOP_SSR_RNG 62
#define CLK_TOP_SPU0 63
#define CLK_TOP_SPU1 64
#define CLK_TOP_DXCC 65
#define CLK_TOP_APLL_I2SIN0 66
#define CLK_TOP_APLL_I2SIN1 67
#define CLK_TOP_APLL_I2SIN2 68
#define CLK_TOP_APLL_I2SIN3 69
#define CLK_TOP_APLL_I2SIN4 70
#define CLK_TOP_APLL_I2SIN6 71
#define CLK_TOP_APLL_I2SOUT0 72
#define CLK_TOP_APLL_I2SOUT1 73
#define CLK_TOP_APLL_I2SOUT2 74
#define CLK_TOP_APLL_I2SOUT3 75
#define CLK_TOP_APLL_I2SOUT4 76
#define CLK_TOP_APLL_I2SOUT6 77
#define CLK_TOP_APLL_FMI2S 78
#define CLK_TOP_APLL_TDMOUT 79
#define CLK_TOP_APLL12_DIV_TDMOUT_M 80
#define CLK_TOP_APLL12_DIV_TDMOUT_B 81
#define CLK_TOP_MAINPLL_D3 82
#define CLK_TOP_MAINPLL_D4 83
#define CLK_TOP_MAINPLL_D4_D2 84
#define CLK_TOP_MAINPLL_D4_D4 85
#define CLK_TOP_MAINPLL_D4_D8 86
#define CLK_TOP_MAINPLL_D5 87
#define CLK_TOP_MAINPLL_D5_D2 88
#define CLK_TOP_MAINPLL_D5_D4 89
#define CLK_TOP_MAINPLL_D5_D8 90
#define CLK_TOP_MAINPLL_D6 91
#define CLK_TOP_MAINPLL_D6_D2 92
#define CLK_TOP_MAINPLL_D7 93
#define CLK_TOP_MAINPLL_D7_D2 94
#define CLK_TOP_MAINPLL_D7_D4 95
#define CLK_TOP_MAINPLL_D7_D8 96
#define CLK_TOP_MAINPLL_D9 97
#define CLK_TOP_UNIVPLL_D4 98
#define CLK_TOP_UNIVPLL_D4_D2 99
#define CLK_TOP_UNIVPLL_D4_D4 100
#define CLK_TOP_UNIVPLL_D4_D8 101
#define CLK_TOP_UNIVPLL_D5 102
#define CLK_TOP_UNIVPLL_D5_D2 103
#define CLK_TOP_UNIVPLL_D5_D4 104
#define CLK_TOP_UNIVPLL_D6 105
#define CLK_TOP_UNIVPLL_D6_D2 106
#define CLK_TOP_UNIVPLL_D6_D4 107
#define CLK_TOP_UNIVPLL_D6_D8 108
#define CLK_TOP_UNIVPLL_D6_D16 109
#define CLK_TOP_UNIVPLL_192M 110
#define CLK_TOP_UNIVPLL_192M_D4 111
#define CLK_TOP_UNIVPLL_192M_D8 112
#define CLK_TOP_UNIVPLL_192M_D16 113
#define CLK_TOP_UNIVPLL_192M_D32 114
#define CLK_TOP_UNIVPLL_192M_D10 115
#define CLK_TOP_TVDPLL1_D2 116
#define CLK_TOP_MSDCPLL_D2 117
#define CLK_TOP_OSC_D2 118
#define CLK_TOP_OSC_D3 119
#define CLK_TOP_OSC_D4 120
#define CLK_TOP_OSC_D5 121
#define CLK_TOP_OSC_D7 122
#define CLK_TOP_OSC_D8 123
#define CLK_TOP_OSC_D10 124
#define CLK_TOP_OSC_D14 125
#define CLK_TOP_OSC_D20 126
#define CLK_TOP_OSC_D32 127
#define CLK_TOP_OSC_D40 128
#define CLK_TOP_SFLASH 129
/* APMIXEDSYS */
#define CLK_APMIXED_MAINPLL 0
#define CLK_APMIXED_UNIVPLL 1
#define CLK_APMIXED_MSDCPLL 2
#define CLK_APMIXED_ADSPPLL 3
#define CLK_APMIXED_EMIPLL 4
#define CLK_APMIXED_EMIPLL2 5
#define CLK_APMIXED_NET1PLL 6
#define CLK_APMIXED_SGMIIPLL 7
/* CKSYS_GP2 */
#define CLK_TOP2_SENINF0 0
#define CLK_TOP2_SENINF1 1
#define CLK_TOP2_SENINF2 2
#define CLK_TOP2_SENINF3 3
#define CLK_TOP2_SENINF4 4
#define CLK_TOP2_SENINF5 5
#define CLK_TOP2_IMG1 6
#define CLK_TOP2_IPE 7
#define CLK_TOP2_CAM 8
#define CLK_TOP2_CAMTM 9
#define CLK_TOP2_DPE 10
#define CLK_TOP2_VDEC 11
#define CLK_TOP2_CCUSYS 12
#define CLK_TOP2_CCUTM 13
#define CLK_TOP2_VENC 14
#define CLK_TOP2_DP1 15
#define CLK_TOP2_DP0 16
#define CLK_TOP2_DISP 17
#define CLK_TOP2_MDP 18
#define CLK_TOP2_MMINFRA 19
#define CLK_TOP2_MMINFRA_SNOC 20
#define CLK_TOP2_MMUP 21
#define CLK_TOP2_MMINFRA_AO 22
#define CLK_TOP2_MAINPLL2_D2 23
#define CLK_TOP2_MAINPLL2_D3 24
#define CLK_TOP2_MAINPLL2_D4 25
#define CLK_TOP2_MAINPLL2_D4_D2 26
#define CLK_TOP2_MAINPLL2_D4_D4 27
#define CLK_TOP2_MAINPLL2_D5 28
#define CLK_TOP2_MAINPLL2_D5_D2 29
#define CLK_TOP2_MAINPLL2_D6 30
#define CLK_TOP2_MAINPLL2_D6_D2 31
#define CLK_TOP2_MAINPLL2_D7 32
#define CLK_TOP2_MAINPLL2_D7_D2 33
#define CLK_TOP2_MAINPLL2_D9 34
#define CLK_TOP2_UNIVPLL2_D3 35
#define CLK_TOP2_UNIVPLL2_D4 36
#define CLK_TOP2_UNIVPLL2_D4_D2 37
#define CLK_TOP2_UNIVPLL2_D5 38
#define CLK_TOP2_UNIVPLL2_D5_D2 39
#define CLK_TOP2_UNIVPLL2_D6 40
#define CLK_TOP2_UNIVPLL2_D6_D2 41
#define CLK_TOP2_UNIVPLL2_D6_D4 42
#define CLK_TOP2_UNIVPLL2_D7 43
#define CLK_TOP2_IMGPLL_D2 44
#define CLK_TOP2_IMGPLL_D4 45
#define CLK_TOP2_IMGPLL_D5 46
#define CLK_TOP2_IMGPLL_D5_D2 47
#define CLK_TOP2_MMPLL2_D3 48
#define CLK_TOP2_MMPLL2_D4 49
#define CLK_TOP2_MMPLL2_D4_D2 50
#define CLK_TOP2_MMPLL2_D5 51
#define CLK_TOP2_MMPLL2_D5_D2 52
#define CLK_TOP2_MMPLL2_D6 53
#define CLK_TOP2_MMPLL2_D6_D2 54
#define CLK_TOP2_MMPLL2_D7 55
#define CLK_TOP2_MMPLL2_D9 56
#define CLK_TOP2_TVDPLL1_D4 57
#define CLK_TOP2_TVDPLL1_D8 58
#define CLK_TOP2_TVDPLL1_D16 59
#define CLK_TOP2_TVDPLL2_D2 60
#define CLK_TOP2_TVDPLL2_D4 61
#define CLK_TOP2_TVDPLL2_D8 62
#define CLK_TOP2_TVDPLL2_D16 63
#define CLK_TOP2_DVO 64
#define CLK_TOP2_DVO_FAVT 65
#define CLK_TOP2_TVDPLL3_D2 66
#define CLK_TOP2_TVDPLL3_D4 67
#define CLK_TOP2_TVDPLL3_D8 68
#define CLK_TOP2_TVDPLL3_D16 69
/* APMIXEDSYS_GP2 */
#define CLK_APMIXED2_MAINPLL2 0
#define CLK_APMIXED2_UNIVPLL2 1
#define CLK_APMIXED2_MMPLL2 2
#define CLK_APMIXED2_IMGPLL 3
#define CLK_APMIXED2_TVDPLL1 4
#define CLK_APMIXED2_TVDPLL2 5
#define CLK_APMIXED2_TVDPLL3 6
/* IMP_IIC_WRAP_E */
#define CLK_IMPE_I2C5 0
/* IMP_IIC_WRAP_W */
#define CLK_IMPW_I2C0 0
#define CLK_IMPW_I2C3 1
#define CLK_IMPW_I2C6 2
#define CLK_IMPW_I2C10 3
/* IMP_IIC_WRAP_N */
#define CLK_IMPN_I2C1 0
#define CLK_IMPN_I2C2 1
#define CLK_IMPN_I2C4 2
#define CLK_IMPN_I2C7 3
#define CLK_IMPN_I2C8 4
#define CLK_IMPN_I2C9 5
/* IMP_IIC_WRAP_C */
#define CLK_IMPC_I2C11 0
#define CLK_IMPC_I2C12 1
#define CLK_IMPC_I2C13 2
#define CLK_IMPC_I2C14 3
/* PERICFG_AO */
#define CLK_PERI_AO_UART0_BCLK 0
#define CLK_PERI_AO_UART1_BCLK 1
#define CLK_PERI_AO_UART2_BCLK 2
#define CLK_PERI_AO_UART3_BCLK 3
#define CLK_PERI_AO_UART4_BCLK 4
#define CLK_PERI_AO_UART5_BCLK 5
#define CLK_PERI_AO_PWM_X16W_HCLK 6
#define CLK_PERI_AO_PWM_X16W_BCLK 7
#define CLK_PERI_AO_PWM_PWM_BCLK0 8
#define CLK_PERI_AO_PWM_PWM_BCLK1 9
#define CLK_PERI_AO_PWM_PWM_BCLK2 10
#define CLK_PERI_AO_PWM_PWM_BCLK3 11
#define CLK_PERI_AO_SPI0_BCLK 12
#define CLK_PERI_AO_SPI1_BCLK 13
#define CLK_PERI_AO_SPI2_BCLK 14
#define CLK_PERI_AO_SPI3_BCLK 15
#define CLK_PERI_AO_SPI4_BCLK 16
#define CLK_PERI_AO_SPI5_BCLK 17
#define CLK_PERI_AO_SPI6_BCLK 18
#define CLK_PERI_AO_SPI7_BCLK 19
#define CLK_PERI_AO_AP_DMA_X32W_BCLK 20
#define CLK_PERI_AO_MSDC1_MSDC_SRC 21
#define CLK_PERI_AO_MSDC1_HCLK 22
#define CLK_PERI_AO_MSDC1_AXI 23
#define CLK_PERI_AO_MSDC1_HCLK_WRAP 24
#define CLK_PERI_AO_MSDC2_MSDC_SRC 25
#define CLK_PERI_AO_MSDC2_HCLK 26
#define CLK_PERI_AO_MSDC2_AXI 27
#define CLK_PERI_AO_MSDC2_HCLK_WRAP 28
#define CLK_PERI_AO_FLASHIF_FLASH 29
#define CLK_PERI_AO_FLASHIF_27M 30
#define CLK_PERI_AO_FLASHIF_DRAM 31
#define CLK_PERI_AO_FLASHIF_AXI 32
#define CLK_PERI_AO_FLASHIF_BCLK 33
/* UFSCFG_AO */
#define CLK_UFSAO_UNIPRO_TX_SYM 0
#define CLK_UFSAO_UNIPRO_RX_SYM0 1
#define CLK_UFSAO_UNIPRO_RX_SYM1 2
#define CLK_UFSAO_UNIPRO_SYS 3
#define CLK_UFSAO_UNIPRO_SAP 4
#define CLK_UFSAO_PHY_SAP 5
#define CLK_UFSAO_UFSHCI_UFS 6
#define CLK_UFSAO_UFSHCI_AES 7
/* PEXTP0CFG_AO */
#define CLK_PEXT_PEXTP_MAC_P0_TL 0
#define CLK_PEXT_PEXTP_MAC_P0_REF 1
#define CLK_PEXT_PEXTP_PHY_P0_MCU_BUS 2
#define CLK_PEXT_PEXTP_PHY_P0_PEXTP_REF 3
#define CLK_PEXT_PEXTP_MAC_P0_AXI_250 4
#define CLK_PEXT_PEXTP_MAC_P0_AHB_APB 5
#define CLK_PEXT_PEXTP_MAC_P0_PL_P 6
#define CLK_PEXT_PEXTP_VLP_AO_P0_LP 7
/* PEXTP1CFG_AO */
#define CLK_PEXT1_PEXTP_MAC_P1_TL 0
#define CLK_PEXT1_PEXTP_MAC_P1_REF 1
#define CLK_PEXT1_PEXTP_MAC_P2_TL 2
#define CLK_PEXT1_PEXTP_MAC_P2_REF 3
#define CLK_PEXT1_PEXTP_PHY_P1_MCU_BUS 4
#define CLK_PEXT1_PEXTP_PHY_P1_PEXTP_REF 5
#define CLK_PEXT1_PEXTP_PHY_P2_MCU_BUS 6
#define CLK_PEXT1_PEXTP_PHY_P2_PEXTP_REF 7
#define CLK_PEXT1_PEXTP_MAC_P1_AXI_250 8
#define CLK_PEXT1_PEXTP_MAC_P1_AHB_APB 9
#define CLK_PEXT1_PEXTP_MAC_P1_PL_P 10
#define CLK_PEXT1_PEXTP_MAC_P2_AXI_250 11
#define CLK_PEXT1_PEXTP_MAC_P2_AHB_APB 12
#define CLK_PEXT1_PEXTP_MAC_P2_PL_P 13
#define CLK_PEXT1_PEXTP_VLP_AO_P1_LP 14
#define CLK_PEXT1_PEXTP_VLP_AO_P2_LP 15
/* VLP_CKSYS */
#define CLK_VLP_APLL1 0
#define CLK_VLP_APLL2 1
#define CLK_VLP_SCP 2
#define CLK_VLP_SCP_SPI 3
#define CLK_VLP_SCP_IIC 4
#define CLK_VLP_SCP_IIC_HS 5
#define CLK_VLP_PWRAP_ULPOSC 6
#define CLK_VLP_SPMI_M_TIA_32K 7
#define CLK_VLP_APXGPT_26M_B 8
#define CLK_VLP_DPSW 9
#define CLK_VLP_DPSW_CENTRAL 10
#define CLK_VLP_SPMI_M_MST 11
#define CLK_VLP_DVFSRC 12
#define CLK_VLP_PWM_VLP 13
#define CLK_VLP_AXI_VLP 14
#define CLK_VLP_SYSTIMER_26M 15
#define CLK_VLP_SSPM 16
#define CLK_VLP_SRCK 17
#define CLK_VLP_CAMTG0 18
#define CLK_VLP_CAMTG1 19
#define CLK_VLP_CAMTG2 20
#define CLK_VLP_CAMTG3 21
#define CLK_VLP_CAMTG4 22
#define CLK_VLP_CAMTG5 23
#define CLK_VLP_CAMTG6 24
#define CLK_VLP_CAMTG7 25
#define CLK_VLP_SSPM_26M 26
#define CLK_VLP_ULPOSC_SSPM 27
#define CLK_VLP_VLP_PBUS_26M 28
#define CLK_VLP_DEBUG_ERR_FLAG 29
#define CLK_VLP_DPMSRDMA 30
#define CLK_VLP_VLP_PBUS_156M 31
#define CLK_VLP_SPM 32
#define CLK_VLP_MMINFRA 33
#define CLK_VLP_USB_TOP 34
#define CLK_VLP_USB_XHCI 35
#define CLK_VLP_NOC_VLP 36
#define CLK_VLP_AUDIO_H 37
#define CLK_VLP_AUD_ENGEN1 38
#define CLK_VLP_AUD_ENGEN2 39
#define CLK_VLP_AUD_INTBUS 40
#define CLK_VLP_SPVLP_26M 41
#define CLK_VLP_SPU0_VLP 42
#define CLK_VLP_SPU1_VLP 43
#define CLK_VLP_CLK26M 44
#define CLK_VLP_APLL1_D4 45
#define CLK_VLP_APLL1_D8 46
#define CLK_VLP_APLL2_D4 47
#define CLK_VLP_APLL2_D8 48
/* DISPSYS_CONFIG */
#define CLK_MM_CONFIG 0
#define CLK_MM_DISP_MUTEX0 1
#define CLK_MM_DISP_AAL0 2
#define CLK_MM_DISP_AAL1 3
#define CLK_MM_DISP_C3D0 4
#define CLK_MM_DISP_C3D1 5
#define CLK_MM_DISP_C3D2 6
#define CLK_MM_DISP_C3D3 7
#define CLK_MM_DISP_CCORR0 8
#define CLK_MM_DISP_CCORR1 9
#define CLK_MM_DISP_CCORR2 10
#define CLK_MM_DISP_CCORR3 11
#define CLK_MM_DISP_CHIST0 12
#define CLK_MM_DISP_CHIST1 13
#define CLK_MM_DISP_COLOR0 14
#define CLK_MM_DISP_COLOR1 15
#define CLK_MM_DISP_DITHER0 16
#define CLK_MM_DISP_DITHER1 17
#define CLK_MM_DISP_DLI_ASYNC0 18
#define CLK_MM_DISP_DLI_ASYNC1 19
#define CLK_MM_DISP_DLI_ASYNC2 20
#define CLK_MM_DISP_DLI_ASYNC3 21
#define CLK_MM_DISP_DLI_ASYNC4 22
#define CLK_MM_DISP_DLI_ASYNC5 23
#define CLK_MM_DISP_DLI_ASYNC6 24
#define CLK_MM_DISP_DLI_ASYNC7 25
#define CLK_MM_DISP_DLI_ASYNC8 26
#define CLK_MM_DISP_DLI_ASYNC9 27
#define CLK_MM_DISP_DLI_ASYNC10 28
#define CLK_MM_DISP_DLI_ASYNC11 29
#define CLK_MM_DISP_DLI_ASYNC12 30
#define CLK_MM_DISP_DLI_ASYNC13 31
#define CLK_MM_DISP_DLI_ASYNC14 32
#define CLK_MM_DISP_DLI_ASYNC15 33
#define CLK_MM_DISP_DLO_ASYNC0 34
#define CLK_MM_DISP_DLO_ASYNC1 35
#define CLK_MM_DISP_DLO_ASYNC2 36
#define CLK_MM_DISP_DLO_ASYNC3 37
#define CLK_MM_DISP_DLO_ASYNC4 38
#define CLK_MM_DISP_DLO_ASYNC5 39
#define CLK_MM_DISP_DLO_ASYNC6 40
#define CLK_MM_DISP_DLO_ASYNC7 41
#define CLK_MM_DISP_DLO_ASYNC8 42
#define CLK_MM_DISP_GAMMA0 43
#define CLK_MM_DISP_GAMMA1 44
#define CLK_MM_MDP_AAL0 45
#define CLK_MM_MDP_AAL1 46
#define CLK_MM_MDP_RDMA0 47
#define CLK_MM_DISP_POSTMASK0 48
#define CLK_MM_DISP_POSTMASK1 49
#define CLK_MM_MDP_RSZ0 50
#define CLK_MM_MDP_RSZ1 51
#define CLK_MM_DISP_SPR0 52
#define CLK_MM_DISP_TDSHP0 53
#define CLK_MM_DISP_TDSHP1 54
#define CLK_MM_DISP_WDMA0 55
#define CLK_MM_DISP_Y2R0 56
#define CLK_MM_SMI_SUB_COMM0 57
#define CLK_MM_DISP_FAKE_ENG0 58
/* DISPSYS1_CONFIG */
#define CLK_MM1_DISPSYS1_CONFIG 0
#define CLK_MM1_DISPSYS1_S_CONFIG 1
#define CLK_MM1_DISP_MUTEX0 2
#define CLK_MM1_DISP_DLI_ASYNC20 3
#define CLK_MM1_DISP_DLI_ASYNC21 4
#define CLK_MM1_DISP_DLI_ASYNC22 5
#define CLK_MM1_DISP_DLI_ASYNC23 6
#define CLK_MM1_DISP_DLI_ASYNC24 7
#define CLK_MM1_DISP_DLI_ASYNC25 8
#define CLK_MM1_DISP_DLI_ASYNC26 9
#define CLK_MM1_DISP_DLI_ASYNC27 10
#define CLK_MM1_DISP_DLI_ASYNC28 11
#define CLK_MM1_DISP_RELAY0 12
#define CLK_MM1_DISP_RELAY1 13
#define CLK_MM1_DISP_RELAY2 14
#define CLK_MM1_DISP_RELAY3 15
#define CLK_MM1_DISP_DP_INTF0 16
#define CLK_MM1_DISP_DP_INTF1 17
#define CLK_MM1_DISP_DSC_WRAP0 18
#define CLK_MM1_DISP_DSC_WRAP1 19
#define CLK_MM1_DISP_DSC_WRAP2 20
#define CLK_MM1_DISP_DSC_WRAP3 21
#define CLK_MM1_DISP_DSI0 22
#define CLK_MM1_DISP_DSI1 23
#define CLK_MM1_DISP_DSI2 24
#define CLK_MM1_DISP_DVO0 25
#define CLK_MM1_DISP_GDMA0 26
#define CLK_MM1_DISP_MERGE0 27
#define CLK_MM1_DISP_MERGE1 28
#define CLK_MM1_DISP_MERGE2 29
#define CLK_MM1_DISP_ODDMR0 30
#define CLK_MM1_DISP_POSTALIGN0 31
#define CLK_MM1_DISP_DITHER2 32
#define CLK_MM1_DISP_R2Y0 33
#define CLK_MM1_DISP_SPLITTER0 34
#define CLK_MM1_DISP_SPLITTER1 35
#define CLK_MM1_DISP_SPLITTER2 36
#define CLK_MM1_DISP_SPLITTER3 37
#define CLK_MM1_DISP_VDCM0 38
#define CLK_MM1_DISP_WDMA1 39
#define CLK_MM1_DISP_WDMA2 40
#define CLK_MM1_DISP_WDMA3 41
#define CLK_MM1_DISP_WDMA4 42
#define CLK_MM1_MDP_RDMA1 43
#define CLK_MM1_SMI_LARB0 44
#define CLK_MM1_MOD1 45
#define CLK_MM1_MOD2 46
#define CLK_MM1_MOD3 47
#define CLK_MM1_MOD4 48
#define CLK_MM1_MOD5 49
#define CLK_MM1_MOD6 50
#define CLK_MM1_CG0 51
#define CLK_MM1_CG1 52
#define CLK_MM1_CG2 53
#define CLK_MM1_CG3 54
#define CLK_MM1_CG4 55
#define CLK_MM1_CG5 56
#define CLK_MM1_CG6 57
#define CLK_MM1_CG7 58
#define CLK_MM1_F26M 59
/* OVLSYS_CONFIG */
#define CLK_OVLSYS_CONFIG 0
#define CLK_OVL_FAKE_ENG0 1
#define CLK_OVL_FAKE_ENG1 2
#define CLK_OVL_MUTEX0 3
#define CLK_OVL_EXDMA0 4
#define CLK_OVL_EXDMA1 5
#define CLK_OVL_EXDMA2 6
#define CLK_OVL_EXDMA3 7
#define CLK_OVL_EXDMA4 8
#define CLK_OVL_EXDMA5 9
#define CLK_OVL_EXDMA6 10
#define CLK_OVL_EXDMA7 11
#define CLK_OVL_EXDMA8 12
#define CLK_OVL_EXDMA9 13
#define CLK_OVL_BLENDER0 14
#define CLK_OVL_BLENDER1 15
#define CLK_OVL_BLENDER2 16
#define CLK_OVL_BLENDER3 17
#define CLK_OVL_BLENDER4 18
#define CLK_OVL_BLENDER5 19
#define CLK_OVL_BLENDER6 20
#define CLK_OVL_BLENDER7 21
#define CLK_OVL_BLENDER8 22
#define CLK_OVL_BLENDER9 23
#define CLK_OVL_OUTPROC0 24
#define CLK_OVL_OUTPROC1 25
#define CLK_OVL_OUTPROC2 26
#define CLK_OVL_OUTPROC3 27
#define CLK_OVL_OUTPROC4 28
#define CLK_OVL_OUTPROC5 29
#define CLK_OVL_MDP_RSZ0 30
#define CLK_OVL_MDP_RSZ1 31
#define CLK_OVL_DISP_WDMA0 32
#define CLK_OVL_DISP_WDMA1 33
#define CLK_OVL_UFBC_WDMA0 34
#define CLK_OVL_MDP_RDMA0 35
#define CLK_OVL_MDP_RDMA1 36
#define CLK_OVL_BWM0 37
#define CLK_OVL_DLI0 38
#define CLK_OVL_DLI1 39
#define CLK_OVL_DLI2 40
#define CLK_OVL_DLI3 41
#define CLK_OVL_DLI4 42
#define CLK_OVL_DLI5 43
#define CLK_OVL_DLI6 44
#define CLK_OVL_DLI7 45
#define CLK_OVL_DLI8 46
#define CLK_OVL_DLO0 47
#define CLK_OVL_DLO1 48
#define CLK_OVL_DLO2 49
#define CLK_OVL_DLO3 50
#define CLK_OVL_DLO4 51
#define CLK_OVL_DLO5 52
#define CLK_OVL_DLO6 53
#define CLK_OVL_DLO7 54
#define CLK_OVL_DLO8 55
#define CLK_OVL_DLO9 56
#define CLK_OVL_DLO10 57
#define CLK_OVL_DLO11 58
#define CLK_OVL_DLO12 59
#define CLK_OVLSYS_RELAY0 60
#define CLK_OVL_INLINEROT0 61
#define CLK_OVL_SMI 62
#define CLK_OVL_SMI_SMI 63
/* OVLSYS1_CONFIG */
#define CLK_OVL1_OVLSYS_CONFIG 0
#define CLK_OVL1_OVL_FAKE_ENG0 1
#define CLK_OVL1_OVL_FAKE_ENG1 2
#define CLK_OVL1_OVL_MUTEX0 3
#define CLK_OVL1_OVL_EXDMA0 4
#define CLK_OVL1_OVL_EXDMA1 5
#define CLK_OVL1_OVL_EXDMA2 6
#define CLK_OVL1_OVL_EXDMA3 7
#define CLK_OVL1_OVL_EXDMA4 8
#define CLK_OVL1_OVL_EXDMA5 9
#define CLK_OVL1_OVL_EXDMA6 10
#define CLK_OVL1_OVL_EXDMA7 11
#define CLK_OVL1_OVL_EXDMA8 12
#define CLK_OVL1_OVL_EXDMA9 13
#define CLK_OVL1_OVL_BLENDER0 14
#define CLK_OVL1_OVL_BLENDER1 15
#define CLK_OVL1_OVL_BLENDER2 16
#define CLK_OVL1_OVL_BLENDER3 17
#define CLK_OVL1_OVL_BLENDER4 18
#define CLK_OVL1_OVL_BLENDER5 19
#define CLK_OVL1_OVL_BLENDER6 20
#define CLK_OVL1_OVL_BLENDER7 21
#define CLK_OVL1_OVL_BLENDER8 22
#define CLK_OVL1_OVL_BLENDER9 23
#define CLK_OVL1_OVL_OUTPROC0 24
#define CLK_OVL1_OVL_OUTPROC1 25
#define CLK_OVL1_OVL_OUTPROC2 26
#define CLK_OVL1_OVL_OUTPROC3 27
#define CLK_OVL1_OVL_OUTPROC4 28
#define CLK_OVL1_OVL_OUTPROC5 29
#define CLK_OVL1_OVL_MDP_RSZ0 30
#define CLK_OVL1_OVL_MDP_RSZ1 31
#define CLK_OVL1_OVL_DISP_WDMA0 32
#define CLK_OVL1_OVL_DISP_WDMA1 33
#define CLK_OVL1_OVL_UFBC_WDMA0 34
#define CLK_OVL1_OVL_MDP_RDMA0 35
#define CLK_OVL1_OVL_MDP_RDMA1 36
#define CLK_OVL1_OVL_BWM0 37
#define CLK_OVL1_DLI0 38
#define CLK_OVL1_DLI1 39
#define CLK_OVL1_DLI2 40
#define CLK_OVL1_DLI3 41
#define CLK_OVL1_DLI4 42
#define CLK_OVL1_DLI5 43
#define CLK_OVL1_DLI6 44
#define CLK_OVL1_DLI7 45
#define CLK_OVL1_DLI8 46
#define CLK_OVL1_DLO0 47
#define CLK_OVL1_DLO1 48
#define CLK_OVL1_DLO2 49
#define CLK_OVL1_DLO3 50
#define CLK_OVL1_DLO4 51
#define CLK_OVL1_DLO5 52
#define CLK_OVL1_DLO6 53
#define CLK_OVL1_DLO7 54
#define CLK_OVL1_DLO8 55
#define CLK_OVL1_DLO9 56
#define CLK_OVL1_DLO10 57
#define CLK_OVL1_DLO11 58
#define CLK_OVL1_DLO12 59
#define CLK_OVL1_OVLSYS_RELAY0 60
#define CLK_OVL1_OVL_INLINEROT0 61
#define CLK_OVL1_SMI 62
/* VDEC_SOC_GCON_BASE */
#define CLK_VDE1_LARB1_CKEN 0
#define CLK_VDE1_LAT_CKEN 1
#define CLK_VDE1_LAT_ACTIVE 2
#define CLK_VDE1_LAT_CKEN_ENG 3
#define CLK_VDE1_VDEC_CKEN 4
#define CLK_VDE1_VDEC_ACTIVE 5
#define CLK_VDE1_VDEC_CKEN_ENG 6
#define CLK_VDE1_VDEC_SOC_APTV_EN 7
#define CLK_VDE1_VDEC_SOC_APTV_TOP_EN 8
#define CLK_VDE1_VDEC_SOC_IPS_EN 9
/* VDEC_GCON_BASE */
#define CLK_VDE2_LARB1_CKEN 0
#define CLK_VDE2_LAT_CKEN 1
#define CLK_VDE2_LAT_ACTIVE 2
#define CLK_VDE2_LAT_CKEN_ENG 3
#define CLK_VDE2_VDEC_CKEN 4
#define CLK_VDE2_VDEC_ACTIVE 5
#define CLK_VDE2_VDEC_CKEN_ENG 6
/* VENC_GCON */
#define CLK_VEN1_CKE0_LARB 0
#define CLK_VEN1_CKE1_VENC 1
#define CLK_VEN1_CKE2_JPGENC 2
#define CLK_VEN1_CKE3_JPGDEC 3
#define CLK_VEN1_CKE4_JPGDEC_C1 4
#define CLK_VEN1_CKE5_GALS 5
#define CLK_VEN1_CKE29_VENC_ADAB_CTRL 6
#define CLK_VEN1_CKE29_VENC_XPC_CTRL 7
#define CLK_VEN1_CKE6_GALS_SRAM 8
#define CLK_VEN1_RES_FLAT 9
/* VENC_GCON_CORE1 */
#define CLK_VEN2_CKE0_LARB 0
#define CLK_VEN2_CKE1_VENC 1
#define CLK_VEN2_CKE2_JPGENC 2
#define CLK_VEN2_CKE3_JPGDEC 3
#define CLK_VEN2_CKE5_GALS 4
#define CLK_VEN2_CKE29_VENC_XPC_CTRL 5
#define CLK_VEN2_CKE6_GALS_SRAM 6
#define CLK_VEN2_RES_FLAT 7
/* VENC_GCON_CORE2 */
#define CLK_VEN_C2_CKE0_LARB 0
#define CLK_VEN_C2_CKE1_VENC 1
#define CLK_VEN_C2_CKE5_GALS 2
#define CLK_VEN_C2_CKE29_VENC_XPC_CTRL 3
#define CLK_VEN_C2_CKE6_GALS_SRAM 4
#define CLK_VEN_C2_RES_FLAT 5
/* MDPSYS_CONFIG */
#define CLK_MDP_MDP_MUTEX0 0
#define CLK_MDP_SMI0 1
#define CLK_MDP_SMI0_SMI 2
#define CLK_MDP_APB_BUS 3
#define CLK_MDP_MDP_RDMA0 4
#define CLK_MDP_MDP_RDMA1 5
#define CLK_MDP_MDP_RDMA2 6
#define CLK_MDP_MDP_BIRSZ0 7
#define CLK_MDP_MDP_HDR0 8
#define CLK_MDP_MDP_AAL0 9
#define CLK_MDP_MDP_RSZ0 10
#define CLK_MDP_MDP_RSZ2 11
#define CLK_MDP_MDP_TDSHP0 12
#define CLK_MDP_MDP_COLOR0 13
#define CLK_MDP_MDP_WROT0 14
#define CLK_MDP_MDP_WROT1 15
#define CLK_MDP_MDP_WROT2 16
#define CLK_MDP_MDP_FAKE_ENG0 17
#define CLK_MDP_APB_DB 18
#define CLK_MDP_MDP_DLI_ASYNC0 19
#define CLK_MDP_MDP_DLI_ASYNC1 20
#define CLK_MDP_MDP_DLO_ASYNC0 21
#define CLK_MDP_MDP_DLO_ASYNC1 22
#define CLK_MDP_MDP_DLI_ASYNC2 23
#define CLK_MDP_MDP_DLO_ASYNC2 24
#define CLK_MDP_MDP_DLO_ASYNC3 25
#define CLK_MDP_IMG_DL_ASYNC0 26
#define CLK_MDP_MDP_RROT0 27
#define CLK_MDP_MDP_MERGE0 28
#define CLK_MDP_MDP_C3D0 29
#define CLK_MDP_MDP_FG0 30
#define CLK_MDP_MDP_CLA2 31
#define CLK_MDP_MDP_DLO_ASYNC4 32
#define CLK_MDP_VPP_RSZ0 33
#define CLK_MDP_VPP_RSZ1 34
#define CLK_MDP_MDP_DLO_ASYNC5 35
#define CLK_MDP_IMG0 36
#define CLK_MDP_F26M 37
#define CLK_MDP_IMG_DL_RELAY0 38
#define CLK_MDP_IMG_DL_RELAY1 39
/* MDPSYS1_CONFIG */
#define CLK_MDP1_MDP_MUTEX0 0
#define CLK_MDP1_SMI0 1
#define CLK_MDP1_SMI0_SMI 2
#define CLK_MDP1_APB_BUS 3
#define CLK_MDP1_MDP_RDMA0 4
#define CLK_MDP1_MDP_RDMA1 5
#define CLK_MDP1_MDP_RDMA2 6
#define CLK_MDP1_MDP_BIRSZ0 7
#define CLK_MDP1_MDP_HDR0 8
#define CLK_MDP1_MDP_AAL0 9
#define CLK_MDP1_MDP_RSZ0 10
#define CLK_MDP1_MDP_RSZ2 11
#define CLK_MDP1_MDP_TDSHP0 12
#define CLK_MDP1_MDP_COLOR0 13
#define CLK_MDP1_MDP_WROT0 14
#define CLK_MDP1_MDP_WROT1 15
#define CLK_MDP1_MDP_WROT2 16
#define CLK_MDP1_MDP_FAKE_ENG0 17
#define CLK_MDP1_APB_DB 18
#define CLK_MDP1_MDP_DLI_ASYNC0 19
#define CLK_MDP1_MDP_DLI_ASYNC1 20
#define CLK_MDP1_MDP_DLO_ASYNC0 21
#define CLK_MDP1_MDP_DLO_ASYNC1 22
#define CLK_MDP1_MDP_DLI_ASYNC2 23
#define CLK_MDP1_MDP_DLO_ASYNC2 24
#define CLK_MDP1_MDP_DLO_ASYNC3 25
#define CLK_MDP1_IMG_DL_ASYNC0 26
#define CLK_MDP1_MDP_RROT0 27
#define CLK_MDP1_MDP_MERGE0 28
#define CLK_MDP1_MDP_C3D0 29
#define CLK_MDP1_MDP_FG0 30
#define CLK_MDP1_MDP_CLA2 31
#define CLK_MDP1_MDP_DLO_ASYNC4 32
#define CLK_MDP1_VPP_RSZ0 33
#define CLK_MDP1_VPP_RSZ1 34
#define CLK_MDP1_MDP_DLO_ASYNC5 35
#define CLK_MDP1_IMG0 36
#define CLK_MDP1_F26M 37
#define CLK_MDP1_IMG_DL_RELAY0 38
#define CLK_MDP1_IMG_DL_RELAY1 39
/* DISP_VDISP_AO_CONFIG */
#define CLK_MM_V_DISP_VDISP_AO_CONFIG 0
#define CLK_MM_V_DISP_DPC 1
#define CLK_MM_V_SMI_SUB_SOMM0 2
/* MFGPLL_PLL_CTRL */
#define CLK_MFG_AO_MFGPLL 0
/* MFGPLL_SC0_PLL_CTRL */
#define CLK_MFGSC0_AO_MFGPLL_SC0 0
/* MFGPLL_SC1_PLL_CTRL */
#define CLK_MFGSC1_AO_MFGPLL_SC1 0
/* CCIPLL_PLL_CTRL */
#define CLK_CCIPLL 0
/* ARMPLL_LL_PLL_CTRL */
#define CLK_CPLL_ARMPLL_LL 0
/* ARMPLL_BL_PLL_CTRL */
#define CLK_CPBL_ARMPLL_BL 0
/* ARMPLL_B_PLL_CTRL */
#define CLK_CPB_ARMPLL_B 0
/* PTPPLL_PLL_CTRL */
#define CLK_PTPPLL 0
#endif /* _DT_BINDINGS_CLK_MT8196_H */

2
include/dt-bindings/clock/mt7622-clk.h
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@ -228,7 +228,7 @@
#define CLK_AUDIO_MEM_ASRC4 44
#define CLK_AUDIO_MEM_ASRC5 45
#define CLK_AUDIO_AFE_CONN 46
#define CLK_AUDIO_NR_CLK 47
#define CLK_AUDIO_AFE_MRGIF 47
/* SSUSBSYS */

26
include/dt-bindings/reset/mediatek,mt8196-resets.h Normal file
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@ -0,0 +1,26 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2025 Collabora Ltd.
* Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
*/
#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8196
#define _DT_BINDINGS_RESET_CONTROLLER_MT8196
/* PEXTP0 resets */
#define MT8196_PEXTP0_RST0_PCIE0_MAC 0
#define MT8196_PEXTP0_RST0_PCIE0_PHY 1
/* PEXTP1 resets */
#define MT8196_PEXTP1_RST0_PCIE1_MAC 0
#define MT8196_PEXTP1_RST0_PCIE1_PHY 1
#define MT8196_PEXTP1_RST0_PCIE2_MAC 2
#define MT8196_PEXTP1_RST0_PCIE2_PHY 3
/* UFS resets */
#define MT8196_UFSAO_RST0_UFS_MPHY 0
#define MT8196_UFSAO_RST1_UFS_UNIPRO 1
#define MT8196_UFSAO_RST1_UFS_CRYPTO 2
#define MT8196_UFSAO_RST1_UFSHCI 3
#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8196 */