From 7f5b28218cec55072b562be386675ccae41acca1 Mon Sep 17 00:00:00 2001 From: Drew Fustini Date: Thu, 1 Aug 2024 11:38:09 -0700 Subject: [PATCH] riscv: dts: thead: add clock to TH1520 gpio nodes Add clock property to TH1520 gpio controller nodes. These clock gates refer to corresponding enable bits in the peripheral clock gate control register. Refer to register PERI_CLK_CFG in section 4.4.2.2.52 of the TH1520 System User Manual. Link: https://git.beagleboard.org/beaglev-ahead/beaglev-ahead/-/tree/main/docs Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index 6ea5cabbcf60..5f4f94ca9cc7 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -327,6 +327,7 @@ reg = <0xff 0xe7f34000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; + clocks = <&clk CLK_GPIO2>; portc: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; @@ -345,6 +346,7 @@ reg = <0xff 0xe7f38000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; + clocks = <&clk CLK_GPIO3>; portd: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; @@ -363,6 +365,7 @@ reg = <0xff 0xec005000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; + clocks = <&clk CLK_GPIO0>; porta: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; @@ -381,6 +384,7 @@ reg = <0xff 0xec006000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; + clocks = <&clk CLK_GPIO1>; portb: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port";