From 7587fa56700e5fb265d98f000853b00866f5541f Mon Sep 17 00:00:00 2001 From: Heinrich Toews Date: Tue, 24 Feb 2026 10:43:23 +0100 Subject: [PATCH] arm: dts: pfc-750-84xx-wosm: mram: adjust timings for 80 Mhz 8s-8s-8s mode Signed-off-by: Heinrich Toews --- .../dts/ti/k3-am623-pfc-750-84xx-wosm.dtsi | 25 +++++++++++++------ 1 file changed, 17 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am623-pfc-750-84xx-wosm.dtsi b/arch/arm64/boot/dts/ti/k3-am623-pfc-750-84xx-wosm.dtsi index b3e3a9e75c88..cea5c30431a5 100644 --- a/arch/arm64/boot/dts/ti/k3-am623-pfc-750-84xx-wosm.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am623-pfc-750-84xx-wosm.dtsi @@ -195,17 +195,26 @@ compatible = "jedec,spi-nor"; reg = <0x0>; - spi-tx-bus-width = <8>; - spi-rx-bus-width = <8>; - spi-max-frequency = <25000000>; - cdns,tshsl-ns = <60>; - cdns,tsd2d-ns = <60>; - cdns,tchsh-ns = <60>; - cdns,tslch-ns = <60>; - cdns,read-delay = <4>; + /* 80 MHz Target */ + spi-max-frequency = <80000000>; + + /* PHY mode is highly recommended for >50MHz on Cadence controllers */ cdns,phy-mode; + /* Read delay: Start with 0. + If you get bit errors, try cdns,read-delay = <1>; */ + cdns,read-delay = <0>; + + /* Tighten timings for 80MHz operation (T=12.5ns) */ + cdns,tshsl-ns = <25>; /* Chip Select high pulse width */ + cdns,tsd2d-ns = <25>; /* Delay between two back-to-back transfers */ + cdns,tchsh-ns = <6>; /* CS# hold time */ + cdns,tslch-ns = <6>; /* CS# setup time */ + + spi-rx-bus-width = <8>; + spi-tx-bus-width = <8>; + partitions { compatible = "fixed-partitions"; #address-cells = <1>;