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dt-bindings: mailbox: fix the mpfs' reg property

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The "data" region of the PolarFire SoC's system controller mailbox is
not one continuous register space - the system controller's QSPI sits
between the control and data registers. Split the "data" reg into two
parts: "data" & "control".

Fixes: 213556235526 ("dt-bindings: soc/microchip: update syscontroller compatibles")
Fixes: ed9543d6f2c4 ("dt-bindings: add bindings for polarfire soc mailbox")
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
This commit is contained in:
Conor Dooley 2022-08-24 08:08:10 +01:00 committed by Jassi Brar
parent 7e5cd064f7
commit 6e2bdf7dc3
1 changed files with 11 additions and 4 deletions
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15
Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml
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@ -14,9 +14,15 @@ properties:
const: microchip,mpfs-mailbox
reg:
items:
- description: mailbox data registers
- description: mailbox interrupt registers
oneOf:
- items:
- description: mailbox control & data registers
- description: mailbox interrupt registers
deprecated: true
- items:
- description: mailbox control registers
- description: mailbox interrupt registers
- description: mailbox data registers
interrupts:
maxItems: 1
@ -39,7 +45,8 @@ examples:
#size-cells = <2>;
mbox: mailbox@37020000 {
compatible = "microchip,mpfs-mailbox";
reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318c 0x0 0x40>;
reg = <0x0 0x37020000 0x0 0x58>, <0x0 0x2000318C 0x0 0x40>,
<0x0 0x37020800 0x0 0x100>;
interrupt-parent = <&L1>;
interrupts = <96>;
#mbox-cells = <1>;