drm/amd/amdgpu: Add CP_IB1_BASE_* to gc_10_3_0 headers
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -6955,6 +6955,12 @@
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#define mmCP_CE_IB2_BASE_HI_BASE_IDX 1
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#define mmCP_CE_IB2_BUFSZ 0x20cb
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#define mmCP_CE_IB2_BUFSZ_BASE_IDX 1
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#define mmCP_IB1_BASE_LO 0x20cc
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#define mmCP_IB1_BASE_LO_BASE_IDX 1
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#define mmCP_IB1_BASE_HI 0x20cd
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#define mmCP_IB1_BASE_HI_BASE_IDX 1
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#define mmCP_IB1_BUFSZ 0x20ce
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#define mmCP_IB1_BUFSZ_BASE_IDX 1
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#define mmCP_IB2_BASE_LO 0x20cf
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#define mmCP_IB2_BASE_LO_BASE_IDX 1
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#define mmCP_IB2_BASE_HI 0x20d0
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@ -25818,6 +25818,15 @@
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//CP_CE_IB2_BUFSZ
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#define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0
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#define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000FFFFFL
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//CP_IB1_BASE_LO
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#define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2
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#define CP_IB1_BASE_LO__IB1_BASE_LO_MASK 0xFFFFFFFCL
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//CP_IB1_BASE_HI
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#define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0
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#define CP_IB1_BASE_HI__IB1_BASE_HI_MASK 0x0000FFFFL
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//CP_IB1_BUFSZ
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#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0
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#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000FFFFFL
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//CP_IB2_BASE_LO
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#define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2
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#define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xFFFFFFFCL
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