From 5c81f0089b0b473d2cf0f432a5a905e04056be82 Mon Sep 17 00:00:00 2001 From: Andrej Unrau Date: Mon, 11 May 2026 10:13:10 +0200 Subject: [PATCH] Revert "arm: dts: pfc-750-84xx-wosm: mram: optimize timings" This reverts commit 49f86c67e217f5bc745c203db5ba3c2783f53076. The optimized MRAM timings are not stable on all devices. Signed-off-by: Andrej Unrau --- arch/arm64/boot/dts/ti/k3-am623-pfc-750-84xx-wosm.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am623-pfc-750-84xx-wosm.dtsi b/arch/arm64/boot/dts/ti/k3-am623-pfc-750-84xx-wosm.dtsi index 546d2038837b..f99f3c884c2f 100644 --- a/arch/arm64/boot/dts/ti/k3-am623-pfc-750-84xx-wosm.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am623-pfc-750-84xx-wosm.dtsi @@ -208,10 +208,10 @@ cdns,read-delay = <5>; /* Tighten timings for 200 MHz (T=5ns) */ - cdns,tshsl-ns = <30>; /* CS# high pulse width */ - cdns,tsd2d-ns = <30>; /* Delay between back-to-back transfers */ - cdns,tchsh-ns = <10>; /* CS# hold time */ - cdns,tslch-ns = <10>; /* CS# setup time */ + cdns,tshsl-ns = <200>; /* CS# high pulse width (increased for stability) */ + cdns,tsd2d-ns = <200>; /* Delay between back-to-back transfers */ + cdns,tchsh-ns = <3>; /* CS# hold time */ + cdns,tslch-ns = <3>; /* CS# setup time */ spi-rx-bus-width = <8>; spi-tx-bus-width = <8>;