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drivers: usb: fsl: Define usb control register mask for w1c bits

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Define and use CONTROL_REGISTER_W1C_MASK to make sure that
w1c bits of usb control register do not get reset while
writing any other bit

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Nikhil Badola
2015-07-14 17:28:47 +05:30
committed by Greg Kroah-Hartman
parent f4fdfaa280
commit 4e02bea82b
2 changed files with 17 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/usb/host/ehci-fsl.c
+14 -7
View File
@@ -127,14 +127,16 @@ static int fsl_ehci_drv_probe(struct platform_device *pdev)
/* Enable USB controller, 83xx or 8536 */ /* Enable USB controller, 83xx or 8536 */
if (pdata->have_sysif_regs && pdata->controller_ver < FSL_USB_VER_1_6) if (pdata->have_sysif_regs && pdata->controller_ver < FSL_USB_VER_1_6)
setbits32(hcd->regs + FSL_SOC_USB_CTRL, 0x4); clrsetbits_be32(hcd->regs + FSL_SOC_USB_CTRL,
CONTROL_REGISTER_W1C_MASK, 0x4);
/* /*
* Enable UTMI phy and program PTS field in UTMI mode before asserting * Enable UTMI phy and program PTS field in UTMI mode before asserting
* controller reset for USB Controller version 2.5 * controller reset for USB Controller version 2.5
*/ */
if (pdata->has_fsl_erratum_a007792) { if (pdata->has_fsl_erratum_a007792) {
writel_be(CTRL_UTMI_PHY_EN, hcd->regs + FSL_SOC_USB_CTRL); clrsetbits_be32(hcd->regs + FSL_SOC_USB_CTRL,
CONTROL_REGISTER_W1C_MASK, CTRL_UTMI_PHY_EN);
writel(PORT_PTS_UTMI, hcd->regs + FSL_SOC_USB_PORTSC1); writel(PORT_PTS_UTMI, hcd->regs + FSL_SOC_USB_PORTSC1);
} }
@@ -200,8 +202,10 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
case FSL_USB2_PHY_ULPI: case FSL_USB2_PHY_ULPI:
if (pdata->have_sysif_regs && pdata->controller_ver) { if (pdata->have_sysif_regs && pdata->controller_ver) {
/* controller version 1.6 or above */ /* controller version 1.6 or above */
clrbits32(non_ehci + FSL_SOC_USB_CTRL, UTMI_PHY_EN); clrbits32(non_ehci + FSL_SOC_USB_CTRL,
setbits32(non_ehci + FSL_SOC_USB_CTRL, CONTROL_REGISTER_W1C_MASK | UTMI_PHY_EN);
clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
CONTROL_REGISTER_W1C_MASK,
ULPI_PHY_CLK_SEL | USB_CTRL_USB_EN); ULPI_PHY_CLK_SEL | USB_CTRL_USB_EN);
} }
portsc |= PORT_PTS_ULPI; portsc |= PORT_PTS_ULPI;
@@ -216,13 +220,15 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
case FSL_USB2_PHY_UTMI_DUAL: case FSL_USB2_PHY_UTMI_DUAL:
if (pdata->have_sysif_regs && pdata->controller_ver) { if (pdata->have_sysif_regs && pdata->controller_ver) {
/* controller version 1.6 or above */ /* controller version 1.6 or above */
setbits32(non_ehci + FSL_SOC_USB_CTRL, UTMI_PHY_EN); clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
CONTROL_REGISTER_W1C_MASK, UTMI_PHY_EN);
mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI PHY CLK to mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI PHY CLK to
become stable - 10ms*/ become stable - 10ms*/
} }
/* enable UTMI PHY */ /* enable UTMI PHY */
if (pdata->have_sysif_regs) if (pdata->have_sysif_regs)
setbits32(non_ehci + FSL_SOC_USB_CTRL, clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
CONTROL_REGISTER_W1C_MASK,
CTRL_UTMI_PHY_EN); CTRL_UTMI_PHY_EN);
portsc |= PORT_PTS_UTMI; portsc |= PORT_PTS_UTMI;
break; break;
@@ -245,7 +251,8 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]); ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]);
if (phy_mode != FSL_USB2_PHY_ULPI && pdata->have_sysif_regs) if (phy_mode != FSL_USB2_PHY_ULPI && pdata->have_sysif_regs)
setbits32(non_ehci + FSL_SOC_USB_CTRL, USB_CTRL_USB_EN); clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
CONTROL_REGISTER_W1C_MASK, USB_CTRL_USB_EN);
return 0; return 0;
} }
drivers/usb/host/ehci-fsl.h
+1
View File
@@ -52,6 +52,7 @@
#define SNOOP_SIZE_2GB 0x1e #define SNOOP_SIZE_2GB 0x1e
/* control Register Bit Masks */ /* control Register Bit Masks */
#define CONTROL_REGISTER_W1C_MASK 0x00020000 /* W1C: PHY_CLK_VALID */
#define ULPI_INT_EN (1<<0) #define ULPI_INT_EN (1<<0)
#define WU_INT_EN (1<<1) #define WU_INT_EN (1<<1)
#define USB_CTRL_USB_EN (1<<2) #define USB_CTRL_USB_EN (1<<2)