drm/amdgpu: retire UMC v12 mca_addr_to_pa
RAS TA will handle it, the function is useless. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Tao Zhou
Alex Deucher
parent
f6ac084236
commit
4b0cb230bd
@ -1457,7 +1457,6 @@ static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev)
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adev->umc.channel_offs = UMC_V12_0_PER_CHANNEL_OFFSET;
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adev->umc.active_mask = adev->aid_mask;
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adev->umc.retire_unit = UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL;
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adev->umc.channel_idx_tbl = &umc_v12_0_channel_idx_tbl[0][0][0];
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if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu)
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adev->umc.ras = &umc_v12_0_ras;
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break;
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@ -28,28 +28,6 @@
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#include "umc/umc_12_0_0_sh_mask.h"
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#include "mp/mp_13_0_6_sh_mask.h"
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const uint32_t
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umc_v12_0_channel_idx_tbl[]
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[UMC_V12_0_UMC_INSTANCE_NUM]
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[UMC_V12_0_CHANNEL_INSTANCE_NUM] = {
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{{3, 7, 11, 15, 2, 6, 10, 14}, {1, 5, 9, 13, 0, 4, 8, 12},
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{19, 23, 27, 31, 18, 22, 26, 30}, {17, 21, 25, 29, 16, 20, 24, 28}},
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{{47, 43, 39, 35, 46, 42, 38, 34}, {45, 41, 37, 33, 44, 40, 36, 32},
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{63, 59, 55, 51, 62, 58, 54, 50}, {61, 57, 53, 49, 60, 56, 52, 48}},
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{{79, 75, 71, 67, 78, 74, 70, 66}, {77, 73, 69, 65, 76, 72, 68, 64},
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{95, 91, 87, 83, 94, 90, 86, 82}, {93, 89, 85, 81, 92, 88, 84, 80}},
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{{99, 103, 107, 111, 98, 102, 106, 110}, {97, 101, 105, 109, 96, 100, 104, 108},
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{115, 119, 123, 127, 114, 118, 122, 126}, {113, 117, 121, 125, 112, 116, 120, 124}}
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};
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/* mapping of MCA error address to normalized address */
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static const uint32_t umc_v12_0_ma2na_mapping[] = {
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0, 5, 6, 8, 9, 14, 12, 13,
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10, 11, 15, 16, 17, 18, 19, 20,
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21, 22, 23, 24, 25, 26, 27, 28,
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24, 7, 29, 30,
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};
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static inline uint64_t get_umc_v12_0_reg_offset(struct amdgpu_device *adev,
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uint32_t node_inst,
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uint32_t umc_inst,
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@ -192,79 +170,6 @@ static void umc_v12_0_query_ras_error_count(struct amdgpu_device *adev,
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umc_v12_0_reset_error_count(adev);
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}
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static bool umc_v12_0_bit_wise_xor(uint32_t val)
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{
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bool result = 0;
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int i;
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for (i = 0; i < 32; i++)
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result = result ^ ((val >> i) & 0x1);
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return result;
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}
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static void umc_v12_0_mca_addr_to_pa(struct amdgpu_device *adev,
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uint64_t err_addr, uint32_t ch_inst, uint32_t umc_inst,
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uint32_t node_inst,
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struct ta_ras_query_address_output *addr_out)
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{
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uint32_t channel_index, i;
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uint64_t na, soc_pa;
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uint32_t bank_hash0, bank_hash1, bank_hash2, bank_hash3, col, row;
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uint32_t bank0, bank1, bank2, bank3, bank;
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bank_hash0 = (err_addr >> UMC_V12_0_MCA_B0_BIT) & 0x1ULL;
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bank_hash1 = (err_addr >> UMC_V12_0_MCA_B1_BIT) & 0x1ULL;
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bank_hash2 = (err_addr >> UMC_V12_0_MCA_B2_BIT) & 0x1ULL;
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bank_hash3 = (err_addr >> UMC_V12_0_MCA_B3_BIT) & 0x1ULL;
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col = (err_addr >> 1) & 0x1fULL;
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row = (err_addr >> 10) & 0x3fffULL;
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/* apply bank hash algorithm */
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bank0 =
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bank_hash0 ^ (UMC_V12_0_XOR_EN0 &
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(umc_v12_0_bit_wise_xor(col & UMC_V12_0_COL_XOR0) ^
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(umc_v12_0_bit_wise_xor(row & UMC_V12_0_ROW_XOR0))));
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bank1 =
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bank_hash1 ^ (UMC_V12_0_XOR_EN1 &
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(umc_v12_0_bit_wise_xor(col & UMC_V12_0_COL_XOR1) ^
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(umc_v12_0_bit_wise_xor(row & UMC_V12_0_ROW_XOR1))));
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bank2 =
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bank_hash2 ^ (UMC_V12_0_XOR_EN2 &
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(umc_v12_0_bit_wise_xor(col & UMC_V12_0_COL_XOR2) ^
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(umc_v12_0_bit_wise_xor(row & UMC_V12_0_ROW_XOR2))));
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bank3 =
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bank_hash3 ^ (UMC_V12_0_XOR_EN3 &
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(umc_v12_0_bit_wise_xor(col & UMC_V12_0_COL_XOR3) ^
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(umc_v12_0_bit_wise_xor(row & UMC_V12_0_ROW_XOR3))));
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bank = bank0 | (bank1 << 1) | (bank2 << 2) | (bank3 << 3);
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err_addr &= ~0x3c0ULL;
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err_addr |= (bank << UMC_V12_0_MCA_B0_BIT);
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na = 0x0;
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/* convert mca error address to normalized address */
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for (i = 1; i < ARRAY_SIZE(umc_v12_0_ma2na_mapping); i++)
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na |= ((err_addr >> i) & 0x1ULL) << umc_v12_0_ma2na_mapping[i];
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channel_index =
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adev->umc.channel_idx_tbl[node_inst * adev->umc.umc_inst_num *
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adev->umc.channel_inst_num +
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umc_inst * adev->umc.channel_inst_num +
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ch_inst];
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/* translate umc channel address to soc pa, 3 parts are included */
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soc_pa = ADDR_OF_32KB_BLOCK(na) |
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ADDR_OF_256B_BLOCK(channel_index) |
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OFFSET_IN_256B_BLOCK(na);
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/* the umc channel bits are not original values, they are hashed */
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UMC_V12_0_SET_CHANNEL_HASH(channel_index, soc_pa);
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addr_out->pa.pa = soc_pa;
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addr_out->pa.bank = bank;
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addr_out->pa.channel_idx = channel_index;
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}
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static void umc_v12_0_convert_error_address(struct amdgpu_device *adev,
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struct ras_err_data *err_data,
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struct ta_ras_query_address_input *addr_in)
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@ -275,10 +180,12 @@ static void umc_v12_0_convert_error_address(struct amdgpu_device *adev,
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err_addr = addr_in->ma.err_addr;
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addr_in->addr_type = TA_RAS_MCA_TO_PA;
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if (psp_ras_query_address(&adev->psp, addr_in, &addr_out))
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/* fallback to old path if fail to get pa from psp */
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umc_v12_0_mca_addr_to_pa(adev, err_addr, addr_in->ma.ch_inst,
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addr_in->ma.umc_inst, addr_in->ma.node_inst, &addr_out);
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if (psp_ras_query_address(&adev->psp, addr_in, &addr_out)) {
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dev_warn(adev->dev, "Failed to query RAS physical address for 0x%llx",
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err_addr);
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return;
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}
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soc_pa = addr_out.pa.pa;
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bank = addr_out.pa.bank;
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@ -55,67 +55,12 @@
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#define UMC_V12_0_NA_MAP_PA_NUM 8
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/* R13 bit shift should be considered, double the number */
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#define UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL (UMC_V12_0_NA_MAP_PA_NUM * 2)
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/* bank bits in MCA error address */
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#define UMC_V12_0_MCA_B0_BIT 6
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#define UMC_V12_0_MCA_B1_BIT 7
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#define UMC_V12_0_MCA_B2_BIT 8
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#define UMC_V12_0_MCA_B3_BIT 9
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/* column bits in SOC physical address */
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#define UMC_V12_0_PA_C2_BIT 15
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#define UMC_V12_0_PA_C4_BIT 21
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/* row bits in SOC physical address */
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#define UMC_V12_0_PA_R13_BIT 35
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/* channel index bits in SOC physical address */
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#define UMC_V12_0_PA_CH4_BIT 12
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#define UMC_V12_0_PA_CH5_BIT 13
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#define UMC_V12_0_PA_CH6_BIT 14
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/* bank hash settings */
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#define UMC_V12_0_XOR_EN0 1
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#define UMC_V12_0_XOR_EN1 1
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#define UMC_V12_0_XOR_EN2 1
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#define UMC_V12_0_XOR_EN3 1
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#define UMC_V12_0_COL_XOR0 0x0
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#define UMC_V12_0_COL_XOR1 0x0
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#define UMC_V12_0_COL_XOR2 0x800
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#define UMC_V12_0_COL_XOR3 0x1000
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#define UMC_V12_0_ROW_XOR0 0x11111
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#define UMC_V12_0_ROW_XOR1 0x22222
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#define UMC_V12_0_ROW_XOR2 0x4444
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#define UMC_V12_0_ROW_XOR3 0x8888
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/* channel hash settings */
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#define UMC_V12_0_HASH_4K 0
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#define UMC_V12_0_HASH_64K 1
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#define UMC_V12_0_HASH_2M 1
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#define UMC_V12_0_HASH_1G 1
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#define UMC_V12_0_HASH_1T 1
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/* XOR some bits of PA into CH4~CH6 bits (bits 12~14 of PA),
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* hash bit is only effective when related setting is enabled
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*/
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#define UMC_V12_0_CHANNEL_HASH_CH4(channel_idx, pa) ((((channel_idx) >> 5) & 0x1) ^ \
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(((pa) >> 20) & 0x1ULL & UMC_V12_0_HASH_64K) ^ \
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(((pa) >> 27) & 0x1ULL & UMC_V12_0_HASH_2M) ^ \
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(((pa) >> 34) & 0x1ULL & UMC_V12_0_HASH_1G) ^ \
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(((pa) >> 41) & 0x1ULL & UMC_V12_0_HASH_1T))
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#define UMC_V12_0_CHANNEL_HASH_CH5(channel_idx, pa) ((((channel_idx) >> 6) & 0x1) ^ \
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(((pa) >> 21) & 0x1ULL & UMC_V12_0_HASH_64K) ^ \
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(((pa) >> 28) & 0x1ULL & UMC_V12_0_HASH_2M) ^ \
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(((pa) >> 35) & 0x1ULL & UMC_V12_0_HASH_1G) ^ \
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(((pa) >> 42) & 0x1ULL & UMC_V12_0_HASH_1T))
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#define UMC_V12_0_CHANNEL_HASH_CH6(channel_idx, pa) ((((channel_idx) >> 4) & 0x1) ^ \
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(((pa) >> 19) & 0x1ULL & UMC_V12_0_HASH_64K) ^ \
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(((pa) >> 26) & 0x1ULL & UMC_V12_0_HASH_2M) ^ \
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(((pa) >> 33) & 0x1ULL & UMC_V12_0_HASH_1G) ^ \
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(((pa) >> 40) & 0x1ULL & UMC_V12_0_HASH_1T) ^ \
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(((pa) >> 47) & 0x1ULL & UMC_V12_0_HASH_4K))
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#define UMC_V12_0_SET_CHANNEL_HASH(channel_idx, pa) do { \
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(pa) &= ~(0x7ULL << UMC_V12_0_PA_CH4_BIT); \
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(pa) |= (UMC_V12_0_CHANNEL_HASH_CH4(channel_idx, pa) << UMC_V12_0_PA_CH4_BIT); \
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(pa) |= (UMC_V12_0_CHANNEL_HASH_CH5(channel_idx, pa) << UMC_V12_0_PA_CH5_BIT); \
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(pa) |= (UMC_V12_0_CHANNEL_HASH_CH6(channel_idx, pa) << UMC_V12_0_PA_CH6_BIT); \
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} while (0)
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#define MCA_IPID_LO_2_UMC_CH(_ipid_lo) (((((_ipid_lo) >> 20) & 0x1) * 4) + \
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(((_ipid_lo) >> 12) & 0xF))
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@ -127,11 +72,6 @@ bool umc_v12_0_is_correctable_error(struct amdgpu_device *adev, uint64_t mc_umc_
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typedef bool (*check_error_type_func)(struct amdgpu_device *adev, uint64_t mc_umc_status);
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extern const uint32_t
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umc_v12_0_channel_idx_tbl[]
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[UMC_V12_0_UMC_INSTANCE_NUM]
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[UMC_V12_0_CHANNEL_INSTANCE_NUM];
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extern struct amdgpu_umc_ras umc_v12_0_ras;
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#endif
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