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[MIPS] Fix "no space between function name and open parenthesis" warnings.

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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
2007-10-11 23:46:15 +01:00
parent 10cc352907
commit 49a89efbbb
104 changed files with 842 additions and 842 deletions
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arch/mips/kernel/traps.c
+13 -13
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@@ -627,7 +627,7 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
lose_fpu(1);
/* Run the emulator */
sig = fpu_emulator_cop1Handler (regs, &current->thread.fpu, 1);
sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1);
/*
* We can't allow the emulated instruction to leave any of
@@ -1165,11 +1165,11 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
if (cpu_has_veic) {
if (board_bind_eic_interrupt)
board_bind_eic_interrupt (n, srs);
board_bind_eic_interrupt(n, srs);
} else if (cpu_has_vint) {
/* SRSMap is only defined if shadow sets are implemented */
if (mips_srs_max() > 1)
change_c0_srsmap (0xf << n*4, srs << n*4);
change_c0_srsmap(0xf << n*4, srs << n*4);
}
if (srs == 0) {
@@ -1198,10 +1198,10 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
* Sigh... panicing won't help as the console
* is probably not configured :(
*/
panic ("VECTORSPACING too small");
panic("VECTORSPACING too small");
}
memcpy (b, &except_vec_vi, handler_len);
memcpy(b, &except_vec_vi, handler_len);
#ifdef CONFIG_MIPS_MT_SMTC
BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */
@@ -1370,9 +1370,9 @@ void __init per_cpu_trap_init(void)
#endif /* CONFIG_MIPS_MT_SMTC */
if (cpu_has_veic || cpu_has_vint) {
write_c0_ebase (ebase);
write_c0_ebase(ebase);
/* Setting vector spacing enables EI/VI mode */
change_c0_intctl (0x3e0, VECTORSPACING);
change_c0_intctl(0x3e0, VECTORSPACING);
}
if (cpu_has_divec) {
if (cpu_has_mipsmt) {
@@ -1390,8 +1390,8 @@ void __init per_cpu_trap_init(void)
* o read IntCtl.IPPCI to determine the performance counter interrupt
*/
if (cpu_has_mips_r2) {
cp0_compare_irq = (read_c0_intctl () >> 29) & 7;
cp0_perfcount_irq = (read_c0_intctl () >> 26) & 7;
cp0_compare_irq = (read_c0_intctl() >> 29) & 7;
cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7;
if (cp0_perfcount_irq == cp0_compare_irq)
cp0_perfcount_irq = -1;
} else {
@@ -1429,7 +1429,7 @@ void __init per_cpu_trap_init(void)
}
/* Install CPU exception handler */
void __init set_handler (unsigned long offset, void *addr, unsigned long size)
void __init set_handler(unsigned long offset, void *addr, unsigned long size)
{
memcpy((void *)(ebase + offset), addr, size);
flush_icache_range(ebase + offset, ebase + offset + size);
@@ -1439,7 +1439,7 @@ static char panic_null_cerr[] __initdata =
"Trying to set NULL cache error exception handler";
/* Install uncached CPU exception handler */
void __init set_uncached_handler (unsigned long offset, void *addr, unsigned long size)
void __init set_uncached_handler(unsigned long offset, void *addr, unsigned long size)
{
#ifdef CONFIG_32BIT
unsigned long uncached_ebase = KSEG1ADDR(ebase);
@@ -1470,7 +1470,7 @@ void __init trap_init(void)
unsigned long i;
if (cpu_has_veic || cpu_has_vint)
ebase = (unsigned long) alloc_bootmem_low_pages (0x200 + VECTORSPACING*64);
ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64);
else
ebase = CAC_BASE;
@@ -1496,7 +1496,7 @@ void __init trap_init(void)
* destination.
*/
if (cpu_has_ejtag && board_ejtag_handler_setup)
board_ejtag_handler_setup ();
board_ejtag_handler_setup();
/*
* Only some CPUs have the watch exceptions.