Merge branches 'intel/vt-d', 'amd/amd-vi' and 'iommufd/arm-smmuv3-nested' into next
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@@ -492,15 +492,50 @@ struct iommu_hw_info_vtd {
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__aligned_u64 ecap_reg;
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};
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/**
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* struct iommu_hw_info_arm_smmuv3 - ARM SMMUv3 hardware information
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* (IOMMU_HW_INFO_TYPE_ARM_SMMUV3)
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*
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* @flags: Must be set to 0
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* @__reserved: Must be 0
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* @idr: Implemented features for ARM SMMU Non-secure programming interface
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* @iidr: Information about the implementation and implementer of ARM SMMU,
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* and architecture version supported
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* @aidr: ARM SMMU architecture version
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*
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* For the details of @idr, @iidr and @aidr, please refer to the chapters
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* from 6.3.1 to 6.3.6 in the SMMUv3 Spec.
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*
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* User space should read the underlying ARM SMMUv3 hardware information for
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* the list of supported features.
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*
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* Note that these values reflect the raw HW capability, without any insight if
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* any required kernel driver support is present. Bits may be set indicating the
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* HW has functionality that is lacking kernel software support, such as BTM. If
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* a VMM is using this information to construct emulated copies of these
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* registers it should only forward bits that it knows it can support.
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*
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* In future, presence of required kernel support will be indicated in flags.
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*/
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struct iommu_hw_info_arm_smmuv3 {
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__u32 flags;
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__u32 __reserved;
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__u32 idr[6];
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__u32 iidr;
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__u32 aidr;
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};
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/**
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* enum iommu_hw_info_type - IOMMU Hardware Info Types
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* @IOMMU_HW_INFO_TYPE_NONE: Used by the drivers that do not report hardware
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* info
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* @IOMMU_HW_INFO_TYPE_INTEL_VTD: Intel VT-d iommu info type
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* @IOMMU_HW_INFO_TYPE_ARM_SMMUV3: ARM SMMUv3 iommu info type
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*/
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enum iommu_hw_info_type {
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IOMMU_HW_INFO_TYPE_NONE = 0,
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IOMMU_HW_INFO_TYPE_INTEL_VTD = 1,
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IOMMU_HW_INFO_TYPE_ARM_SMMUV3 = 2,
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};
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/**
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@@ -35,7 +35,7 @@
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#define VFIO_EEH 5
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/* Two-stage IOMMU */
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#define VFIO_TYPE1_NESTING_IOMMU 6 /* Implies v2 */
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#define __VFIO_RESERVED_TYPE1_NESTING_IOMMU 6 /* Implies v2 */
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#define VFIO_SPAPR_TCE_v2_IOMMU 7
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