From 9e999a702701b621be7427a6f2cc29bd04defa7f Mon Sep 17 00:00:00 2001 From: Sai Sree Kartheek Adivi Date: Mon, 20 Jan 2025 13:24:42 +0530 Subject: [PATCH 01/32] arm64: dts: ti: k3-am62a-mcu: enable mcu domain pinmux Enable mcu domain pinmux by default to be able to access mcu domain peripherals from main domain. This also makes it consistent with the rest of the k3 platforms where mcu domain pinmux is enabled by default. Signed-off-by: Sai Sree Kartheek Adivi Link: https://lore.kernel.org/r/20250120075442.181191-1-s-adivi@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi index 0469c766b769..9ed9d703ff24 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi @@ -12,7 +12,6 @@ #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; - status = "disabled"; }; mcu_esm: esm@4100000 { From 8a3629a6a9e52b30c55910b26c9c0dbc376f9d29 Mon Sep 17 00:00:00 2001 From: Jayesh Choudhary Date: Fri, 10 Jan 2025 16:27:53 +0530 Subject: [PATCH 02/32] arm64: dts: ti: k3-j784s4-evm-quad-port-eth-exp1: Remove duplicate hogs The j784s4-evm board dts now has the gpio hogs for MUX2 after integration of audio support. Remove duplicate gpio-hogs from the overlay dtso to prevent mux probe failures leading to can-phy3 deferred probe: 'gpio-mux mux-controller: probe with driver gpio-mux failed with error -16' Fixes: 479112c9f531 ("arm64: dts: ti: k3-j784s4-evm: Enable analog audio support") Reviewed-by: Siddharth Vadapalli Signed-off-by: Jayesh Choudhary Link: https://lore.kernel.org/r/20250110105753.223049-1-j-choudhary@ti.com Signed-off-by: Vignesh Raghavendra --- .../boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso | 7 ------- 1 file changed, 7 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso b/arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso index dcd2c7c39ec3..c1f9573557d0 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso @@ -102,13 +102,6 @@ gpios = <16 GPIO_ACTIVE_HIGH>; output-low; }; - - /* Toggle MUX2 for MDIO lines */ - mux-sel-hog { - gpio-hog; - gpios = <13 GPIO_ACTIVE_HIGH>, <14 GPIO_ACTIVE_HIGH>, <15 GPIO_ACTIVE_HIGH>; - output-high; - }; }; &main_pmx0 { From bc8d9e6b5821c40ab5dd3a81e096cb114939de50 Mon Sep 17 00:00:00 2001 From: Hrushikesh Salunke Date: Thu, 16 Jan 2025 18:27:26 +0530 Subject: [PATCH 03/32] arm64: dts: ti: k3-j722s-evm: Fix USB2.0_MUX_SEL to select Type-C J722S SOC has two usb controllers USB0 and USB1. USB0 is brought out on the EVM as a stacked USB connector which has one Type-A and one Type-C port. These Type-A and Type-C ports are connected to MUX so only one of them can be enabled at a time. Commit under Fixes, tries to enable the USB0 instance of USB to interface with the Type-C port via the USB hub, by configuring the USB2.0_MUX_SEL to GPIO_ACTIVE_HIGH. But it is observed on J722S-EVM that Type-A port is enabled instead of Type-C port. Fix this by setting USB2.0_MUX_SEL to GPIO_ACTIVE_LOW to enable Type-C port. Fixes: 485705df5d5f ("arm64: dts: ti: k3-j722s: Enable PCIe and USB support on J722S-EVM") Signed-off-by: Hrushikesh Salunke Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20250116125726.2549489-1-h-salunke@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts index d184e9c1a0a5..adee69607fdb 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -590,7 +590,7 @@ p05-hog { /* P05 - USB2.0_MUX_SEL */ gpio-hog; - gpios = <5 GPIO_ACTIVE_HIGH>; + gpios = <5 GPIO_ACTIVE_LOW>; output-high; }; From e7ee00e314da736b00ebb26405f8e2cab84cfa22 Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Wed, 22 Jan 2025 18:11:48 +0530 Subject: [PATCH 04/32] arm64: dts: ti: k3-am62a7-sk: Add boot phase tag for USB0 The USB0 instance of USB on AM62Ax SoC can be used for USB DFU boot. This requires USB0 to be enabled at all stages of the boot process. In order to support USB DFU boot on AM62A7-SK, add the "bootph-all" property to USB0. Signed-off-by: Siddharth Vadapalli Link: https://lore.kernel.org/r/20250122124223.1118789-2-s-vadapalli@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts index a6f0d87a50d8..afe654cf1c22 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -655,6 +655,7 @@ }; &usb0 { + bootph-all; usb-role-switch; port { From 732c4cffe463f222f7f694d469d1f730f4a3adab Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Wed, 22 Jan 2025 18:11:49 +0530 Subject: [PATCH 05/32] arm64: dts: ti: k3-am62p5-sk: Add boot phase tag for USB0 The USB0 instance of USB on AM62Px SoC can be used for USB DFU boot. This requires USB0 to be enabled at all stages of the boot process. In order to support USB DFU boot on AM62P5-SK, add the "bootph-all" property to USB0. Signed-off-by: Siddharth Vadapalli Link: https://lore.kernel.org/r/20250122124223.1118789-3-s-vadapalli@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts index ad71d2f27f53..20ceb1c11d8e 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -519,6 +519,7 @@ }; &usb0 { + bootph-all; usb-role-switch; port { From 398898f9cca1a19a83184430c675562680e57c7b Mon Sep 17 00:00:00 2001 From: Keerthy Date: Tue, 18 Feb 2025 10:52:48 +0530 Subject: [PATCH 06/32] arm64: dts: ti: k3-j784s4-j742s2-main-common: Correct the GICD size Currently we get the warning: "GICv3: [Firmware Bug]: GICR region 0x0000000001900000 has overlapping address" As per TRM GICD is 64 KB. Fix it by correcting the size of GICD. Cc: stable@vger.kernel.org Fixes: 9cc161a4509c ("arm64: dts: ti: Refactor J784s4 SoC files to a common file") Link: https://lore.kernel.org/r/20250218052248.4734-1-j-keerthy@ti.com Signed-off-by: Keerthy Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi index 83bbf94b58d1..3b72fca158ad 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi @@ -193,7 +193,7 @@ ranges; #interrupt-cells = <3>; interrupt-controller; - reg = <0x00 0x01800000 0x00 0x200000>, /* GICD */ + reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ <0x00 0x01900000 0x00 0x100000>, /* GICR */ <0x00 0x6f000000 0x00 0x2000>, /* GICC */ <0x00 0x6f010000 0x00 0x1000>, /* GICH */ From 7139df64e7c13c079b754476355c62b490213055 Mon Sep 17 00:00:00 2001 From: Stefan Eichenberger Date: Mon, 17 Feb 2025 15:46:04 +0100 Subject: [PATCH 07/32] arm64: dts: ti: k3-am62-verdin-dahlia: add Microphone Jack to sound card The simple-audio-card's microphone widget currently connects to the headphone jack. Routing the microphone input to the microphone jack allows for independent operation of the microphone and headphones. This resolves the following boot-time kernel log message, which indicated a conflict when the microphone and headphone functions were not separated: debugfs: File 'Headphone Jack' in directory 'dapm' already present! Fixes: f5bf894c865b ("arm64: dts: ti: verdin-am62: dahlia: add sound card") Signed-off-by: Stefan Eichenberger Reviewed-by: Francesco Dolcini Reviewed-by: Jai Luthra Link: https://lore.kernel.org/r/20250217144643.178222-1-eichest@gmail.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi index 9202181fbd65..fcc4cb2e9389 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi @@ -28,10 +28,10 @@ "Headphone Jack", "HPOUTR", "IN2L", "Line In Jack", "IN2R", "Line In Jack", - "Headphone Jack", "MICBIAS", - "IN1L", "Headphone Jack"; + "Microphone Jack", "MICBIAS", + "IN1L", "Microphone Jack"; simple-audio-card,widgets = - "Microphone", "Headphone Jack", + "Microphone", "Microphone Jack", "Headphone", "Headphone Jack", "Line", "Line In Jack"; From d9f17c11650c205fd4802033a5e880bf79662ace Mon Sep 17 00:00:00 2001 From: Udit Kumar Date: Sat, 15 Feb 2025 12:30:59 +0530 Subject: [PATCH 08/32] arm64: dts: ti: k3-j721s2-som-p0: Add flash partition details When used as boot device, OSPI flash hosts different boot binaries and rootfs etc. So Add partition details for images hosted on OSPI flash. Signed-off-by: Udit Kumar Link: https://lore.kernel.org/r/20250215070059.1593489-1-u-kumar1@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 41 ++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi index b3a0385ed3d8..54fc5c4f8c3f 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi @@ -448,6 +448,47 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "ospi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "ospi.env.backup"; + reg = <0x6c0000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; }; }; From 34887f2dab33b30de2730005681c796114fba351 Mon Sep 17 00:00:00 2001 From: Vibhore Vardhan Date: Fri, 14 Feb 2025 17:22:12 -0600 Subject: [PATCH 09/32] arm64: dts: ti: k3-am62a7-sk: Add alias for RTC Adds alias for SoC RTC so that it gets assigned rtc0. PMIC node is assigned rtc1 so that PMIC RTC gets probed as rtc1. This makes it consistent for testing rtcwake with other AM62 devices where rtc0 is SoC RTC. Signed-off-by: Vibhore Vardhan [k-willis@ti.com: Reworded commit message] Reviewed-by: Dhruva Gole Signed-off-by: Kendall Willis Link: https://lore.kernel.org/r/20250214232212.1158505-1-k-willis@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts index afe654cf1c22..c5b199bb3f8e 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -22,6 +22,8 @@ serial3 = &main_uart1; mmc0 = &sdhci0; mmc1 = &sdhci1; + rtc0 = &wkup_rtc0; + rtc1 = &tps659312; }; chosen { From b0de0b2de409d99408c0f3a38af841ae3bcaa225 Mon Sep 17 00:00:00 2001 From: Vibhore Vardhan Date: Wed, 12 Feb 2025 15:52:48 -0600 Subject: [PATCH 10/32] arm64: dts: ti: k3-am62p-j722s-common-wakeup: Configure ti-sysc for wkup_uart0 Similar to the TI K3-AM62x Soc commit ce27f7f9e328c8582a169f97f1466976561f1 ("arm64: dts: ti: k3-am62-wakeup: Configure ti-sysc for wkup_uart0") The devices in the wkup domain are capable of waking up the system from suspend. We can configure the wkup domain devices in a generic way using the ti-sysc interconnect target module driver like we have done with the earlier TI SoCs. As ti-sysc manages the SYSCONFIG related registers independent of the child hardware device, the wake-up configuration is also set even if wkup_uart0 is reserved by sysfw. The wkup_uart0 device has interconnect target module register mapping like dra7 wkup uart. There is a 1 MB interconnect target range with one uart IP block in the target module. The power domain and clock affects the whole interconnect target module. Note we change the functional clock name to follow the ti-sysc binding and use "fck" instead of "fclk". Also note that we need to disable the target module reset as noted by Markus. Otherwise the sysfw using wkup_uart0 can get confused on some devices leading to boot time issues such as mbox timeouts. Signed-off-by: Vibhore Vardhan Signed-off-by: Kendall Willis Reviewed-by: Dhruva Gole Link: https://lore.kernel.org/r/20250212215248.746838-1-k-willis@ti.com Signed-off-by: Vignesh Raghavendra --- .../dts/ti/k3-am62p-j722s-common-wakeup.dtsi | 36 +++++++++++++++---- 1 file changed, 29 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi index 6f32135f00a5..6757b37a9de3 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi @@ -2,9 +2,11 @@ /* * Device Tree file for the WAKEUP domain peripherals shared by AM62P and J722S * - * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2025 Texas Instruments Incorporated - https://www.ti.com/ */ +#include + &cbass_wakeup { wkup_conf: bus@43000000 { compatible = "simple-bus"; @@ -41,14 +43,34 @@ }; }; - wkup_uart0: serial@2b300000 { - compatible = "ti,am64-uart", "ti,am654-uart"; - reg = <0x00 0x2b300000 0x00 0x100>; - interrupts = ; + target-module@2b300050 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0 0x2b300050 0 0x4>, + <0 0x2b300054 0 0x4>, + <0 0x2b300058 0 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + ti,no-reset-on-init; power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 114 0>; - clock-names = "fclk"; - status = "disabled"; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x2b300000 0x100000>; + + wkup_uart0: serial@0 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0 0x100>; + interrupts = ; + status = "disabled"; + }; }; wkup_i2c0: i2c@2b200000 { From 59ac3f9f54db76f676ac5db05054586956c57e39 Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Sun, 9 Feb 2025 13:47:32 +0530 Subject: [PATCH 11/32] arm64: dts: ti: k3-j721e-common-proc-board: Add boot phase tag to SERDES3 The USB0 instance of USB on J721E SoC can be used for USB DFU boot. Since the USB Type-C interface on the J721E-EVM is connected to USB0 via SERDES3, supporting USB DFU boot requires SERDES3 link associated with USB0 to be functional at all stages of the USB DFU boot process. Thus, add the "bootph-all" boot phase tag to "serdes3_usb_link" device-tree node. Signed-off-by: Siddharth Vadapalli Link: https://lore.kernel.org/r/20250209081738.1874749-2-s-vadapalli@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 4c1e02a4e7a2..4421852161dd 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -540,6 +540,7 @@ #phy-cells = <0>; cdns,phy-type = ; resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>; + bootph-all; }; }; From 871c73229bd276fbdb43c42fb3f5a25bcd8a9c85 Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Sun, 9 Feb 2025 13:47:33 +0530 Subject: [PATCH 12/32] arm64: dts: ti: k3-j721e-sk: Add boot phase tag to SERDES3 The USB0 instance of USB on J721E SoC can be used for USB DFU boot. Since the USB Type-C interface on the J721E-SK is connected to USB0 via SERDES3, supporting USB DFU boot requires SERDES3 link associated with USB0 to be functional at all stages of the USB DFU boot process. Thus, add the "bootph-all" boot phase tag to "serdes3_usb_link" device-tree node. Signed-off-by: Siddharth Vadapalli Link: https://lore.kernel.org/r/20250209081738.1874749-3-s-vadapalli@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index 69b3d1ed8a21..440ef57be294 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -1040,6 +1040,7 @@ #phy-cells = <0>; cdns,phy-type = ; resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>; + bootph-all; }; }; From 47ab49247b68423c399717f2c8623e7f5d70153e Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 31 Jan 2025 11:35:08 -0600 Subject: [PATCH 13/32] arm64: dts: ti: k3-am625-beagleplay: Reserve 128MiB of global CMA In the same lines of commit 9e8560556f9c ("arm64: dts: ti: k3-am62x-sk-common: Reserve 128MiB of global CMA"), reserve global CMA pool for: LCD Display: 16MiB, HDMI (1080p): 16MiB, GPU: 16MiB, CSI2 1 1080p sensor: 32MiB with a 32MiB set for other peripherals and a 16MiB buffer. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20250131173508.1338842-1-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts index 75c80290b12a..a5469f2712f0 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts @@ -65,6 +65,14 @@ pmsg-size = <0x8000>; }; + /* global cma region */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x00 0x8000000>; + linux,cma-default; + }; + secure_tfa_ddr: tfa@9e780000 { reg = <0x00 0x9e780000 0x00 0x80000>; no-map; From 115290c112952db27009668aa7ae2f29920704f0 Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Thu, 30 Jan 2025 11:55:47 +0530 Subject: [PATCH 14/32] arm64: dts: ti: k3-am62p5-sk: Support SoC wakeup using USB1 wakeup After the SoC has entered the Deep Sleep mode, USB1 can be used to wakeup the SoC based on USB events triggered by USB devices. This requires that the pin corresponding to the Type-A connector remains pulled up even after the SoC has entered the Deep Sleep mode. Hence, enable Deep Sleep pullup / pulldown selection for the USB1_DRVBUS pin and set its Deep Sleep state to PULL_UP. Signed-off-by: Siddharth Vadapalli Link: https://lore.kernel.org/r/20250130062550.1554651-1-s-vadapalli@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts index 20ceb1c11d8e..b62460fe5c24 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -310,7 +310,7 @@ main_usb1_pins_default: main-usb1-default-pins { pinctrl-single,pins = < - AM62PX_IOPAD(0x0258, PIN_INPUT, 0) /* (G21) USB1_DRVVBUS */ + AM62PX_IOPAD(0x0258, PIN_INPUT | PIN_DS_PULLUD_ENABLE | PIN_DS_PULL_UP, 0) /* (G21) USB1_DRVVBUS */ >; }; From 3e7f622685e8c3ae3adb5d905f56008c4371c660 Mon Sep 17 00:00:00 2001 From: Markus Schneider-Pargmann Date: Mon, 3 Feb 2025 10:34:10 +0100 Subject: [PATCH 15/32] arm64: dts: ti: k3-am62x-sk-common: Add serial aliases Add aliases for mcu_uart0 and wkup_uart0. Signed-off-by: Markus Schneider-Pargmann Link: https://lore.kernel.org/r/20250203-topic-am62-serial-aliases-v6-14-v1-1-f26d4124a9f1@baylibre.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi index 2f129e8cd5b9..d52cb2a5a589 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -12,6 +12,8 @@ / { aliases { + serial0 = &wkup_uart0; + serial1 = &mcu_uart0; serial2 = &main_uart0; mmc0 = &sdhci0; mmc1 = &sdhci1; From 5a74aef8821885e3d567f4a67bc20ecd723731e7 Mon Sep 17 00:00:00 2001 From: Markus Schneider-Pargmann Date: Mon, 3 Feb 2025 10:34:11 +0100 Subject: [PATCH 16/32] arm64: dts: ti: k3-am62a7-sk: Add serial alias Add alias for mcu_uart0. Signed-off-by: Markus Schneider-Pargmann Link: https://lore.kernel.org/r/20250203-topic-am62-serial-aliases-v6-14-v1-2-f26d4124a9f1@baylibre.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts index c5b199bb3f8e..1c9d95696c83 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -18,6 +18,7 @@ aliases { serial0 = &wkup_uart0; + serial1 = &mcu_uart0; serial2 = &main_uart0; serial3 = &main_uart1; mmc0 = &sdhci0; From 8b0f601f9869b01e2dc35c5860eb0f8ce0650be5 Mon Sep 17 00:00:00 2001 From: Vibhore Vardhan Date: Mon, 3 Feb 2025 10:34:12 +0100 Subject: [PATCH 17/32] arm64: dts: ti: k3-am62p5-sk: Add serial alias Add alias for mcu_uart0. Signed-off-by: Vibhore Vardhan Signed-off-by: Markus Schneider-Pargmann Link: https://lore.kernel.org/r/20250203-topic-am62-serial-aliases-v6-14-v1-3-f26d4124a9f1@baylibre.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts index b62460fe5c24..d29f524600af 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -19,6 +19,7 @@ aliases { serial0 = &wkup_uart0; + serial1 = &mcu_uart0; serial2 = &main_uart0; serial3 = &main_uart1; mmc0 = &sdhci0; From eeab4a777eb490b9eca670379720b938226b1c79 Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Fri, 31 Jan 2025 10:35:30 +0100 Subject: [PATCH 18/32] arm64: dts: ti: k3-am64-phycore-som: Reserve RTOS IPC memory Reserve a portion of memory for inter-processor communication between all remote processors running RTOS or baremetal firmware. Signed-off-by: Wadim Egorov Link: https://lore.kernel.org/r/20250131093531.1054924-1-w.egorov@phytec.de Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi index 99a6fdfaa7fb..e8d1b88651e7 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi @@ -99,6 +99,12 @@ reg = <0x00 0xa4100000 0x00 0xf00000>; no-map; }; + + rtos_ipc_memory_region: ipc-memories@a5000000 { + reg = <0x00 0xa5000000 0x00 0x00800000>; + alignment = <0x1000>; + no-map; + }; }; leds { From 4ad59ca98c2764ee2a58e48c96338b6fb88ce85a Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Fri, 31 Jan 2025 10:35:31 +0100 Subject: [PATCH 19/32] arm64: dts: ti: k3-am62-phycore-som: Reserve RTOS IPC memory Reserve a portion of memory for inter-processor communication between all remote processors running RTOS or baremetal firmware. Move ramoops to lower region so the IPC fits to the correct address. Signed-off-by: Wadim Egorov Link: https://lore.kernel.org/r/20250131093531.1054924-2-w.egorov@phytec.de Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi index 2ef4cbaec789..4bffa8ce0410 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi @@ -36,15 +36,21 @@ #size-cells = <2>; ranges; - ramoops@9ca00000 { + ramoops@9c700000 { compatible = "ramoops"; - reg = <0x00 0x9ca00000 0x00 0x00100000>; + reg = <0x00 0x9c700000 0x00 0x00100000>; record-size = <0x8000>; console-size = <0x8000>; ftrace-size = <0x00>; pmsg-size = <0x8000>; }; + rtos_ipc_memory_region: ipc-memories@9c800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9c800000 0x00 0x00300000>; + no-map; + }; + mcu_m4fss_dma_memory_region: m4f-dma-memory@9cb00000 { compatible = "shared-dma-pool"; reg = <0x00 0x9cb00000 0x00 0x100000>; From 6a02c9aa222ce0fff47f526686690f84b7a97f4e Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Thu, 6 Feb 2025 16:39:11 +0100 Subject: [PATCH 20/32] arm64: dts: ti: k3-am62p: Enable AUDIO_REFCLKx On AM62P-based SoCs the AUDIO_REFCLKx clocks can be used as an input to external peripherals when configured through CTRL_MMR, so add the clock nodes. Link: http://downloads.ti.com/tisci/esd/latest/5_soc_doc/am62px/clocks.html Signed-off-by: Francesco Dolcini Link: https://lore.kernel.org/r/20250206153911.414702-1-francesco@dolcini.it Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62p-main.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi index 420c77c8e9e5..4b47b0774330 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi @@ -42,6 +42,26 @@ ti,interrupt-ranges = <5 69 35>; }; +&main_conf { + audio_refclk0: clock-controller@82e0 { + compatible = "ti,am62-audio-refclk"; + reg = <0x82e0 0x4>; + clocks = <&k3_clks 157 0>; + assigned-clocks = <&k3_clks 157 0>; + assigned-clock-parents = <&k3_clks 157 16>; + #clock-cells = <0>; + }; + + audio_refclk1: clock-controller@82e4 { + compatible = "ti,am62-audio-refclk"; + reg = <0x82e4 0x4>; + clocks = <&k3_clks 157 18>; + assigned-clocks = <&k3_clks 157 18>; + assigned-clock-parents = <&k3_clks 157 34>; + #clock-cells = <0>; + }; +}; + &main_pmx0 { pinctrl-single,gpio-range = <&main_pmx0_range 0 32 PIN_GPIO_RANGE_IOPAD>, From 38e7f9092efbbf2a4a67e4410b55b797f8d1e184 Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Fri, 28 Feb 2025 11:08:50 +0530 Subject: [PATCH 21/32] arm64: dts: ti: k3-j784s4-j742s2-main-common: Fix serdes_ln_ctrl reg-masks Commit under Fixes added the 'idle-states' property for SERDES4 lane muxes without defining the corresponding register offsets and masks for it in the 'mux-reg-masks' property within the 'serdes_ln_ctrl' node. Fix this. Fixes: 7287d423f138 ("arm64: dts: ti: k3-j784s4-main: Add system controller and SERDES lane mux") Cc: stable@vger.kernel.org Signed-off-by: Siddharth Vadapalli Link: https://lore.kernel.org/r/20250228053850.506028-1-s-vadapalli@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi index 3b72fca158ad..1944616ab357 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi @@ -84,7 +84,9 @@ <0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */ <0x18 0x3>, <0x1c 0x3>, /* SERDES1 lane2/3 select */ <0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */ - <0x28 0x3>, <0x2c 0x3>; /* SERDES2 lane2/3 select */ + <0x28 0x3>, <0x2c 0x3>, /* SERDES2 lane2/3 select */ + <0x40 0x3>, <0x44 0x3>, /* SERDES4 lane0/1 select */ + <0x48 0x3>, <0x4c 0x3>; /* SERDES4 lane2/3 select */ idle-states = , , , From 638ab30ce4c63edae4934dcaa7a61f37b96efe6c Mon Sep 17 00:00:00 2001 From: Daniel Schultz Date: Tue, 28 Jan 2025 02:03:56 -0800 Subject: [PATCH 22/32] arm64: dts: ti: am64-phyboard-electra: Add DT overlay for X27 connector Add a device tree overlay for SPI1 , UART3 and GPIO1 on X27 connector. By default, not all interfaces on the X27 connector are accessible due to being disabled or set to alternative pin mux configurations. This overlay activates and configures these interfaces to support connections with external devices. Signed-off-by: Wadim Egorov Signed-off-by: Daniel Schultz Link: https://lore.kernel.org/r/20250128100356.462934-1-d.schultz@phytec.de Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 3 + ...phyboard-electra-x27-gpio1-spi1-uart3.dtso | 63 +++++++++++++++++++ 2 files changed, 66 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 8a4bdf87e2d4..03d4cecfc001 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -54,6 +54,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am642-evm-nand.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-rdk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-gpio-fan.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-pcie-usb2.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am642-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl.dtb dtb-$(CONFIG_ARCH_K3) += k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo @@ -185,6 +186,8 @@ k3-am642-phyboard-electra-gpio-fan-dtbs := \ k3-am642-phyboard-electra-rdk.dtb k3-am642-phyboard-electra-gpio-fan.dtbo k3-am642-phyboard-electra-pcie-usb2-dtbs := \ k3-am642-phyboard-electra-rdk.dtb k3-am642-phyboard-electra-pcie-usb2.dtbo +k3-am642-phyboard-electra-x27-gpio1-spi1-uart3-dtbs := \ + k3-am642-phyboard-electra-rdk.dtb k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtbo k3-am642-tqma64xxl-mbax4xxl-sdcard-dtbs := \ k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo k3-am642-tqma64xxl-mbax4xxl-wlan-dtbs := \ diff --git a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtso b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtso new file mode 100644 index 000000000000..996c42ec4253 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtso @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + * Authors: + * Wadim Egorov + * Daniel Schultz + * + * GPIO, SPI and UART examples for the X27 expansion connector. + */ + +/dts-v1/; +/plugin/; + +#include "k3-pinctrl.h" + +&{/} { + aliases { + serial5 = "/bus@f4000/serial@2830000"; + }; +}; + +&main_pmx0 { + main_gpio1_exp_header_gpio_pins_default: main-gpio1-exp-header-gpio-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0220, PIN_INPUT, 7) /* (D14) SPI1_CS1.GPIO1_48 */ + >; + }; + + main_spi1_pins_default: main-spi1-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0224, PIN_INPUT, 0) /* (C14) SPI1_CLK */ + AM64X_IOPAD(0x021C, PIN_OUTPUT, 0) /* (B14) SPI1_CS0 */ + AM64X_IOPAD(0x0228, PIN_OUTPUT, 0) /* (B15) SPI1_D0 */ + AM64X_IOPAD(0x022C, PIN_INPUT, 0) /* (A15) SPI1_D1 */ + >; + }; + + main_uart3_pins_default: main-uart3-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0048, PIN_INPUT, 2) /* (U20) GPMC0_AD3.UART3_RXD */ + AM64X_IOPAD(0x004c, PIN_OUTPUT, 2) /* (U18) GPMC0_AD4.UART3_TXD */ + >; + }; +}; + +&main_gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_gpio1_exp_header_gpio_pins_default>; + status = "okay"; +}; + +&main_spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_spi1_pins_default>; + ti,pindir-d0-out-d1-in = <1>; + status = "okay"; +}; + +&main_uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart3_pins_default>; + status = "okay"; +}; From 33bab9d84e52188cf73c3573fd7cf3ec0e01d007 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Fri, 21 Feb 2025 10:14:46 +0100 Subject: [PATCH 23/32] arm64: dts: ti: k3-am62p: fix pinctrl settings It appears that pinctrl-single is misused on this SoC to control both the mux and the input and output and bias settings. This results in non-working pinctrl configurations for GPIOs within the device tree. This is what happens: (1) During startup the pinctrl settings are applied according to the device tree. I.e. the pin is configured as output and with pull-ups enabled. (2) During startup a device driver requests a GPIO. (3) pinctrl-single is applying the default GPIO setting according to the pinctrl-single,gpio-range property. This would work as expected if the pinctrl-single is only controlling the function mux, but it also controls the input/output buffer enable, the pull-up and pull-down settings etc (pinctrl-single,function-mask covers the entire pad setting instead of just the mux field). Remove the pinctrl-single,gpio-range property, so that no settings are applied during a gpio_request() call. Fixes: d72d73a44c3c ("arm64: dts: ti: k3-am62p: Add gpio-ranges properties") Signed-off-by: Michael Walle Link: https://lore.kernel.org/r/20250221091447.595199-1-mwalle@kernel.org Signed-off-by: Vignesh Raghavendra --- .../boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi | 8 -------- arch/arm64/boot/dts/ti/k3-am62p-main.dtsi | 14 -------------- 2 files changed, 22 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi index b33aff0d65c9..bd6a00d13aea 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi @@ -12,15 +12,7 @@ #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; - pinctrl-single,gpio-range = - <&mcu_pmx_range 0 21 PIN_GPIO_RANGE_IOPAD>, - <&mcu_pmx_range 23 1 PIN_GPIO_RANGE_IOPAD>, - <&mcu_pmx_range 32 2 PIN_GPIO_RANGE_IOPAD>; bootph-all; - - mcu_pmx_range: gpio-range { - #pinctrl-single,gpio-range-cells = <3>; - }; }; mcu_esm: esm@4100000 { diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi index 4b47b0774330..6aea9d3f134e 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi @@ -62,20 +62,6 @@ }; }; -&main_pmx0 { - pinctrl-single,gpio-range = - <&main_pmx0_range 0 32 PIN_GPIO_RANGE_IOPAD>, - <&main_pmx0_range 33 38 PIN_GPIO_RANGE_IOPAD>, - <&main_pmx0_range 72 22 PIN_GPIO_RANGE_IOPAD>, - <&main_pmx0_range 137 5 PIN_GPIO_RANGE_IOPAD>, - <&main_pmx0_range 143 3 PIN_GPIO_RANGE_IOPAD>, - <&main_pmx0_range 149 2 PIN_GPIO_RANGE_IOPAD>; - - main_pmx0_range: gpio-range { - #pinctrl-single,gpio-range-cells = <3>; - }; -}; - &main_gpio0 { gpio-ranges = <&main_pmx0 0 0 32>, <&main_pmx0 32 33 38>, <&main_pmx0 70 72 22>; From 06daad327d043c23bc1ab4cdb519f589094b9e98 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Fri, 21 Feb 2025 10:14:47 +0100 Subject: [PATCH 24/32] arm64: dts: ti: k3-j722s: fix pinctrl settings It appears that pinctrl-single is misused on this SoC to control both the mux and the input and output and bias settings. This results in non-working pinctrl configurations for GPIOs within the device tree. This is what happens: (1) During startup the pinctrl settings are applied according to the device tree. I.e. the pin is configured as output and with pull-ups enabled. (2) During startup a device driver requests a GPIO. (3) pinctrl-single is applying the default GPIO setting according to the pinctrl-single,gpio-range property. This would work as expected if the pinctrl-single is only controlling the function mux, but it also controls the input/output buffer enable, the pull-up and pull-down settings etc (pinctrl-single,function-mask covers the entire pad setting instead of just the mux field). Remove the pinctrl-single,gpio-range property, so that no settings are applied during a gpio_request() call. Fixes: 5e5c50964e2e ("arm64: dts: ti: k3-j722s: Add gpio-ranges properties") Signed-off-by: Michael Walle Link: https://lore.kernel.org/r/20250221091447.595199-2-mwalle@kernel.org Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi index 3ac2d45a0558..6da7b3a2943c 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi @@ -251,21 +251,6 @@ ti,interrupt-ranges = <7 71 21>; }; -&main_pmx0 { - pinctrl-single,gpio-range = - <&main_pmx0_range 0 32 PIN_GPIO_RANGE_IOPAD>, - <&main_pmx0_range 33 38 PIN_GPIO_RANGE_IOPAD>, - <&main_pmx0_range 72 17 PIN_GPIO_RANGE_IOPAD>, - <&main_pmx0_range 101 25 PIN_GPIO_RANGE_IOPAD>, - <&main_pmx0_range 137 5 PIN_GPIO_RANGE_IOPAD>, - <&main_pmx0_range 143 3 PIN_GPIO_RANGE_IOPAD>, - <&main_pmx0_range 149 2 PIN_GPIO_RANGE_IOPAD>; - - main_pmx0_range: gpio-range { - #pinctrl-single,gpio-range-cells = <3>; - }; -}; - &main_gpio0 { gpio-ranges = <&main_pmx0 0 0 32>, <&main_pmx0 32 33 38>, <&main_pmx0 70 72 17>; From fb1b230bf9c45f5d6579dc329c2aafcd1263b70a Mon Sep 17 00:00:00 2001 From: Vaishnav Achath Date: Wed, 19 Feb 2025 00:24:48 +0530 Subject: [PATCH 25/32] arm64: dts: ti: k3-j722s-main: Add BCDMA CSI overrides J722S has a dedicated CSI BCDMA instance which is slightly different from AM62P in TX channel support, add the overrides and additional properties to support CSI BCDMA on J722S. Signed-off-by: Vaishnav Achath Reviewed-by: Yemike Abhilash Chandra Link: https://lore.kernel.org/r/20250218185452.600797-2-vaishnav.a@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi index 6da7b3a2943c..9bb2782de2b8 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi @@ -204,6 +204,16 @@ }; }; +&main_bcdma_csi { + compatible = "ti,j722s-dmss-bcdma-csi"; + reg = <0x00 0x4e230000 0x00 0x100>, + <0x00 0x4e180000 0x00 0x20000>, + <0x00 0x4e300000 0x00 0x10000>, + <0x00 0x4e100000 0x00 0x80000>; + reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; + ti,sci-rm-range-tchan = <0x22>; +}; + /* MCU domain overrides */ &mcu_r5fss0_core0 { From 8fea4519f625e6c1b05078f2ecea252b7b28b06e Mon Sep 17 00:00:00 2001 From: Vaishnav Achath Date: Wed, 19 Feb 2025 00:24:49 +0530 Subject: [PATCH 26/32] arm64: dts: ti: k3-j722s-main: Add CSI2RX nodes J722S has 4 CSI2RX receiver instances with external DPHY. The first CSI2RX instance node is derived from the AM62P common dtsi, Add the nodes for the subsequent three instances and keep them disabled. TRM (12.6 Camera Peripherals): https://www.ti.com/lit/zip/sprujb3 Signed-off-by: Vaishnav Achath Reviewed-by: Yemike Abhilash Chandra Link: https://lore.kernel.org/r/20250218185452.600797-3-vaishnav.a@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 183 ++++++++++++++++++++++ 1 file changed, 183 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi index 9bb2782de2b8..6850f50530f1 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi @@ -154,6 +154,189 @@ }; }; + ti_csi2rx1: ticsi2rx@30122000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x00 0x30122000 0x00 0x1000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dmas = <&main_bcdma_csi 0 0x5100 0>; + dma-names = "rx0"; + power-domains = <&k3_pds 247 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + cdns_csi2rx1: csi-bridge@30121000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x30121000 0x00 0x1000>; + clocks = <&k3_clks 247 0>, <&k3_clks 247 3>, <&k3_clks 247 0>, + <&k3_clks 247 0>, <&k3_clks 247 4>, <&k3_clks 247 4>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy1>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi1_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi1_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi1_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi1_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + ti_csi2rx2: ticsi2rx@30142000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x00 0x30142000 0x00 0x1000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>; + dmas = <&main_bcdma_csi 0 0x5200 0>; + dma-names = "rx0"; + status = "disabled"; + + cdns_csi2rx2: csi-bridge@30141000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x30141000 0x00 0x1000>; + clocks = <&k3_clks 248 0>, <&k3_clks 248 3>, <&k3_clks 248 0>, + <&k3_clks 248 0>, <&k3_clks 248 4>, <&k3_clks 248 4>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy2>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi2_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi2_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi2_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi2_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi2_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + ti_csi2rx3: ticsi2rx@30162000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x00 0x30162000 0x00 0x1000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dmas = <&main_bcdma_csi 0 0x5300 0>; + dma-names = "rx0"; + power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + cdns_csi2rx3: csi-bridge@30161000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x30161000 0x00 0x1000>; + clocks = <&k3_clks 249 0>, <&k3_clks 249 3>, <&k3_clks 249 0>, + <&k3_clks 249 0>, <&k3_clks 249 4>, <&k3_clks 249 4>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy3>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi3_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi3_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi3_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi3_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi3_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + dphy1: phy@30130000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x30130000 0x00 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 251 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + dphy2: phy@30150000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x30150000 0x00 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + dphy3: phy@30170000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x30170000 0x00 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + main_r5fss0: r5fss@78400000 { compatible = "ti,am62-r5fss"; #address-cells = <1>; From ce553288ad2368f0d27e47b39a23121a825a2b33 Mon Sep 17 00:00:00 2001 From: Vaishnav Achath Date: Wed, 19 Feb 2025 00:24:50 +0530 Subject: [PATCH 27/32] arm64: dts: ti: k3-j722s-evm: Add camera peripherals J722S EVM has four RPi camera connectors and dual MIPI Samtec CSI connectors which bring out the 4 x CSI2RX instances and the I2C camera control interfaces. Add the nodes for PCA9543 I2C switch and enable them. J722S EVM schematics: https://www.ti.com/lit/pdf/sprujb5 Signed-off-by: Vaishnav Achath Reviewed-by: Yemike Abhilash Chandra Link: https://lore.kernel.org/r/20250218185452.600797-4-vaishnav.a@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 28 +++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts index adee69607fdb..2127316f36a3 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -263,6 +263,13 @@ bootph-all; }; + main_i2c2_pins_default: main-i2c2-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (P22) GPMC0_CSn2.I2C2_SCL */ + J722S_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (P23) GPMC0_CSn3.I2C2_SDA */ + >; + }; + main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < J722S_IOPAD(0x01c8, PIN_INPUT, 0) /* (A22) UART0_RXD */ @@ -631,6 +638,27 @@ }; }; +&main_i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c2_pins_default>; + clock-frequency = <400000>; + + pca9543_0: i2c-mux@70 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + }; + + pca9543_1: i2c-mux@71 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + }; +}; + &ospi0 { pinctrl-names = "default"; pinctrl-0 = <&ospi0_pins_default>; From 63426153ef11cd29490c0ab916c76e0d635b8136 Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Wed, 5 Mar 2025 09:55:33 +0100 Subject: [PATCH 28/32] arm64: dts: ti: k3-am62x-phyboard-lyra: Add boot phase tags The bootph-all and bootph-pre-ram tags were introduced in dt-schema (dtschema/schemas/bootph.yaml) to define node usage across different boot phases. Add boot phase tags to all required nodes to ensure boot support from all sources, including UART, USB (DFU), Ethernet, uSD card, eMMC, and OSPI NOR Flash. Signed-off-by: Wadim Egorov Link: https://lore.kernel.org/r/20250305085537.3976579-1-w.egorov@phytec.de Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi | 15 +++++++++++++++ .../arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi | 9 +++++++++ 2 files changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi index 4bffa8ce0410..55ed418c023b 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi @@ -29,6 +29,7 @@ memory@80000000 { device_type = "memory"; reg = <0x00000000 0x80000000 0x00000000 0x80000000>; + bootph-all; }; reserved_memory: reserved-memory { @@ -137,6 +138,7 @@ AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */ AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */ >; + bootph-all; }; main_mdio1_pins_default: main-mdio1-default-pins { @@ -144,6 +146,7 @@ AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */ AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */ >; + bootph-all; }; main_mmc0_pins_default: main-mmc0-default-pins { @@ -159,6 +162,7 @@ AM62X_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */ AM62X_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */ >; + bootph-all; }; main_rgmii1_pins_default: main-rgmii1-default-pins { @@ -176,6 +180,7 @@ AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */ AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */ >; + bootph-all; }; ospi0_pins_default: ospi0-default-pins { @@ -192,6 +197,7 @@ AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */ AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */ >; + bootph-all; }; pmic_irq_pins_default: pmic-irq-default-pins { @@ -216,6 +222,7 @@ &cpsw_port1 { phy-mode = "rgmii-rxid"; phy-handle = <&cpsw3g_phy1>; + bootph-all; }; &cpsw3g_mdio { @@ -226,6 +233,7 @@ cpsw3g_phy1: ethernet-phy@1 { compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22"; reg = <1>; + bootph-all; ti,rx-internal-delay = ; ti,fifo-depth = ; }; @@ -238,10 +246,15 @@ }; }; +&main_pktdma { + bootph-all; +}; + &main_i2c0 { pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; clock-frequency = <400000>; + bootph-all; status = "okay"; pmic@30 { @@ -361,6 +374,7 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <0>; + bootph-all; }; }; @@ -369,5 +383,6 @@ pinctrl-0 = <&main_mmc0_pins_default>; disable-wp; non-removable; + bootph-all; status = "okay"; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi index 922cad14c9f8..aab74d6019b0 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi @@ -138,6 +138,7 @@ regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; + bootph-all; }; vcc_3v3_sw: regulator-vcc-3v3-sw { @@ -233,6 +234,7 @@ AM62X_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (D22) MMC1_DAT3 */ AM62X_IOPAD(0x240, PIN_INPUT_PULLUP, 0) /* (D17) MMC1_SDCD */ >; + bootph-all; }; main_rgmii2_pins_default: main-rgmii2-default-pins { @@ -257,6 +259,7 @@ AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */ AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ >; + bootph-all; }; main_uart1_pins_default: main-uart1-default-pins { @@ -266,6 +269,7 @@ AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19) MCASP0_AFSR.UART1_RXD */ AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */ >; + bootph-pre-ram; }; main_usb1_pins_default: main-usb1-default-pins { @@ -430,12 +434,14 @@ &main_uart0 { pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; + bootph-all; status = "okay"; }; &main_uart1 { pinctrl-names = "default"; pinctrl-0 = <&main_uart1_pins_default>; + bootph-pre-ram; /* Main UART1 may be used by TIFS firmware */ status = "okay"; }; @@ -467,11 +473,13 @@ pinctrl-0 = <&main_mmc1_pins_default>; disable-wp; no-1-8-v; + bootph-all; status = "okay"; }; &usbss0 { ti,vbus-divider; + bootph-all; status = "okay"; }; @@ -482,6 +490,7 @@ &usb0 { usb-role-switch; + bootph-all; port { typec_hs: endpoint { From 2285ea3f8065f47a6a1b62e6fcfa85105c8c261b Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Wed, 5 Mar 2025 09:55:34 +0100 Subject: [PATCH 29/32] arm64: dts: ti: k3-am62a-phycore-som: Add boot phase tags The bootph-all and bootph-pre-ram tags were introduced in dt-schema (dtschema/schemas/bootph.yaml) to define node usage across different boot phases. Add boot phase tags to all required nodes to ensure boot support from all sources, including UART, USB (DFU), Ethernet, uSD card, eMMC, and OSPI NOR Flash. Signed-off-by: Wadim Egorov Link: https://lore.kernel.org/r/20250305085537.3976579-2-w.egorov@phytec.de Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi index a5aceaa39670..7920559e84a3 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi @@ -42,6 +42,7 @@ device_type = "memory"; /* 2G RAM */ reg = <0x00000000 0x80000000 0x00000000 0x80000000>; + bootph-all; }; reserved-memory { @@ -99,6 +100,7 @@ AM62AX_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (D17) I2C0_SCL */ AM62AX_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (E16) I2C0_SDA */ >; + bootph-all; }; main_mdio1_pins_default: main-mdio1-default-pins { @@ -106,6 +108,7 @@ AM62AX_IOPAD(0x160, PIN_OUTPUT, 0) /* (V12) MDIO0_MDC */ AM62AX_IOPAD(0x15c, PIN_INPUT, 0) /* (V13) MDIO0_MDIO */ >; + bootph-all; }; main_mmc0_pins_default: main-mmc0-default-pins { @@ -121,6 +124,7 @@ AM62AX_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (W9) MMC0_DAT6 */ AM62AX_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AB8) MMC0_DAT7 */ >; + bootph-all; }; main_rgmii1_pins_default: main-rgmii1-default-pins { @@ -138,6 +142,7 @@ AM62AX_IOPAD(0x130, PIN_OUTPUT, 0) /* (AB17) RGMII1_TXC */ AM62AX_IOPAD(0x12c, PIN_OUTPUT, 0) /* (W16) RGMII1_TX_CTL */ >; + bootph-all; }; ospi0_pins_default: ospi0-default-pins { @@ -155,6 +160,7 @@ AM62AX_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */ AM62AX_IOPAD(0x008, PIN_INPUT, 0) /* (L21) OSPI0_DQS */ >; + bootph-all; }; pmic_irq_pins_default: pmic-irq-default-pins { @@ -168,11 +174,13 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_rgmii1_pins_default>; + status = "okay"; }; &cpsw_port1 { phy-mode = "rgmii-rxid"; phy-handle = <&cpsw3g_phy1>; + bootph-all; }; &cpsw3g_mdio { @@ -182,6 +190,7 @@ cpsw3g_phy1: ethernet-phy@1 { compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22"; reg = <1>; + bootph-all; ti,clk-output-sel = ; ti,rx-internal-delay = ; ti,fifo-depth = ; @@ -196,6 +205,7 @@ pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; clock-frequency = <400000>; + bootph-all; status = "okay"; pmic@30 { @@ -302,6 +312,10 @@ status = "okay"; }; +&main_pktdma { + bootph-all; +}; + &ospi0 { pinctrl-names = "default"; pinctrl-0 = <&ospi0_pins_default>; @@ -318,6 +332,7 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <0>; + bootph-all; }; }; @@ -326,5 +341,6 @@ pinctrl-0 = <&main_mmc0_pins_default>; disable-wp; non-removable; + bootph-all; status = "okay"; }; From 17141e9cabed0cf3236575842f91f6239993bf4d Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Wed, 5 Mar 2025 09:55:35 +0100 Subject: [PATCH 30/32] arm64: dts: ti: k3-am642-phyboard-electra: Add boot phase tags The bootph-all and bootph-pre-ram tags were introduced in dt-schema (dtschema/schemas/bootph.yaml) to define node usage across different boot phases. Add boot phase tags to all required nodes to ensure boot support from all sources, including UART, Ethernet, uSD card, eMMC, and OSPI NOR Flash. Signed-off-by: Wadim Egorov Link: https://lore.kernel.org/r/20250305085537.3976579-3-w.egorov@phytec.de Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi | 15 +++++++++++++++ .../boot/dts/ti/k3-am642-phyboard-electra-rdk.dts | 5 +++++ 2 files changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi index e8d1b88651e7..c95f9d642f0d 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi @@ -27,6 +27,7 @@ memory@80000000 { device_type = "memory"; reg = <0x00000000 0x80000000 0x00000000 0x80000000>; + bootph-all; }; reserved_memory: reserved-memory { @@ -138,6 +139,7 @@ AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */ AM64X_IOPAD(0x0100, PIN_OUTPUT, 7) /* (V7) PRG1_PRU0_GPO18.GPIO0_63 */ >; + bootph-all; }; cpsw_rgmii1_pins_default: cpsw-rgmii1-default-pins { @@ -156,6 +158,7 @@ AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */ AM64X_IOPAD(0x0154, PIN_INPUT, 7) /* (V12) PRG1_PRU1_GPO19.GPIO0_84 */ >; + bootph-all; }; eeprom_wp_pins_default: eeprom-wp-default-pins { @@ -175,6 +178,7 @@ AM64X_IOPAD(0x0260, PIN_INPUT, 0) /* (A18) I2C0_SCL */ AM64X_IOPAD(0x0264, PIN_INPUT, 0) /* (B18) I2C0_SDA */ >; + bootph-all; }; ospi0_pins_default: ospi0-default-pins { @@ -191,6 +195,7 @@ AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */ AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */ >; + bootph-all; }; rtc_pins_default: rtc-defaults-pins { @@ -210,6 +215,7 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&cpsw_mdio_pins_default>; + bootph-all; cpsw3g_phy1: ethernet-phy@1 { compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22"; @@ -221,12 +227,14 @@ reset-gpios = <&main_gpio0 63 GPIO_ACTIVE_LOW>; reset-assert-us = <1000>; reset-deassert-us = <1000>; + bootph-all; }; }; &cpsw_port1 { phy-mode = "rgmii-rxid"; phy-handle = <&cpsw3g_phy1>; + bootph-all; status = "okay"; }; @@ -272,6 +280,7 @@ pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; clock-frequency = <400000>; + bootph-all; eeprom@50 { compatible = "atmel,24c32"; @@ -336,6 +345,10 @@ }; }; +&main_pktdma { + bootph-all; +}; + &main_r5fss0_core0 { mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, @@ -383,6 +396,7 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <0>; + bootph-all; }; }; @@ -392,6 +406,7 @@ ti,driver-strength-ohm = <50>; disable-wp; keep-power-in-suspend; + bootph-all; }; &tscadc0 { diff --git a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts index bc8e1ce11047..6fbd8d932396 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts @@ -171,6 +171,7 @@ regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; + bootph-all; }; }; @@ -275,6 +276,7 @@ AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */ AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */ >; + bootph-all; }; main_spi0_pins_default: main-spi0-default-pins { @@ -291,6 +293,7 @@ AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */ AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */ >; + bootph-all; }; main_uart1_pins_default: main-uart1-default-pins { @@ -413,6 +416,7 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; + bootph-all; }; &main_uart1 { @@ -429,6 +433,7 @@ pinctrl-0 = <&main_mmc1_pins_default>; disable-wp; no-1-8-v; + bootph-all; }; &serdes0 { From 0100a04a55685b6bfb2ea40e9d6882cc35e2e433 Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Wed, 5 Mar 2025 09:55:36 +0100 Subject: [PATCH 31/32] arm64: dts: ti: k3-am642-phyboard-electra: Reorder properties per DTS coding style Reorder properties to comply with the DeviceTree coding style guidelines: https://docs.kernel.org/devicetree/bindings/dts-coding-style.html Signed-off-by: Wadim Egorov Link: https://lore.kernel.org/r/20250305085537.3976579-4-w.egorov@phytec.de Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi | 12 ++++++------ .../boot/dts/ti/k3-am642-phyboard-electra-rdk.dts | 14 +++++++------- 2 files changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi index c95f9d642f0d..d9d491b12c33 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi @@ -212,22 +212,22 @@ }; &cpsw3g_mdio { - status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&cpsw_mdio_pins_default>; bootph-all; + status = "okay"; cpsw3g_phy1: ethernet-phy@1 { compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22"; reg = <1>; interrupt-parent = <&main_gpio0>; interrupts = <84 IRQ_TYPE_EDGE_FALLING>; - ti,rx-internal-delay = ; - ti,fifo-depth = ; reset-gpios = <&main_gpio0 63 GPIO_ACTIVE_LOW>; reset-assert-us = <1000>; reset-deassert-us = <1000>; bootph-all; + ti,rx-internal-delay = ; + ti,fifo-depth = ; }; }; @@ -276,11 +276,11 @@ }; &main_i2c0 { - status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; clock-frequency = <400000>; bootph-all; + status = "okay"; eeprom@50 { compatible = "atmel,24c32"; @@ -381,9 +381,9 @@ }; &ospi0 { - status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ospi0_pins_default>; + status = "okay"; serial_flash: flash@0 { compatible = "jedec,spi-nor"; @@ -401,12 +401,12 @@ }; &sdhci0 { - status = "okay"; non-removable; ti,driver-strength-ohm = <50>; disable-wp; keep-power-in-suspend; bootph-all; + status = "okay"; }; &tscadc0 { diff --git a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts index 6fbd8d932396..f63c101b7d61 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts @@ -352,10 +352,10 @@ }; &main_i2c1 { - status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c1_pins_default>; clock-frequency = <400000>; + status = "okay"; eeprom@51 { compatible = "atmel,24c02"; @@ -385,25 +385,25 @@ }; &main_mcan0 { - status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_mcan0_pins_default>; phys = <&can_tc1>; + status = "okay"; }; &main_mcan1 { - status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_mcan1_pins_default>; phys = <&can_tc2>; + status = "okay"; }; &main_spi0 { - status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_spi0_pins_default>; cs-gpios = <0>, <&main_gpio1 43 GPIO_ACTIVE_LOW>; ti,pindir-d0-out-d1-in; + status = "okay"; tpm@1 { compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; @@ -413,27 +413,27 @@ }; &main_uart0 { - status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; bootph-all; + status = "okay"; }; &main_uart1 { - status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart1_pins_default>; uart-has-rtscts; + status = "okay"; }; &sdhci1 { - status = "okay"; vmmc-supply = <&vcc_3v3_mmc>; pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; disable-wp; no-1-8-v; bootph-all; + status = "okay"; }; &serdes0 { From 377fde74eae4abcbcd5475676d58fb595a07ff85 Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Wed, 5 Mar 2025 09:55:37 +0100 Subject: [PATCH 32/32] arm64: dts: ti: k3-am62a-phycore-som: Reorder properties per DTS coding style Reorder properties to comply with the DeviceTree coding style guidelines: https://docs.kernel.org/devicetree/bindings/dts-coding-style.html Signed-off-by: Wadim Egorov Link: https://lore.kernel.org/r/20250305085537.3976579-5-w.egorov@phytec.de Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi index 7920559e84a3..147d56b87984 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi @@ -171,7 +171,6 @@ }; &cpsw3g { - status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_rgmii1_pins_default>; status = "okay"; @@ -225,8 +224,8 @@ interrupts = ; interrupt-controller; #interrupt-cells = <1>; - ti,power-button; system-power-controller; + ti,power-button; regulators { vdd_3v3: buck1 {