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drm/rockchip: add dynamic debug for vop

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Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I50858d1c6d1e344ab2e7fbc85e5474a130f6fc6f
This commit is contained in:
Sandy Huang
2023-08-29 10:47:39 +08:00
committed by Tao Huang
parent adf004e7c8
commit 2e409456c1
1 changed files with 13 additions and 0 deletions
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drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+13
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@@ -1873,6 +1873,9 @@ static void vop_plane_atomic_disable(struct drm_plane *plane,
to_vop_plane_state(plane->state);
#endif
rockchip_drm_dbg(vop->dev, VOP_DEBUG_PLANE, "disable win%d-area%d by %s\n",
win->win_id, win->area_id, current->comm);
if (!old_state->crtc)
return;
@@ -1982,6 +1985,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
uint32_t val;
bool rb_swap, global_alpha_en;
int is_yuv = fb->format->is_yuv;
struct drm_format_name_buf format_name;
#if defined(CONFIG_ROCKCHIP_DRM_DEBUG)
bool AFBC_flag = false;
@@ -2146,6 +2150,13 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
VOP_WIN_SET(vop, win, enable, 1);
VOP_WIN_SET(vop, win, gate, 1);
spin_unlock(&vop->reg_lock);
drm_get_format_name(fb->format->format, &format_name);
rockchip_drm_dbg(vop->dev, VOP_DEBUG_PLANE,
"update win%d-area%d [%dx%d->%dx%d@(%d, %d)] zpos:%d fmt[%s%s] addr[%pad] by %s\n",
win->win_id, win->area_id, actual_w, actual_h,
dsp_w, dsp_h, dsp_stx, dsp_sty, vop_plane_state->zpos, format_name.str,
fb->modifier ? "[AFBC]" : "", &vop_plane_state->yrgb_mst, current->comm);
/*
* spi interface(vop_plane_state->yrgb_kvaddr, fb->pixel_format,
* actual_w, actual_h)
@@ -4031,6 +4042,7 @@ static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
spin_lock_irqsave(&vop->irq_lock, flags);
vop->pre_overlay = s->hdr.pre_overlay;
vop_cfg_done(vop);
rockchip_drm_dbg(vop->dev, VOP_DEBUG_CFG_DONE, "cfg_done\n\n");
/*
* rk322x and rk332x odd-even field will mistake when in interlace mode.
* we must switch to frame effect before switch screen and switch to
@@ -4396,6 +4408,7 @@ static irqreturn_t vop_isr(int irq, void *data)
* frame effective, but actually it's effective immediately, so
* we config this register at frame start.
*/
rockchip_drm_dbg(vop->dev, VOP_DEBUG_VSYNC, "vsync\n");
spin_lock_irqsave(&vop->irq_lock, flags);
VOP_CTRL_SET(vop, level2_overlay_en, vop->pre_overlay);
VOP_CTRL_SET(vop, alpha_hard_calc, vop->pre_overlay);