Merge branch 'common/serial-rework' into sh-latest
This commit is contained in:
Paul Mundt
@@ -974,7 +974,7 @@ config SERIAL_IP22_ZILOG_CONSOLE
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config SERIAL_SH_SCI
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tristate "SuperH SCI(F) serial port support"
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depends on HAVE_CLK && (SUPERH || H8300 || ARCH_SHMOBILE)
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depends on HAVE_CLK && (SUPERH || ARCH_SHMOBILE)
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select SERIAL_CORE
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config SERIAL_SH_SCI_NR_UARTS
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+352
-226
@@ -54,10 +54,6 @@
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#include <asm/sh_bios.h>
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#endif
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#ifdef CONFIG_H8300
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#include <asm/gpio.h>
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#endif
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#include "sh-sci.h"
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struct sci_port {
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@@ -121,6 +117,255 @@ to_sci_port(struct uart_port *uart)
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return container_of(uart, struct sci_port, port);
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}
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struct plat_sci_reg {
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u8 offset, size;
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};
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/* Helper for invalidating specific entries of an inherited map. */
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#define sci_reg_invalid { .offset = 0, .size = 0 }
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static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
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[SCIx_PROBE_REGTYPE] = {
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[0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
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},
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/*
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* Common SCI definitions, dependent on the port's regshift
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* value.
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*/
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[SCIx_SCI_REGTYPE] = {
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[SCSMR] = { 0x00, 8 },
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[SCBRR] = { 0x01, 8 },
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[SCSCR] = { 0x02, 8 },
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[SCxTDR] = { 0x03, 8 },
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[SCxSR] = { 0x04, 8 },
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[SCxRDR] = { 0x05, 8 },
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[SCFCR] = sci_reg_invalid,
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[SCFDR] = sci_reg_invalid,
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[SCTFDR] = sci_reg_invalid,
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[SCRFDR] = sci_reg_invalid,
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[SCSPTR] = sci_reg_invalid,
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[SCLSR] = sci_reg_invalid,
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},
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/*
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* Common definitions for legacy IrDA ports, dependent on
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* regshift value.
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*/
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[SCIx_IRDA_REGTYPE] = {
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[SCSMR] = { 0x00, 8 },
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[SCBRR] = { 0x01, 8 },
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[SCSCR] = { 0x02, 8 },
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[SCxTDR] = { 0x03, 8 },
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[SCxSR] = { 0x04, 8 },
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[SCxRDR] = { 0x05, 8 },
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[SCFCR] = { 0x06, 8 },
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[SCFDR] = { 0x07, 16 },
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[SCTFDR] = sci_reg_invalid,
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[SCRFDR] = sci_reg_invalid,
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[SCSPTR] = sci_reg_invalid,
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[SCLSR] = sci_reg_invalid,
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},
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/*
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* Common SCIFA definitions.
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*/
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[SCIx_SCIFA_REGTYPE] = {
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[SCSMR] = { 0x00, 16 },
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[SCBRR] = { 0x04, 8 },
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[SCSCR] = { 0x08, 16 },
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[SCxTDR] = { 0x20, 8 },
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[SCxSR] = { 0x14, 16 },
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[SCxRDR] = { 0x24, 8 },
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[SCFCR] = { 0x18, 16 },
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[SCFDR] = { 0x1c, 16 },
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[SCTFDR] = sci_reg_invalid,
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[SCRFDR] = sci_reg_invalid,
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[SCSPTR] = sci_reg_invalid,
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[SCLSR] = sci_reg_invalid,
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},
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/*
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* Common SCIFB definitions.
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*/
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[SCIx_SCIFB_REGTYPE] = {
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[SCSMR] = { 0x00, 16 },
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[SCBRR] = { 0x04, 8 },
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[SCSCR] = { 0x08, 16 },
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[SCxTDR] = { 0x40, 8 },
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[SCxSR] = { 0x14, 16 },
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[SCxRDR] = { 0x60, 8 },
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[SCFCR] = { 0x18, 16 },
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[SCFDR] = { 0x1c, 16 },
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[SCTFDR] = sci_reg_invalid,
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[SCRFDR] = sci_reg_invalid,
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[SCSPTR] = sci_reg_invalid,
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[SCLSR] = sci_reg_invalid,
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},
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/*
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* Common SH-3 SCIF definitions.
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*/
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[SCIx_SH3_SCIF_REGTYPE] = {
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[SCSMR] = { 0x00, 8 },
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[SCBRR] = { 0x02, 8 },
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[SCSCR] = { 0x04, 8 },
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[SCxTDR] = { 0x06, 8 },
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[SCxSR] = { 0x08, 16 },
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[SCxRDR] = { 0x0a, 8 },
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[SCFCR] = { 0x0c, 8 },
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[SCFDR] = { 0x0e, 16 },
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[SCTFDR] = sci_reg_invalid,
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[SCRFDR] = sci_reg_invalid,
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[SCSPTR] = sci_reg_invalid,
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[SCLSR] = sci_reg_invalid,
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},
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/*
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* Common SH-4(A) SCIF(B) definitions.
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*/
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[SCIx_SH4_SCIF_REGTYPE] = {
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[SCSMR] = { 0x00, 16 },
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[SCBRR] = { 0x04, 8 },
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[SCSCR] = { 0x08, 16 },
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[SCxTDR] = { 0x0c, 8 },
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[SCxSR] = { 0x10, 16 },
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[SCxRDR] = { 0x14, 8 },
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[SCFCR] = { 0x18, 16 },
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[SCFDR] = { 0x1c, 16 },
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[SCTFDR] = sci_reg_invalid,
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[SCRFDR] = sci_reg_invalid,
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[SCSPTR] = { 0x20, 16 },
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[SCLSR] = { 0x24, 16 },
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},
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/*
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* Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
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* register.
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*/
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[SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
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[SCSMR] = { 0x00, 16 },
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[SCBRR] = { 0x04, 8 },
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[SCSCR] = { 0x08, 16 },
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[SCxTDR] = { 0x0c, 8 },
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[SCxSR] = { 0x10, 16 },
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[SCxRDR] = { 0x14, 8 },
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[SCFCR] = { 0x18, 16 },
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[SCFDR] = { 0x1c, 16 },
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[SCTFDR] = sci_reg_invalid,
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[SCRFDR] = sci_reg_invalid,
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[SCSPTR] = sci_reg_invalid,
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[SCLSR] = { 0x24, 16 },
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},
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/*
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* Common SH-4(A) SCIF(B) definitions for ports with FIFO data
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* count registers.
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*/
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[SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
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[SCSMR] = { 0x00, 16 },
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[SCBRR] = { 0x04, 8 },
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[SCSCR] = { 0x08, 16 },
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[SCxTDR] = { 0x0c, 8 },
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[SCxSR] = { 0x10, 16 },
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[SCxRDR] = { 0x14, 8 },
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[SCFCR] = { 0x18, 16 },
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[SCFDR] = { 0x1c, 16 },
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[SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
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[SCRFDR] = { 0x20, 16 },
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[SCSPTR] = { 0x24, 16 },
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[SCLSR] = { 0x28, 16 },
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},
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/*
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* SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
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* registers.
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*/
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[SCIx_SH7705_SCIF_REGTYPE] = {
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[SCSMR] = { 0x00, 16 },
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[SCBRR] = { 0x04, 8 },
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[SCSCR] = { 0x08, 16 },
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[SCxTDR] = { 0x20, 8 },
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[SCxSR] = { 0x14, 16 },
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[SCxRDR] = { 0x24, 8 },
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[SCFCR] = { 0x18, 16 },
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[SCFDR] = { 0x1c, 16 },
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[SCTFDR] = sci_reg_invalid,
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[SCRFDR] = sci_reg_invalid,
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[SCSPTR] = sci_reg_invalid,
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[SCLSR] = sci_reg_invalid,
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},
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};
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#define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
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/*
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* The "offset" here is rather misleading, in that it refers to an enum
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* value relative to the port mapping rather than the fixed offset
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* itself, which needs to be manually retrieved from the platform's
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* register map for the given port.
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*/
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static unsigned int sci_serial_in(struct uart_port *p, int offset)
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{
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struct plat_sci_reg *reg = sci_getreg(p, offset);
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if (reg->size == 8)
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return ioread8(p->membase + (reg->offset << p->regshift));
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else if (reg->size == 16)
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return ioread16(p->membase + (reg->offset << p->regshift));
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else
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WARN(1, "Invalid register access\n");
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return 0;
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}
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static void sci_serial_out(struct uart_port *p, int offset, int value)
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{
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struct plat_sci_reg *reg = sci_getreg(p, offset);
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if (reg->size == 8)
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iowrite8(value, p->membase + (reg->offset << p->regshift));
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else if (reg->size == 16)
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iowrite16(value, p->membase + (reg->offset << p->regshift));
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else
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WARN(1, "Invalid register access\n");
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}
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#define sci_in(up, offset) (up->serial_in(up, offset))
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#define sci_out(up, offset, value) (up->serial_out(up, offset, value))
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static int sci_probe_regmap(struct plat_sci_port *cfg)
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{
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switch (cfg->type) {
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case PORT_SCI:
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cfg->regtype = SCIx_SCI_REGTYPE;
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break;
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case PORT_IRDA:
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cfg->regtype = SCIx_IRDA_REGTYPE;
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break;
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case PORT_SCIFA:
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cfg->regtype = SCIx_SCIFA_REGTYPE;
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break;
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case PORT_SCIFB:
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cfg->regtype = SCIx_SCIFB_REGTYPE;
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break;
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case PORT_SCIF:
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/*
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* The SH-4 is a bit of a misnomer here, although that's
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* where this particular port layout originated. This
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* configuration (or some slight variation thereof)
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* remains the dominant model for all SCIFs.
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*/
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cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
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break;
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default:
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printk(KERN_ERR "Can't probe register map for given port\n");
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return -EINVAL;
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}
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return 0;
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}
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#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
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#ifdef CONFIG_CONSOLE_POLL
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@@ -164,225 +409,78 @@ static void sci_poll_put_char(struct uart_port *port, unsigned char c)
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}
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#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
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#if defined(__H8300H__) || defined(__H8300S__)
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static void sci_init_pins(struct uart_port *port, unsigned int cflag)
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{
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int ch = (port->mapbase - SMR0) >> 3;
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struct sci_port *s = to_sci_port(port);
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struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
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/* set DDR regs */
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H8300_GPIO_DDR(h8300_sci_pins[ch].port,
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h8300_sci_pins[ch].rx,
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H8300_GPIO_INPUT);
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H8300_GPIO_DDR(h8300_sci_pins[ch].port,
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h8300_sci_pins[ch].tx,
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H8300_GPIO_OUTPUT);
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/* tx mark output*/
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H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
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}
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#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
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static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
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{
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if (port->mapbase == 0xA4400000) {
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__raw_writew(__raw_readw(PACR) & 0xffc0, PACR);
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__raw_writew(__raw_readw(PBCR) & 0x0fff, PBCR);
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} else if (port->mapbase == 0xA4410000)
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__raw_writew(__raw_readw(PBCR) & 0xf003, PBCR);
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}
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#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721)
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static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
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{
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unsigned short data;
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if (cflag & CRTSCTS) {
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/* enable RTS/CTS */
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if (port->mapbase == 0xa4430000) { /* SCIF0 */
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/* Clear PTCR bit 9-2; enable all scif pins but sck */
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data = __raw_readw(PORT_PTCR);
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__raw_writew((data & 0xfc03), PORT_PTCR);
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} else if (port->mapbase == 0xa4438000) { /* SCIF1 */
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/* Clear PVCR bit 9-2 */
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data = __raw_readw(PORT_PVCR);
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__raw_writew((data & 0xfc03), PORT_PVCR);
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}
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} else {
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if (port->mapbase == 0xa4430000) { /* SCIF0 */
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/* Clear PTCR bit 5-2; enable only tx and rx */
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data = __raw_readw(PORT_PTCR);
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__raw_writew((data & 0xffc3), PORT_PTCR);
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} else if (port->mapbase == 0xa4438000) { /* SCIF1 */
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/* Clear PVCR bit 5-2 */
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data = __raw_readw(PORT_PVCR);
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__raw_writew((data & 0xffc3), PORT_PVCR);
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}
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/*
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* Use port-specific handler if provided.
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*/
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if (s->cfg->ops && s->cfg->ops->init_pins) {
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s->cfg->ops->init_pins(port, cflag);
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return;
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}
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}
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#elif defined(CONFIG_CPU_SH3)
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/* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
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static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
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{
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unsigned short data;
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/* We need to set SCPCR to enable RTS/CTS */
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data = __raw_readw(SCPCR);
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/* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
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__raw_writew(data & 0x0fcf, SCPCR);
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/*
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* For the generic path SCSPTR is necessary. Bail out if that's
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* unavailable, too.
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*/
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if (!reg->size)
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return;
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if (!(cflag & CRTSCTS)) {
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/* We need to set SCPCR to enable RTS/CTS */
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data = __raw_readw(SCPCR);
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/* Clear out SCP7MD1,0, SCP4MD1,0,
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Set SCP6MD1,0 = {01} (output) */
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__raw_writew((data & 0x0fcf) | 0x1000, SCPCR);
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data = __raw_readb(SCPDR);
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/* Set /RTS2 (bit6) = 0 */
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__raw_writeb(data & 0xbf, SCPDR);
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}
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}
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#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
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static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
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{
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unsigned short data;
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if (port->mapbase == 0xffe00000) {
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data = __raw_readw(PSCR);
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data &= ~0x03cf;
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if (!(cflag & CRTSCTS))
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data |= 0x0340;
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__raw_writew(data, PSCR);
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}
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}
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#elif defined(CONFIG_CPU_SUBTYPE_SH7757) || \
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defined(CONFIG_CPU_SUBTYPE_SH7763) || \
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defined(CONFIG_CPU_SUBTYPE_SH7780) || \
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defined(CONFIG_CPU_SUBTYPE_SH7785) || \
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defined(CONFIG_CPU_SUBTYPE_SH7786) || \
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defined(CONFIG_CPU_SUBTYPE_SHX3)
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static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
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{
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if (!(cflag & CRTSCTS))
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__raw_writew(0x0080, SCSPTR0); /* Set RTS = 1 */
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sci_out(port, SCSPTR, 0x0080); /* Set RTS = 1 */
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}
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#elif defined(CONFIG_CPU_SH4) && !defined(CONFIG_CPU_SH4A)
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static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
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{
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if (!(cflag & CRTSCTS))
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__raw_writew(0x0080, SCSPTR2); /* Set RTS = 1 */
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}
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#else
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static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
|
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{
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/* Nothing to do */
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}
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
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defined(CONFIG_CPU_SUBTYPE_SH7780) || \
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defined(CONFIG_CPU_SUBTYPE_SH7785) || \
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defined(CONFIG_CPU_SUBTYPE_SH7786)
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static int scif_txfill(struct uart_port *port)
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{
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return sci_in(port, SCTFDR) & 0xff;
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}
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||||
|
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static int scif_txroom(struct uart_port *port)
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{
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return SCIF_TXROOM_MAX - scif_txfill(port);
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||||
}
|
||||
|
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static int scif_rxfill(struct uart_port *port)
|
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{
|
||||
return sci_in(port, SCRFDR) & 0xff;
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||||
}
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#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
|
||||
static int scif_txfill(struct uart_port *port)
|
||||
{
|
||||
if (port->mapbase == 0xffe00000 ||
|
||||
port->mapbase == 0xffe08000)
|
||||
/* SCIF0/1*/
|
||||
return sci_in(port, SCTFDR) & 0xff;
|
||||
else
|
||||
/* SCIF2 */
|
||||
return sci_in(port, SCFDR) >> 8;
|
||||
}
|
||||
|
||||
static int scif_txroom(struct uart_port *port)
|
||||
{
|
||||
if (port->mapbase == 0xffe00000 ||
|
||||
port->mapbase == 0xffe08000)
|
||||
/* SCIF0/1*/
|
||||
return SCIF_TXROOM_MAX - scif_txfill(port);
|
||||
else
|
||||
/* SCIF2 */
|
||||
return SCIF2_TXROOM_MAX - scif_txfill(port);
|
||||
}
|
||||
|
||||
static int scif_rxfill(struct uart_port *port)
|
||||
{
|
||||
if ((port->mapbase == 0xffe00000) ||
|
||||
(port->mapbase == 0xffe08000)) {
|
||||
/* SCIF0/1*/
|
||||
return sci_in(port, SCRFDR) & 0xff;
|
||||
} else {
|
||||
/* SCIF2 */
|
||||
return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
|
||||
}
|
||||
}
|
||||
#elif defined(CONFIG_ARCH_SH7372)
|
||||
static int scif_txfill(struct uart_port *port)
|
||||
{
|
||||
if (port->type == PORT_SCIFA)
|
||||
return sci_in(port, SCFDR) >> 8;
|
||||
else
|
||||
return sci_in(port, SCTFDR);
|
||||
}
|
||||
|
||||
static int scif_txroom(struct uart_port *port)
|
||||
{
|
||||
return port->fifosize - scif_txfill(port);
|
||||
}
|
||||
|
||||
static int scif_rxfill(struct uart_port *port)
|
||||
{
|
||||
if (port->type == PORT_SCIFA)
|
||||
return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
|
||||
else
|
||||
return sci_in(port, SCRFDR);
|
||||
}
|
||||
#else
|
||||
static int scif_txfill(struct uart_port *port)
|
||||
{
|
||||
return sci_in(port, SCFDR) >> 8;
|
||||
}
|
||||
|
||||
static int scif_txroom(struct uart_port *port)
|
||||
{
|
||||
return SCIF_TXROOM_MAX - scif_txfill(port);
|
||||
}
|
||||
|
||||
static int scif_rxfill(struct uart_port *port)
|
||||
{
|
||||
return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
|
||||
}
|
||||
#endif
|
||||
|
||||
static int sci_txfill(struct uart_port *port)
|
||||
{
|
||||
struct plat_sci_reg *reg;
|
||||
|
||||
reg = sci_getreg(port, SCTFDR);
|
||||
if (reg->size)
|
||||
return sci_in(port, SCTFDR) & 0xff;
|
||||
|
||||
reg = sci_getreg(port, SCFDR);
|
||||
if (reg->size)
|
||||
return sci_in(port, SCFDR) >> 8;
|
||||
|
||||
return !(sci_in(port, SCxSR) & SCI_TDRE);
|
||||
}
|
||||
|
||||
static int sci_txroom(struct uart_port *port)
|
||||
{
|
||||
return !sci_txfill(port);
|
||||
return port->fifosize - sci_txfill(port);
|
||||
}
|
||||
|
||||
static int sci_rxfill(struct uart_port *port)
|
||||
{
|
||||
struct plat_sci_reg *reg;
|
||||
|
||||
reg = sci_getreg(port, SCRFDR);
|
||||
if (reg->size)
|
||||
return sci_in(port, SCRFDR) & 0xff;
|
||||
|
||||
reg = sci_getreg(port, SCFDR);
|
||||
if (reg->size)
|
||||
return sci_in(port, SCFDR) & ((port->fifosize << 1) - 1);
|
||||
|
||||
return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* SCI helper for checking the state of the muxed port/RXD pins.
|
||||
*/
|
||||
static inline int sci_rxd_in(struct uart_port *port)
|
||||
{
|
||||
struct sci_port *s = to_sci_port(port);
|
||||
|
||||
if (s->cfg->port_reg <= 0)
|
||||
return 1;
|
||||
|
||||
return !!__raw_readb(s->cfg->port_reg);
|
||||
}
|
||||
|
||||
/* ********************************************************************** *
|
||||
* the interrupt related routines *
|
||||
* ********************************************************************** */
|
||||
@@ -406,10 +504,7 @@ static void sci_transmit_chars(struct uart_port *port)
|
||||
return;
|
||||
}
|
||||
|
||||
if (port->type == PORT_SCI)
|
||||
count = sci_txroom(port);
|
||||
else
|
||||
count = scif_txroom(port);
|
||||
count = sci_txroom(port);
|
||||
|
||||
do {
|
||||
unsigned char c;
|
||||
@@ -464,13 +559,8 @@ static void sci_receive_chars(struct uart_port *port)
|
||||
return;
|
||||
|
||||
while (1) {
|
||||
if (port->type == PORT_SCI)
|
||||
count = sci_rxfill(port);
|
||||
else
|
||||
count = scif_rxfill(port);
|
||||
|
||||
/* Don't copy more bytes than there is room for in the buffer */
|
||||
count = tty_buffer_request_room(tty, count);
|
||||
count = tty_buffer_request_room(tty, sci_rxfill(port));
|
||||
|
||||
/* If for any reason we can't copy more data, we're done! */
|
||||
if (count == 0)
|
||||
@@ -583,13 +673,19 @@ static int sci_handle_errors(struct uart_port *port)
|
||||
int copied = 0;
|
||||
unsigned short status = sci_in(port, SCxSR);
|
||||
struct tty_struct *tty = port->state->port.tty;
|
||||
struct sci_port *s = to_sci_port(port);
|
||||
|
||||
if (status & SCxSR_ORER(port)) {
|
||||
/* overrun error */
|
||||
if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
|
||||
copied++;
|
||||
/*
|
||||
* Handle overruns, if supported.
|
||||
*/
|
||||
if (s->cfg->overrun_bit != SCIx_NOT_SUPPORTED) {
|
||||
if (status & (1 << s->cfg->overrun_bit)) {
|
||||
/* overrun error */
|
||||
if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
|
||||
copied++;
|
||||
|
||||
dev_notice(port->dev, "overrun error");
|
||||
dev_notice(port->dev, "overrun error");
|
||||
}
|
||||
}
|
||||
|
||||
if (status & SCxSR_FER(port)) {
|
||||
@@ -637,12 +733,15 @@ static int sci_handle_errors(struct uart_port *port)
|
||||
static int sci_handle_fifo_overrun(struct uart_port *port)
|
||||
{
|
||||
struct tty_struct *tty = port->state->port.tty;
|
||||
struct sci_port *s = to_sci_port(port);
|
||||
struct plat_sci_reg *reg;
|
||||
int copied = 0;
|
||||
|
||||
if (port->type != PORT_SCIF)
|
||||
reg = sci_getreg(port, SCLSR);
|
||||
if (!reg->size)
|
||||
return 0;
|
||||
|
||||
if ((sci_in(port, SCLSR) & SCIF_ORER) != 0) {
|
||||
if ((sci_in(port, SCLSR) & (1 << s->cfg->overrun_bit))) {
|
||||
sci_out(port, SCLSR, 0);
|
||||
|
||||
tty_insert_flip_char(tty, 0, TTY_OVERRUN);
|
||||
@@ -915,7 +1014,7 @@ static void sci_free_irq(struct sci_port *port)
|
||||
static unsigned int sci_tx_empty(struct uart_port *port)
|
||||
{
|
||||
unsigned short status = sci_in(port, SCxSR);
|
||||
unsigned short in_tx_fifo = scif_txfill(port);
|
||||
unsigned short in_tx_fifo = sci_txfill(port);
|
||||
|
||||
return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
|
||||
}
|
||||
@@ -1746,6 +1845,9 @@ static int __devinit sci_init_single(struct platform_device *dev,
|
||||
break;
|
||||
}
|
||||
|
||||
if (p->regtype == SCIx_PROBE_REGTYPE)
|
||||
BUG_ON(sci_probe_regmap(p) != 0);
|
||||
|
||||
if (dev) {
|
||||
sci_port->iclk = clk_get(&dev->dev, "sci_ick");
|
||||
if (IS_ERR(sci_port->iclk)) {
|
||||
@@ -1775,14 +1877,41 @@ static int __devinit sci_init_single(struct platform_device *dev,
|
||||
sci_port->break_timer.function = sci_break_timer;
|
||||
init_timer(&sci_port->break_timer);
|
||||
|
||||
/*
|
||||
* Establish some sensible defaults for the error detection.
|
||||
*/
|
||||
if (!p->error_mask)
|
||||
p->error_mask = (p->type == PORT_SCI) ?
|
||||
SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK;
|
||||
|
||||
/*
|
||||
* Establish sensible defaults for the overrun detection, unless
|
||||
* the part has explicitly disabled support for it.
|
||||
*/
|
||||
if (p->overrun_bit != SCIx_NOT_SUPPORTED) {
|
||||
if (p->type == PORT_SCI)
|
||||
p->overrun_bit = 5;
|
||||
else if (p->scbrr_algo_id == SCBRR_ALGO_4)
|
||||
p->overrun_bit = 9;
|
||||
else
|
||||
p->overrun_bit = 0;
|
||||
|
||||
/*
|
||||
* Make the error mask inclusive of overrun detection, if
|
||||
* supported.
|
||||
*/
|
||||
p->error_mask |= (1 << p->overrun_bit);
|
||||
}
|
||||
|
||||
sci_port->cfg = p;
|
||||
|
||||
port->mapbase = p->mapbase;
|
||||
port->type = p->type;
|
||||
port->flags = p->flags;
|
||||
port->regshift = p->regshift;
|
||||
|
||||
/*
|
||||
* The UART port needs an IRQ value, so we peg this to the TX IRQ
|
||||
* The UART port needs an IRQ value, so we peg this to the RX IRQ
|
||||
* for the multi-IRQ ports, which is where we are primarily
|
||||
* concerned with the shutdown path synchronization.
|
||||
*
|
||||
@@ -1790,6 +1919,9 @@ static int __devinit sci_init_single(struct platform_device *dev,
|
||||
*/
|
||||
port->irq = p->irqs[SCIx_RXI_IRQ];
|
||||
|
||||
port->serial_in = sci_serial_in;
|
||||
port->serial_out = sci_serial_out;
|
||||
|
||||
if (p->dma_dev)
|
||||
dev_dbg(port->dev, "DMA device %p, tx %d, rx %d\n",
|
||||
p->dma_dev, p->dma_slave_tx, p->dma_slave_rx);
|
||||
@@ -1863,14 +1995,8 @@ static int __devinit serial_console_setup(struct console *co, char *options)
|
||||
if (options)
|
||||
uart_parse_options(options, &baud, &parity, &bits, &flow);
|
||||
|
||||
ret = uart_set_options(port, co, baud, parity, bits, flow);
|
||||
#if defined(__H8300H__) || defined(__H8300S__)
|
||||
/* disable rx interrupt */
|
||||
if (ret == 0)
|
||||
sci_stop_rx(port);
|
||||
#endif
|
||||
/* TODO: disable clock */
|
||||
return ret;
|
||||
return uart_set_options(port, co, baud, parity, bits, flow);
|
||||
}
|
||||
|
||||
static struct console serial_console = {
|
||||
|
||||
+2
-432
@@ -2,169 +2,14 @@
|
||||
#include <linux/io.h>
|
||||
#include <linux/gpio.h>
|
||||
|
||||
#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
|
||||
#include <asm/regs306x.h>
|
||||
#endif
|
||||
#if defined(CONFIG_H8S2678)
|
||||
#include <asm/regs267x.h>
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7707) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7708) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7709)
|
||||
# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
|
||||
# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
|
||||
# define SCIF0 0xA4400000
|
||||
# define SCIF2 0xA4410000
|
||||
# define SCPCR 0xA4000116
|
||||
# define SCPDR 0xA4000136
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7721) || \
|
||||
defined(CONFIG_ARCH_SH73A0) || \
|
||||
defined(CONFIG_ARCH_SH7367) || \
|
||||
defined(CONFIG_ARCH_SH7377) || \
|
||||
defined(CONFIG_ARCH_SH7372)
|
||||
# define PORT_PTCR 0xA405011EUL
|
||||
# define PORT_PVCR 0xA4050122UL
|
||||
# define SCIF_ORER 0x0200 /* overrun error bit */
|
||||
#elif defined(CONFIG_SH_RTS7751R2D)
|
||||
# define SCSPTR1 0xFFE0001C /* 8 bit SCIF */
|
||||
# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
|
||||
# define SCIF_ORER 0x0001 /* overrun error bit */
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7091) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7751) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7751R)
|
||||
# define SCSPTR1 0xffe0001c /* 8 bit SCI */
|
||||
# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
|
||||
# define SCIF_ORER 0x0001 /* overrun error bit */
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
|
||||
# define SCSPTR0 0xfe600024 /* 16 bit SCIF */
|
||||
# define SCSPTR1 0xfe610024 /* 16 bit SCIF */
|
||||
# define SCSPTR2 0xfe620024 /* 16 bit SCIF */
|
||||
# define SCIF_ORER 0x0001 /* overrun error bit */
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
|
||||
# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
|
||||
# define SCIF_ORER 0x0001 /* overrun error bit */
|
||||
# define PACR 0xa4050100
|
||||
# define PBCR 0xa4050102
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
|
||||
# define SCSPTR0 0xffe00010 /* 16 bit SCIF */
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
|
||||
# define PADR 0xA4050120
|
||||
# define PSDR 0xA405013e
|
||||
# define PWDR 0xA4050166
|
||||
# define PSCR 0xA405011E
|
||||
# define SCIF_ORER 0x0001 /* overrun error bit */
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7366)
|
||||
# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
|
||||
# define SCSPTR0 SCPDR0
|
||||
# define SCIF_ORER 0x0001 /* overrun error bit */
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
|
||||
# define SCSPTR0 0xa4050160
|
||||
# define SCIF_ORER 0x0001 /* overrun error bit */
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
|
||||
# define SCIF_ORER 0x0001 /* overrun error bit */
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
|
||||
# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
|
||||
# define SCIF_ORER 0x0001 /* overrun error bit */
|
||||
#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
|
||||
# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
|
||||
#elif defined(CONFIG_H8S2678)
|
||||
# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7757)
|
||||
# define SCSPTR0 0xfe4b0020
|
||||
# define SCIF_ORER 0x0001
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
|
||||
# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
|
||||
# define SCIF_ORER 0x0001 /* overrun error bit */
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
|
||||
# define SCSPTR0 0xff923020 /* 16 bit SCIF */
|
||||
# define SCIF_ORER 0x0001 /* overrun error bit */
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
|
||||
# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
|
||||
# define SCIF_ORER 0x0001 /* Overrun error bit */
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7786)
|
||||
# define SCSPTR0 0xffea0024 /* 16 bit SCIF */
|
||||
# define SCIF_ORER 0x0001 /* Overrun error bit */
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7203) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7206) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7263)
|
||||
# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
|
||||
# define SCSPTR0 0xf8400020 /* 16 bit SCIF */
|
||||
# define SCIF_ORER 0x0001 /* overrun error bit */
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
|
||||
# define SCSPTR0 0xffc30020 /* 16 bit SCIF */
|
||||
# define SCIF_ORER 0x0001 /* Overrun error bit */
|
||||
#else
|
||||
# error CPU subtype not defined
|
||||
#endif
|
||||
|
||||
/* SCxSR SCI */
|
||||
#define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
|
||||
#define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
|
||||
#define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
|
||||
#define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
|
||||
#define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
|
||||
#define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
|
||||
/* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
|
||||
/* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
|
||||
|
||||
#define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
|
||||
|
||||
/* SCxSR SCIF */
|
||||
#define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
|
||||
#define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
|
||||
#define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
|
||||
#define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
|
||||
#define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
|
||||
#define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
|
||||
#define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
|
||||
#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7720) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7721) || \
|
||||
defined(CONFIG_ARCH_SH73A0) || \
|
||||
defined(CONFIG_ARCH_SH7367) || \
|
||||
defined(CONFIG_ARCH_SH7377) || \
|
||||
defined(CONFIG_ARCH_SH7372)
|
||||
# define SCIF_ORER 0x0200
|
||||
# define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
|
||||
# define SCIF_RFDC_MASK 0x007f
|
||||
# define SCIF_TXROOM_MAX 64
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
|
||||
# define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK )
|
||||
# define SCIF_RFDC_MASK 0x007f
|
||||
# define SCIF_TXROOM_MAX 64
|
||||
/* SH7763 SCIF2 support */
|
||||
# define SCIF2_RFDC_MASK 0x001f
|
||||
# define SCIF2_TXROOM_MAX 16
|
||||
#else
|
||||
# define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
|
||||
# define SCIF_RFDC_MASK 0x001f
|
||||
# define SCIF_TXROOM_MAX 16
|
||||
#endif
|
||||
|
||||
#ifndef SCIF_ORER
|
||||
#define SCIF_ORER 0x0000
|
||||
#endif
|
||||
|
||||
#define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
|
||||
#define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
|
||||
#define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
|
||||
#define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
|
||||
#define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
|
||||
#define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
|
||||
#define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
|
||||
#define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER)
|
||||
|
||||
#define SCxSR_ERRORS(port) (to_sci_port(port)->cfg->error_mask)
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7720) || \
|
||||
@@ -191,278 +36,3 @@
|
||||
|
||||
#define SCI_MAJOR 204
|
||||
#define SCI_MINOR_START 8
|
||||
|
||||
#define SCI_IN(size, offset) \
|
||||
if ((size) == 8) { \
|
||||
return ioread8(port->membase + (offset)); \
|
||||
} else { \
|
||||
return ioread16(port->membase + (offset)); \
|
||||
}
|
||||
#define SCI_OUT(size, offset, value) \
|
||||
if ((size) == 8) { \
|
||||
iowrite8(value, port->membase + (offset)); \
|
||||
} else if ((size) == 16) { \
|
||||
iowrite16(value, port->membase + (offset)); \
|
||||
}
|
||||
|
||||
#define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
|
||||
static inline unsigned int sci_##name##_in(struct uart_port *port) \
|
||||
{ \
|
||||
if (port->type == PORT_SCIF || port->type == PORT_SCIFB) { \
|
||||
SCI_IN(scif_size, scif_offset) \
|
||||
} else { /* PORT_SCI or PORT_SCIFA */ \
|
||||
SCI_IN(sci_size, sci_offset); \
|
||||
} \
|
||||
} \
|
||||
static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
|
||||
{ \
|
||||
if (port->type == PORT_SCIF || port->type == PORT_SCIFB) { \
|
||||
SCI_OUT(scif_size, scif_offset, value) \
|
||||
} else { /* PORT_SCI or PORT_SCIFA */ \
|
||||
SCI_OUT(sci_size, sci_offset, value); \
|
||||
} \
|
||||
}
|
||||
|
||||
#ifdef CONFIG_H8300
|
||||
/* h8300 don't have SCIF */
|
||||
#define CPU_SCIF_FNS(name) \
|
||||
static inline unsigned int sci_##name##_in(struct uart_port *port) \
|
||||
{ \
|
||||
return 0; \
|
||||
} \
|
||||
static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
|
||||
{ \
|
||||
}
|
||||
#else
|
||||
#define CPU_SCIF_FNS(name, scif_offset, scif_size) \
|
||||
static inline unsigned int sci_##name##_in(struct uart_port *port) \
|
||||
{ \
|
||||
SCI_IN(scif_size, scif_offset); \
|
||||
} \
|
||||
static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
|
||||
{ \
|
||||
SCI_OUT(scif_size, scif_offset, value); \
|
||||
}
|
||||
#endif
|
||||
|
||||
#define CPU_SCI_FNS(name, sci_offset, sci_size) \
|
||||
static inline unsigned int sci_##name##_in(struct uart_port* port) \
|
||||
{ \
|
||||
SCI_IN(sci_size, sci_offset); \
|
||||
} \
|
||||
static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \
|
||||
{ \
|
||||
SCI_OUT(sci_size, sci_offset, value); \
|
||||
}
|
||||
|
||||
#if defined(CONFIG_CPU_SH3) || \
|
||||
defined(CONFIG_ARCH_SH73A0) || \
|
||||
defined(CONFIG_ARCH_SH7367) || \
|
||||
defined(CONFIG_ARCH_SH7377) || \
|
||||
defined(CONFIG_ARCH_SH7372)
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
|
||||
#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
|
||||
sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
|
||||
h8_sci_offset, h8_sci_size) \
|
||||
CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
|
||||
#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
|
||||
CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7720) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7721) || \
|
||||
defined(CONFIG_ARCH_SH7367)
|
||||
#define SCIF_FNS(name, scif_offset, scif_size) \
|
||||
CPU_SCIF_FNS(name, scif_offset, scif_size)
|
||||
#elif defined(CONFIG_ARCH_SH7377) || \
|
||||
defined(CONFIG_ARCH_SH7372) || \
|
||||
defined(CONFIG_ARCH_SH73A0)
|
||||
#define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scifb_offset, sh4_scifb_size) \
|
||||
CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scifb_offset, sh4_scifb_size)
|
||||
#define SCIF_FNS(name, scif_offset, scif_size) \
|
||||
CPU_SCIF_FNS(name, scif_offset, scif_size)
|
||||
#else
|
||||
#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
|
||||
sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
|
||||
h8_sci_offset, h8_sci_size) \
|
||||
CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)
|
||||
#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
|
||||
CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
|
||||
#endif
|
||||
#elif defined(__H8300H__) || defined(__H8300S__)
|
||||
#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
|
||||
sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
|
||||
h8_sci_offset, h8_sci_size) \
|
||||
CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
|
||||
#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
|
||||
CPU_SCIF_FNS(name)
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7724)
|
||||
#define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) \
|
||||
CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size)
|
||||
#define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
|
||||
CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
|
||||
#else
|
||||
#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
|
||||
sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
|
||||
h8_sci_offset, h8_sci_size) \
|
||||
CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
|
||||
#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
|
||||
CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7720) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7721) || \
|
||||
defined(CONFIG_ARCH_SH7367)
|
||||
|
||||
SCIF_FNS(SCSMR, 0x00, 16)
|
||||
SCIF_FNS(SCBRR, 0x04, 8)
|
||||
SCIF_FNS(SCSCR, 0x08, 16)
|
||||
SCIF_FNS(SCxSR, 0x14, 16)
|
||||
SCIF_FNS(SCFCR, 0x18, 16)
|
||||
SCIF_FNS(SCFDR, 0x1c, 16)
|
||||
SCIF_FNS(SCxTDR, 0x20, 8)
|
||||
SCIF_FNS(SCxRDR, 0x24, 8)
|
||||
SCIF_FNS(SCLSR, 0x00, 0)
|
||||
#elif defined(CONFIG_ARCH_SH7377) || \
|
||||
defined(CONFIG_ARCH_SH7372) || \
|
||||
defined(CONFIG_ARCH_SH73A0)
|
||||
SCIF_FNS(SCSMR, 0x00, 16)
|
||||
SCIF_FNS(SCBRR, 0x04, 8)
|
||||
SCIF_FNS(SCSCR, 0x08, 16)
|
||||
SCIF_FNS(SCTDSR, 0x0c, 16)
|
||||
SCIF_FNS(SCFER, 0x10, 16)
|
||||
SCIF_FNS(SCxSR, 0x14, 16)
|
||||
SCIF_FNS(SCFCR, 0x18, 16)
|
||||
SCIF_FNS(SCFDR, 0x1c, 16)
|
||||
SCIF_FNS(SCTFDR, 0x38, 16)
|
||||
SCIF_FNS(SCRFDR, 0x3c, 16)
|
||||
SCIx_FNS(SCxTDR, 0x20, 8, 0x40, 8)
|
||||
SCIx_FNS(SCxRDR, 0x24, 8, 0x60, 8)
|
||||
SCIF_FNS(SCLSR, 0x00, 0)
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7724)
|
||||
SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16)
|
||||
SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8)
|
||||
SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16)
|
||||
SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8)
|
||||
SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16)
|
||||
SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8)
|
||||
SCIx_FNS(SCSPTR, 0, 0, 0, 0)
|
||||
SCIF_FNS(SCFCR, 0x18, 16)
|
||||
SCIF_FNS(SCFDR, 0x1c, 16)
|
||||
SCIF_FNS(SCLSR, 0x24, 16)
|
||||
#else
|
||||
/* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
|
||||
/* name off sz off sz off sz off sz off sz*/
|
||||
SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8)
|
||||
SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8)
|
||||
SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8)
|
||||
SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
|
||||
SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
|
||||
SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
|
||||
SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7780) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7785) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7786)
|
||||
SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
|
||||
SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
|
||||
SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
|
||||
SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
|
||||
SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
|
||||
SCIF_FNS(SCFDR, 0, 0, 0x1C, 16)
|
||||
SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
|
||||
SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
|
||||
SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
|
||||
SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
|
||||
#else
|
||||
SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7722)
|
||||
SCIF_FNS(SCSPTR, 0, 0, 0, 0)
|
||||
#else
|
||||
SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
|
||||
#endif
|
||||
SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
|
||||
#endif
|
||||
#endif
|
||||
#define sci_in(port, reg) sci_##reg##_in(port)
|
||||
#define sci_out(port, reg, value) sci_##reg##_out(port, value)
|
||||
|
||||
/* H8/300 series SCI pins assignment */
|
||||
#if defined(__H8300H__) || defined(__H8300S__)
|
||||
static const struct __attribute__((packed)) {
|
||||
int port; /* GPIO port no */
|
||||
unsigned short rx,tx; /* GPIO bit no */
|
||||
} h8300_sci_pins[] = {
|
||||
#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
|
||||
{ /* SCI0 */
|
||||
.port = H8300_GPIO_P9,
|
||||
.rx = H8300_GPIO_B2,
|
||||
.tx = H8300_GPIO_B0,
|
||||
},
|
||||
{ /* SCI1 */
|
||||
.port = H8300_GPIO_P9,
|
||||
.rx = H8300_GPIO_B3,
|
||||
.tx = H8300_GPIO_B1,
|
||||
},
|
||||
{ /* SCI2 */
|
||||
.port = H8300_GPIO_PB,
|
||||
.rx = H8300_GPIO_B7,
|
||||
.tx = H8300_GPIO_B6,
|
||||
}
|
||||
#elif defined(CONFIG_H8S2678)
|
||||
{ /* SCI0 */
|
||||
.port = H8300_GPIO_P3,
|
||||
.rx = H8300_GPIO_B2,
|
||||
.tx = H8300_GPIO_B0,
|
||||
},
|
||||
{ /* SCI1 */
|
||||
.port = H8300_GPIO_P3,
|
||||
.rx = H8300_GPIO_B3,
|
||||
.tx = H8300_GPIO_B1,
|
||||
},
|
||||
{ /* SCI2 */
|
||||
.port = H8300_GPIO_P5,
|
||||
.rx = H8300_GPIO_B1,
|
||||
.tx = H8300_GPIO_B0,
|
||||
}
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7707) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7708) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7709)
|
||||
static inline int sci_rxd_in(struct uart_port *port)
|
||||
{
|
||||
if (port->mapbase == 0xfffffe80)
|
||||
return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */
|
||||
return 1;
|
||||
}
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7751) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7091)
|
||||
static inline int sci_rxd_in(struct uart_port *port)
|
||||
{
|
||||
if (port->mapbase == 0xffe00000)
|
||||
return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
|
||||
return 1;
|
||||
}
|
||||
#elif defined(__H8300H__) || defined(__H8300S__)
|
||||
static inline int sci_rxd_in(struct uart_port *port)
|
||||
{
|
||||
int ch = (port->mapbase - SMR0) >> 3;
|
||||
return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
|
||||
}
|
||||
#else /* default case for non-SCI processors */
|
||||
static inline int sci_rxd_in(struct uart_port *port)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user