From 0cee980cc7e15a396637b71ee0bf2f9838c701e2 Mon Sep 17 00:00:00 2001 From: Oleg Karfich Date: Tue, 10 Feb 2026 16:07:34 +0100 Subject: [PATCH] arm64: dts: k3-am623-pfc-750-84xx-baseboard: move KSZ9477 reset pin to MCU GPIO Move the reset GPIO pin for the KSZ9477 Ethernet switch from main_gpio1 pin 10 to mcu_gpio0 pin 11 to match the actual hardware configuration. This change: - Removes the reset pin definition from main_pmx0 pinctrl group - Adds a new mcu_pmx0 pinctrl group for the MCU GPIO configuration - Updates the ksz9477 device node to reference both pinctrl groups - Changes reset-gpios from main_gpio1 10 to mcu_gpio0 11 Signed-off-by: Oleg Karfich --- .../dts/ti/k3-am623-pfc-750-84xx-baseboard.dtsi | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am623-pfc-750-84xx-baseboard.dtsi b/arch/arm64/boot/dts/ti/k3-am623-pfc-750-84xx-baseboard.dtsi index 034bb4327f85..b9f971a9b12b 100644 --- a/arch/arm64/boot/dts/ti/k3-am623-pfc-750-84xx-baseboard.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am623-pfc-750-84xx-baseboard.dtsi @@ -9,21 +9,28 @@ &main_pmx0 { main_ksz9477_pins: main-ksz9477-pins { pinctrl-single,pins = < - AM62X_IOPAD(0x01a0, PIN_OUTPUT, 7) /* (E18) MCASP0_AXR0.GPIO1_10 nRST-RGMII2 / nRST-ETHSW (BB) */ AM62X_IOPAD(0x0034, PIN_INPUT, 7) /* (H21) OSPI0_CSn2.GPIO0_13 nINT-RGMII2 / nINT-ETHSW(BB) */ >; }; }; +&mcu_pmx0 { + mcu_ksz9477_pins: mcu-ksz9477-pins { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x002c, PIN_OUTPUT, 7) /* (C6) WKUP_UART0_CTSn.MCU_GPIO0_11 nRST-RGMII2 / nRST-ETHSW(BB) */ + >; + }; +}; + &mcu_spi0 { ksz9477@0 { compatible = "microchip,ksz9477"; pinctrl-names = "default"; - pinctrl-0 = <&main_ksz9477_pins>; + pinctrl-0 = <&main_ksz9477_pins>, <&mcu_ksz9477_pins>; reg = <0>; spi-max-frequency = <1000000>; - reset-gpios = <&main_gpio1 10 GPIO_ACTIVE_LOW>; + reset-gpios = <&mcu_gpio0 11 GPIO_ACTIVE_LOW>; dsa,member = <0 0>;