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drm/tegra: sor: Remove unnecessary conditional

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Checking for sor->aux in eDP specific code is unnecessary because eDP
inherently requires a valid AUX channel.

Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Thierry Reding
2015-11-11 17:15:29 +01:00
parent 9542c2376e
commit 01b9bea0c2
1 changed files with 43 additions and 54 deletions
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drivers/gpu/drm/tegra/sor.c
+43 -54
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@@ -1196,6 +1196,7 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder)
struct tegra_sor *sor = to_sor(output); struct tegra_sor *sor = to_sor(output);
struct tegra_sor_config config; struct tegra_sor_config config;
struct drm_dp_link link; struct drm_dp_link link;
u8 rate, lanes;
int err = 0; int err = 0;
u32 value; u32 value;
@@ -1208,17 +1209,14 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder)
if (output->panel) if (output->panel)
drm_panel_prepare(output->panel); drm_panel_prepare(output->panel);
if (sor->aux) { err = drm_dp_aux_enable(sor->aux);
err = drm_dp_aux_enable(sor->aux); if (err < 0)
if (err < 0) dev_err(sor->dev, "failed to enable DP: %d\n", err);
dev_err(sor->dev, "failed to enable DP: %d\n", err);
err = drm_dp_link_probe(sor->aux, &link); err = drm_dp_link_probe(sor->aux, &link);
if (err < 0) { if (err < 0) {
dev_err(sor->dev, "failed to probe eDP link: %d\n", dev_err(sor->dev, "failed to probe eDP link: %d\n", err);
err); return;
return;
}
} }
err = clk_set_parent(sor->clk, sor->clk_safe); err = clk_set_parent(sor->clk, sor->clk_safe);
@@ -1430,61 +1428,52 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder)
value |= SOR_DP_PADCTL_PAD_CAL_PD; value |= SOR_DP_PADCTL_PAD_CAL_PD;
tegra_sor_writel(sor, value, SOR_DP_PADCTL0); tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
if (sor->aux) { err = drm_dp_link_probe(sor->aux, &link);
u8 rate, lanes; if (err < 0)
dev_err(sor->dev, "failed to probe eDP link: %d\n", err);
err = drm_dp_link_probe(sor->aux, &link); err = drm_dp_link_power_up(sor->aux, &link);
if (err < 0) if (err < 0)
dev_err(sor->dev, "failed to probe eDP link: %d\n", dev_err(sor->dev, "failed to power up eDP link: %d\n", err);
err);
err = drm_dp_link_power_up(sor->aux, &link); err = drm_dp_link_configure(sor->aux, &link);
if (err < 0) if (err < 0)
dev_err(sor->dev, "failed to power up eDP link: %d\n", dev_err(sor->dev, "failed to configure eDP link: %d\n", err);
err);
err = drm_dp_link_configure(sor->aux, &link); rate = drm_dp_link_rate_to_bw_code(link.rate);
if (err < 0) lanes = link.num_lanes;
dev_err(sor->dev, "failed to configure eDP link: %d\n",
err);
rate = drm_dp_link_rate_to_bw_code(link.rate); value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
lanes = link.num_lanes; value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate);
tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
value = tegra_sor_readl(sor, SOR_CLK_CNTRL); value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate); value |= SOR_DP_LINKCTL_LANE_COUNT(lanes);
tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); if (link.capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
value |= SOR_DP_LINKCTL_LANE_COUNT(lanes);
if (link.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); /* disable training pattern generator */
/* disable training pattern generator */ for (i = 0; i < link.num_lanes; i++) {
unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
for (i = 0; i < link.num_lanes; i++) { SOR_DP_TPG_SCRAMBLER_GALIOS |
unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | SOR_DP_TPG_PATTERN_NONE;
SOR_DP_TPG_SCRAMBLER_GALIOS | value = (value << 8) | lane;
SOR_DP_TPG_PATTERN_NONE;
value = (value << 8) | lane;
}
tegra_sor_writel(sor, value, SOR_DP_TPG);
err = tegra_sor_dp_train_fast(sor, &link);
if (err < 0) {
dev_err(sor->dev, "DP fast link training failed: %d\n",
err);
}
dev_dbg(sor->dev, "fast link training succeeded\n");
} }
tegra_sor_writel(sor, value, SOR_DP_TPG);
err = tegra_sor_dp_train_fast(sor, &link);
if (err < 0)
dev_err(sor->dev, "DP fast link training failed: %d\n", err);
dev_dbg(sor->dev, "fast link training succeeded\n");
err = tegra_sor_power_up(sor, 250); err = tegra_sor_power_up(sor, 250);
if (err < 0) if (err < 0)
dev_err(sor->dev, "failed to power up SOR: %d\n", err); dev_err(sor->dev, "failed to power up SOR: %d\n", err);