From a2e7f6c48740bac078863227ce91a40f65d428c9 Mon Sep 17 00:00:00 2001 From: Sandie Cao Date: Mon, 24 Mar 2025 10:09:58 +0800 Subject: [PATCH 1/6] riscv: dts: starfive: fml13v01: enable USB 3.0 port Add usb_cdns3 and usb0_pins configuration to support super speed USB device on the FML13V01 board. Signed-off-by: Sandie Cao Tested-by: Maud Spierings Reviewed-by: Emil Renner Berthing Signed-off-by: Conor Dooley --- .../jh7110-deepcomputing-fml13v01.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts b/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts index 8d9ce8b69a71..f2857d021d68 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts +++ b/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts @@ -43,9 +43,28 @@ GPOEN_DISABLE, slew-rate = <0>; }; }; + + usb0_pins: usb0-0 { + vbus-pins { + pinmux = ; + bias-disable; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; }; &usb0 { dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&usb0_pins>; status = "okay"; }; + +&usb_cdns3 { + phys = <&usbphy0>, <&pciephy0>; + phy-names = "cdns3,usb2-phy", "cdns3,usb3-phy"; +}; From 71385a893cea3e3bc752aa75e3e616073cda7889 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 24 Apr 2025 14:06:05 +0800 Subject: [PATCH 2/6] riscv: dts: starfive: jh7110-common: use macros for MMC0 pins The pin names of MMC0 pinmux is defined in the pinctrl dt binding header associated with starfive,jh7110-pinctrl . Include the header file and use these names instead of raw numbers for defining MMC0 pinmux. Signed-off-by: Icenowy Zheng Reviewed-by: Emil Renner Berthing Signed-off-by: Conor Dooley --- .../boot/dts/starfive/jh7110-common.dtsi | 21 ++++++++++--------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi index c2f70f5e2918..a2c72b385a90 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi @@ -8,6 +8,7 @@ #include "jh7110.dtsi" #include "jh7110-pinfunc.h" #include +#include / { aliases { @@ -428,16 +429,16 @@ GPOEN_ENABLE, }; mmc-pins { - pinmux = , - , - , - , - , - , - , - , - , - ; + pinmux = , + , + , + , + , + , + , + , + , + ; bias-pull-up; drive-strength = <12>; input-enable; From 724a6718ce216f904192211f71973643f97384ec Mon Sep 17 00:00:00 2001 From: E Shattow Date: Fri, 2 May 2025 03:30:41 -0700 Subject: [PATCH 3/6] riscv: dts: starfive: jh7110-common: add CPU BUS PERH QSPI clocks to syscrg Add syscrg clock assignments for CPU, BUS, PERH, and QSPI as required by boot loader before kernel. Signed-off-by: E Shattow Reviewed-by: Emil Renner Berthing Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi index a2c72b385a90..cf1ee98454d6 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi @@ -354,9 +354,17 @@ &spi0 { }; &syscrg { - assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>, + assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>, + <&syscrg JH7110_SYSCLK_BUS_ROOT>, + <&syscrg JH7110_SYSCLK_PERH_ROOT>, + <&syscrg JH7110_SYSCLK_QSPI_REF>, + <&syscrg JH7110_SYSCLK_CPU_CORE>, <&pllclk JH7110_PLLCLK_PLL0_OUT>; - assigned-clock-rates = <500000000>, <1500000000>; + assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>, + <&pllclk JH7110_PLLCLK_PLL2_OUT>, + <&pllclk JH7110_PLLCLK_PLL2_OUT>, + <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>; + assigned-clock-rates = <0>, <0>, <0>, <0>, <500000000>, <1500000000>; }; &sysgpio { From 59404dceb303712faa9507b27c6fb14d8629c528 Mon Sep 17 00:00:00 2001 From: E Shattow Date: Fri, 2 May 2025 03:30:42 -0700 Subject: [PATCH 4/6] riscv: dts: starfive: jh7110-common: qspi flash setting read-delay 2 cycles max 100MHz Use qspi flash read-delay and spi-max-frequency settings compatible with U-Boot bootloader. Observations from testing on Pine64 Star64 hardware within U-Boot bootloader and read-delay=2 are spi-max-frequency less than 49.8MHz fails to write, corrupt data writes at 25MHz to 49.799999MHz, and valid data writes at 49.8MHz to 100MHz (not tested above 100MHz). No valid spi-max-frequency was found for 1 Reviewed-by: Hal Feng Acked-by: Emil Renner Berthing Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi index cf1ee98454d6..0d6932220968 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi @@ -318,8 +318,8 @@ &qspi { nor_flash: flash@0 { compatible = "jedec,spi-nor"; reg = <0>; - cdns,read-delay = <5>; - spi-max-frequency = <12000000>; + cdns,read-delay = <2>; + spi-max-frequency = <100000000>; cdns,tshsl-ns = <1>; cdns,tsd2d-ns = <1>; cdns,tchsh-ns = <1>; From 635918111453aa5c6c74d9dec9fe1f2037e531ed Mon Sep 17 00:00:00 2001 From: E Shattow Date: Fri, 2 May 2025 03:30:43 -0700 Subject: [PATCH 5/6] riscv: dts: starfive: jh7110-common: add eeprom node to i2c5 StarFive VisionFive2 and similar JH7110 boards have an eeprom compatible with Atmel 24c04. Add the node so this may be used with the at24 driver. Signed-off-by: E Shattow Reviewed-by: Hal Feng Reviewed-by: Emil Renner Berthing Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi index 0d6932220968..e7286c918c9b 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi @@ -246,6 +246,12 @@ emmc_vdd: aldo4 { }; }; }; + + eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + pagesize = <16>; + }; }; &i2c6 { From d50108706a63dfd896db42172bf9f6aebec219c5 Mon Sep 17 00:00:00 2001 From: E Shattow Date: Fri, 2 May 2025 03:30:44 -0700 Subject: [PATCH 6/6] riscv: dts: starfive: jh7110-common: bootph-pre-ram hinting needed by boot loader Add bootph-pre-ram hinting to jh7110-common.dtsi: - i2c5_pins and i2c-pins subnode for connection to eeprom - eeprom node - qspi flash configuration subnode - memory node - mmc0 for eMMC - mmc1 for SD Card - uart0 for serial console With this the U-Boot SPL secondary program loader may drop such overrides. Signed-off-by: E Shattow Acked-by: Emil Renner Berthing Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi index e7286c918c9b..4baeb981d4df 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi @@ -29,6 +29,7 @@ chosen { memory@40000000 { device_type = "memory"; reg = <0x0 0x40000000 0x1 0x0>; + bootph-pre-ram; }; gpio-restart { @@ -250,6 +251,7 @@ emmc_vdd: aldo4 { eeprom@50 { compatible = "atmel,24c04"; reg = <0x50>; + bootph-pre-ram; pagesize = <16>; }; }; @@ -269,6 +271,7 @@ &mmc0 { assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>; assigned-clock-rates = <50000000>; bus-width = <8>; + bootph-pre-ram; cap-mmc-highspeed; mmc-ddr-1_8v; mmc-hs200-1_8v; @@ -286,6 +289,7 @@ &mmc1 { assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>; assigned-clock-rates = <50000000>; bus-width = <4>; + bootph-pre-ram; no-sdio; no-mmc; cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>; @@ -324,6 +328,7 @@ &qspi { nor_flash: flash@0 { compatible = "jedec,spi-nor"; reg = <0>; + bootph-pre-ram; cdns,read-delay = <2>; spi-max-frequency = <100000000>; cdns,tshsl-ns = <1>; @@ -403,6 +408,8 @@ GPOEN_SYS_I2C2_DATA, }; i2c5_pins: i2c5-0 { + bootph-pre-ram; + i2c-pins { pinmux = , GPOEN_SYS_I2C5_DATA, GPI_SYS_I2C5_DATA)>; bias-disable; /* external pull-up */ + bootph-pre-ram; input-enable; input-schmitt-enable; }; @@ -639,6 +647,7 @@ GPOEN_DISABLE, }; &uart0 { + bootph-pre-ram; pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; status = "okay";